1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_ethdev_pci.h>
9 #include <rte_malloc.h>
11 #include <rte_mbuf_pool_ops.h>
12 #include <rte_mempool.h>
14 #include "otx2_ethdev.h"
15 #include "otx2_ethdev_sec.h"
17 static inline uint64_t
18 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
20 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
22 if (otx2_dev_is_vf(dev) ||
23 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)
24 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
29 static inline uint64_t
30 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
32 uint64_t capa = NIX_TX_OFFLOAD_CAPA;
34 /* TSO not supported for earlier chip revisions */
35 if (otx2_dev_is_96xx_A0(dev) || otx2_dev_is_95xx_Ax(dev))
36 capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
37 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
38 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
39 DEV_TX_OFFLOAD_GRE_TNL_TSO);
43 static const struct otx2_dev_ops otx2_dev_ops = {
44 .link_status_update = otx2_eth_dev_link_status_update,
45 .ptp_info_update = otx2_eth_dev_ptp_info_update
49 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
51 struct otx2_mbox *mbox = dev->mbox;
52 struct nix_lf_alloc_req *req;
53 struct nix_lf_alloc_rsp *rsp;
56 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
60 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
61 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
62 req->xqe_sz = NIX_XQESZ_W16;
63 req->rss_sz = dev->rss_info.rss_size;
64 req->rss_grps = NIX_RSS_GRPS;
65 req->npa_func = otx2_npa_pf_func_get();
66 req->sso_func = otx2_sso_pf_func_get();
67 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
68 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
69 DEV_RX_OFFLOAD_UDP_CKSUM)) {
70 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
71 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
73 req->rx_cfg |= (BIT_ULL(32 /* DROP_RE */) |
74 BIT_ULL(33 /* Outer L2 Length */) |
75 BIT_ULL(38 /* Inner L4 UDP Length */) |
76 BIT_ULL(39 /* Inner L3 Length */) |
77 BIT_ULL(40 /* Outer L4 UDP Length */) |
78 BIT_ULL(41 /* Outer L3 Length */));
80 if (dev->rss_tag_as_xor == 0)
81 req->flags = NIX_LF_RSS_TAG_LSB_AS_ADDER;
83 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
87 dev->sqb_size = rsp->sqb_size;
88 dev->tx_chan_base = rsp->tx_chan_base;
89 dev->rx_chan_base = rsp->rx_chan_base;
90 dev->rx_chan_cnt = rsp->rx_chan_cnt;
91 dev->tx_chan_cnt = rsp->tx_chan_cnt;
92 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
93 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
94 dev->lf_tx_stats = rsp->lf_tx_stats;
95 dev->lf_rx_stats = rsp->lf_rx_stats;
96 dev->cints = rsp->cints;
97 dev->qints = rsp->qints;
98 dev->npc_flow.channel = dev->rx_chan_base;
99 dev->ptp_en = rsp->hw_rx_tstamp_en;
105 nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev, bool enable)
107 struct otx2_mbox *mbox = dev->mbox;
108 struct npc_set_pkind *req;
109 struct msg_resp *rsp;
112 if (dev->npc_flow.switch_header_type == 0)
115 if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_LEN_90B &&
116 !otx2_dev_is_sdp(dev)) {
117 otx2_err("chlen90b is not supported on non-SDP device");
121 /* Notify AF about higig2 config */
122 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
123 req->mode = dev->npc_flow.switch_header_type;
125 req->mode = OTX2_PRIV_FLAGS_DEFAULT;
127 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
130 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
131 req->mode = dev->npc_flow.switch_header_type;
133 req->mode = OTX2_PRIV_FLAGS_DEFAULT;
135 return otx2_mbox_process_msg(mbox, (void *)&rsp);
139 nix_lf_free(struct otx2_eth_dev *dev)
141 struct otx2_mbox *mbox = dev->mbox;
142 struct nix_lf_free_req *req;
143 struct ndc_sync_op *ndc_req;
146 /* Sync NDC-NIX for LF */
147 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
148 ndc_req->nix_lf_tx_sync = 1;
149 ndc_req->nix_lf_rx_sync = 1;
150 rc = otx2_mbox_process(mbox);
152 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
154 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
155 /* Let AF driver free all this nix lf's
156 * NPC entries allocated using NPC MBOX.
160 return otx2_mbox_process(mbox);
164 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
166 struct otx2_mbox *mbox = dev->mbox;
168 if (otx2_dev_is_vf_or_sdp(dev))
171 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
173 return otx2_mbox_process(mbox);
177 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
179 struct otx2_mbox *mbox = dev->mbox;
181 if (otx2_dev_is_vf_or_sdp(dev))
184 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
186 return otx2_mbox_process(mbox);
190 npc_rx_enable(struct otx2_eth_dev *dev)
192 struct otx2_mbox *mbox = dev->mbox;
194 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
196 return otx2_mbox_process(mbox);
200 npc_rx_disable(struct otx2_eth_dev *dev)
202 struct otx2_mbox *mbox = dev->mbox;
204 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
206 return otx2_mbox_process(mbox);
210 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
212 struct otx2_mbox *mbox = dev->mbox;
214 if (otx2_dev_is_vf_or_sdp(dev))
217 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
219 return otx2_mbox_process(mbox);
223 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
225 struct otx2_mbox *mbox = dev->mbox;
227 if (en && otx2_dev_is_vf_or_sdp(dev))
231 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
233 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
235 return otx2_mbox_process(mbox);
239 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
241 struct otx2_mbox *mbox = dev->mbox;
243 if (otx2_dev_is_vf_or_sdp(dev))
246 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
248 return otx2_mbox_process(mbox);
252 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
258 static inline uint32_t
259 nix_qsize_to_val(enum nix_q_size_e qsize)
261 return (16UL << (qsize * 2));
264 static inline enum nix_q_size_e
265 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
269 if (otx2_ethdev_fixup_is_min_4k_q(dev))
274 for (; i < nix_q_size_max; i++)
275 if (val <= nix_qsize_to_val(i))
278 if (i >= nix_q_size_max)
279 i = nix_q_size_max - 1;
285 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
286 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
288 struct otx2_mbox *mbox = dev->mbox;
289 const struct rte_memzone *rz;
290 uint32_t ring_size, cq_size;
291 struct nix_aq_enq_req *aq;
296 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
297 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
298 NIX_CQ_ALIGN, dev->node);
300 otx2_err("Failed to allocate mem for cq hw ring");
304 memset(rz->addr, 0, rz->len);
305 rxq->desc = (uintptr_t)rz->addr;
306 rxq->qmask = cq_size - 1;
308 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
310 aq->ctype = NIX_AQ_CTYPE_CQ;
311 aq->op = NIX_AQ_INSTOP_INIT;
315 aq->cq.qsize = rxq->qsize;
316 aq->cq.base = rz->iova;
317 aq->cq.avg_level = 0xff;
318 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
319 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
321 /* Many to one reduction */
322 aq->cq.qint_idx = qid % dev->qints;
323 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
324 aq->cq.cint_idx = qid;
326 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
327 const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
328 uint16_t min_rx_drop;
330 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
331 aq->cq.drop = min_rx_drop;
333 rxq->cq_drop = min_rx_drop;
335 rxq->cq_drop = NIX_CQ_THRESH_LEVEL;
336 aq->cq.drop = rxq->cq_drop;
340 /* TX pause frames enable flowctrl on RX side */
341 if (dev->fc_info.tx_pause) {
342 /* Single bpid is allocated for all rx channels for now */
343 aq->cq.bpid = dev->fc_info.bpid[0];
344 aq->cq.bp = rxq->cq_drop;
348 rc = otx2_mbox_process(mbox);
350 otx2_err("Failed to init cq context");
354 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
356 aq->ctype = NIX_AQ_CTYPE_RQ;
357 aq->op = NIX_AQ_INSTOP_INIT;
361 if (rxq->offloads & DEV_RX_OFFLOAD_SECURITY)
362 aq->rq.ipsech_ena = 1;
364 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
366 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
367 first_skip = (sizeof(struct rte_mbuf));
368 first_skip += RTE_PKTMBUF_HEADROOM;
369 first_skip += rte_pktmbuf_priv_size(mp);
370 rxq->data_off = first_skip;
372 first_skip /= 8; /* Expressed in number of dwords */
373 aq->rq.first_skip = first_skip;
374 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
375 aq->rq.flow_tagw = 32; /* 32-bits */
376 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
377 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
378 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
379 aq->rq.lpb_sizem1 /= 8;
380 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
382 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
383 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
384 aq->rq.rq_int_ena = 0;
385 /* Many to one reduction */
386 aq->rq.qint_idx = qid % dev->qints;
388 aq->rq.xqe_drop_ena = 1;
390 rc = otx2_mbox_process(mbox);
392 otx2_err("Failed to init rq context");
402 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
403 struct otx2_eth_rxq *rxq, const bool enb)
405 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
406 struct otx2_mbox *mbox = dev->mbox;
407 struct nix_aq_enq_req *aq;
409 /* Pkts will be dropped silently if RQ is disabled */
410 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
412 aq->ctype = NIX_AQ_CTYPE_RQ;
413 aq->op = NIX_AQ_INSTOP_WRITE;
416 aq->rq_mask.ena = ~(aq->rq_mask.ena);
418 return otx2_mbox_process(mbox);
422 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
424 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
425 struct otx2_mbox *mbox = dev->mbox;
426 struct nix_aq_enq_req *aq;
429 /* RQ is already disabled */
431 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
433 aq->ctype = NIX_AQ_CTYPE_CQ;
434 aq->op = NIX_AQ_INSTOP_WRITE;
437 aq->cq_mask.ena = ~(aq->cq_mask.ena);
439 rc = otx2_mbox_process(mbox);
441 otx2_err("Failed to disable cq context");
449 nix_get_data_off(struct otx2_eth_dev *dev)
451 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
455 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
457 struct rte_mbuf mb_def;
460 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
461 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
462 offsetof(struct rte_mbuf, data_off) != 2);
463 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
464 offsetof(struct rte_mbuf, data_off) != 4);
465 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
466 offsetof(struct rte_mbuf, data_off) != 6);
468 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
469 mb_def.port = port_id;
470 rte_mbuf_refcnt_set(&mb_def, 1);
472 /* Prevent compiler reordering: rearm_data covers previous fields */
473 rte_compiler_barrier();
474 tmp = (uint64_t *)&mb_def.rearm_data;
480 otx2_nix_rx_queue_release(void *rx_queue)
482 struct otx2_eth_rxq *rxq = rx_queue;
487 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
488 nix_cq_rq_uninit(rxq->eth_dev, rxq);
493 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
494 uint16_t nb_desc, unsigned int socket,
495 const struct rte_eth_rxconf *rx_conf,
496 struct rte_mempool *mp)
498 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
499 struct rte_mempool_ops *ops;
500 struct otx2_eth_rxq *rxq;
501 const char *platform_ops;
502 enum nix_q_size_e qsize;
508 /* Compile time check to make sure all fast path elements in a CL */
509 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
512 if (rx_conf->rx_deferred_start == 1) {
513 otx2_err("Deferred Rx start is not supported");
517 platform_ops = rte_mbuf_platform_mempool_ops();
518 /* This driver needs octeontx2_npa mempool ops to work */
519 ops = rte_mempool_get_ops(mp->ops_index);
520 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
521 otx2_err("mempool ops should be of octeontx2_npa type");
525 if (mp->pool_id == 0) {
526 otx2_err("Invalid pool_id");
530 /* Free memory prior to re-allocation if needed */
531 if (eth_dev->data->rx_queues[rq] != NULL) {
532 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
533 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
534 eth_dev->data->rx_queues[rq] = NULL;
537 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
538 dev->rx_offloads |= offloads;
540 /* Find the CQ queue size */
541 qsize = nix_qsize_clampup_get(dev, nb_desc);
542 /* Allocate rxq memory */
543 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
545 otx2_err("Failed to allocate rq=%d", rq);
550 rxq->eth_dev = eth_dev;
552 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
553 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
554 rxq->wdata = (uint64_t)rq << 32;
555 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
556 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
557 eth_dev->data->port_id);
558 rxq->offloads = offloads;
560 rxq->qlen = nix_qsize_to_val(qsize);
562 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
563 rxq->tstamp = &dev->tstamp;
565 /* Alloc completion queue */
566 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
568 otx2_err("Failed to allocate rxq=%u", rq);
572 rxq->qconf.socket_id = socket;
573 rxq->qconf.nb_desc = nb_desc;
574 rxq->qconf.mempool = mp;
575 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
577 nix_rx_queue_reset(rxq);
578 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
579 rq, mp->name, qsize, nb_desc, rxq->qlen);
581 eth_dev->data->rx_queues[rq] = rxq;
582 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
584 /* Calculating delta and freq mult between PTP HI clock and tsc.
585 * These are needed in deriving raw clock value from tsc counter.
586 * read_clock eth op returns raw clock value.
588 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
589 otx2_ethdev_is_ptp_en(dev)) {
590 rc = otx2_nix_raw_clock_tsc_conv(dev);
592 otx2_err("Failed to calculate delta and freq mult");
600 otx2_nix_rx_queue_release(rxq);
605 static inline uint8_t
606 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
609 * Maximum three segments can be supported with W8, Choose
610 * NIX_MAXSQESZ_W16 for multi segment offload.
612 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
613 return NIX_MAXSQESZ_W16;
615 return NIX_MAXSQESZ_W8;
619 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
621 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
622 struct rte_eth_dev_data *data = eth_dev->data;
623 struct rte_eth_conf *conf = &data->dev_conf;
624 struct rte_eth_rxmode *rxmode = &conf->rxmode;
627 if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
628 (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
629 flags |= NIX_RX_OFFLOAD_RSS_F;
631 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
632 DEV_RX_OFFLOAD_UDP_CKSUM))
633 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
635 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
636 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
637 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
639 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
640 flags |= NIX_RX_MULTI_SEG_F;
642 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
643 DEV_RX_OFFLOAD_QINQ_STRIP))
644 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
646 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
647 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
649 if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY)
650 flags |= NIX_RX_OFFLOAD_SECURITY_F;
652 if (!dev->ptype_disable)
653 flags |= NIX_RX_OFFLOAD_PTYPE_F;
659 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
661 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
662 uint64_t conf = dev->tx_offloads;
665 /* Fastpath is dependent on these enums */
666 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
667 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
668 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
669 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
670 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
671 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
672 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
673 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
674 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
675 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
676 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
677 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
678 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
679 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
680 offsetof(struct rte_mbuf, buf_iova) + 8);
681 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
682 offsetof(struct rte_mbuf, buf_iova) + 16);
683 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
684 offsetof(struct rte_mbuf, ol_flags) + 12);
685 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
686 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
688 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
689 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
690 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
692 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
693 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
694 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
696 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
697 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
698 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
699 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
700 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
702 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
703 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
705 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
706 flags |= NIX_TX_MULTI_SEG_F;
708 /* Enable Inner checksum for TSO */
709 if (conf & DEV_TX_OFFLOAD_TCP_TSO)
710 flags |= (NIX_TX_OFFLOAD_TSO_F |
711 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
713 /* Enable Inner and Outer checksum for Tunnel TSO */
714 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
715 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
716 DEV_TX_OFFLOAD_GRE_TNL_TSO))
717 flags |= (NIX_TX_OFFLOAD_TSO_F |
718 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
719 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
721 if (conf & DEV_TX_OFFLOAD_SECURITY)
722 flags |= NIX_TX_OFFLOAD_SECURITY_F;
724 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
725 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
731 nix_sq_init(struct otx2_eth_txq *txq)
733 struct otx2_eth_dev *dev = txq->dev;
734 struct otx2_mbox *mbox = dev->mbox;
735 struct nix_aq_enq_req *sq;
740 if (txq->sqb_pool->pool_id == 0)
743 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
745 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
749 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
751 sq->ctype = NIX_AQ_CTYPE_SQ;
752 sq->op = NIX_AQ_INSTOP_INIT;
753 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
756 sq->sq.smq_rr_quantum = rr_quantum;
757 sq->sq.default_chan = dev->tx_chan_base;
758 sq->sq.sqe_stype = NIX_STYPE_STF;
760 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
761 sq->sq.sqe_stype = NIX_STYPE_STP;
763 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
764 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
765 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
766 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
767 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
769 /* Many to one reduction */
770 sq->sq.qint_idx = txq->sq % dev->qints;
772 return otx2_mbox_process(mbox);
776 nix_sq_uninit(struct otx2_eth_txq *txq)
778 struct otx2_eth_dev *dev = txq->dev;
779 struct otx2_mbox *mbox = dev->mbox;
780 struct ndc_sync_op *ndc_req;
781 struct nix_aq_enq_rsp *rsp;
782 struct nix_aq_enq_req *aq;
783 uint16_t sqes_per_sqb;
787 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
789 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
791 aq->ctype = NIX_AQ_CTYPE_SQ;
792 aq->op = NIX_AQ_INSTOP_READ;
794 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
798 /* Check if sq is already cleaned up */
803 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
805 aq->ctype = NIX_AQ_CTYPE_SQ;
806 aq->op = NIX_AQ_INSTOP_WRITE;
808 aq->sq_mask.ena = ~aq->sq_mask.ena;
811 rc = otx2_mbox_process(mbox);
815 /* Read SQ and free sqb's */
816 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
818 aq->ctype = NIX_AQ_CTYPE_SQ;
819 aq->op = NIX_AQ_INSTOP_READ;
821 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
826 otx2_err("SQ has pending sqe's");
828 count = aq->sq.sqb_count;
829 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
830 /* Free SQB's that are used */
831 sqb_buf = (void *)rsp->sq.head_sqb;
835 next_sqb = *(void **)((uintptr_t)sqb_buf + (uint32_t)
836 ((sqes_per_sqb - 1) *
837 nix_sq_max_sqe_sz(txq)));
838 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
844 /* Free next to use sqb */
845 if (rsp->sq.next_sqb)
846 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
849 /* Sync NDC-NIX-TX for LF */
850 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
851 ndc_req->nix_lf_tx_sync = 1;
852 rc = otx2_mbox_process(mbox);
854 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
860 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
862 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
863 struct npa_aq_enq_req *aura_req;
865 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
866 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
867 aura_req->ctype = NPA_AQ_CTYPE_AURA;
868 aura_req->op = NPA_AQ_INSTOP_WRITE;
870 aura_req->aura.limit = nb_sqb_bufs;
871 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
873 return otx2_mbox_process(npa_lf->mbox);
877 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
879 struct otx2_eth_dev *dev = txq->dev;
880 uint16_t sqes_per_sqb, nb_sqb_bufs;
881 char name[RTE_MEMPOOL_NAMESIZE];
882 struct rte_mempool_objsz sz;
883 struct npa_aura_s *aura;
884 uint32_t tmp, blk_sz;
886 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
887 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
888 blk_sz = dev->sqb_size;
890 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
891 sqes_per_sqb = (dev->sqb_size / 8) / 16;
893 sqes_per_sqb = (dev->sqb_size / 8) / 8;
895 nb_sqb_bufs = nb_desc / sqes_per_sqb;
896 /* Clamp up to devarg passed SQB count */
897 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_DEF_SQB,
898 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
900 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
902 MEMPOOL_F_NO_SPREAD);
903 txq->nb_sqb_bufs = nb_sqb_bufs;
904 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
905 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
906 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
907 txq->nb_sqb_bufs_adj =
908 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
910 if (txq->sqb_pool == NULL) {
911 otx2_err("Failed to allocate sqe mempool");
915 memset(aura, 0, sizeof(*aura));
917 aura->fc_addr = txq->fc_iova;
918 aura->fc_hyst_bits = 0; /* Store count on all updates */
919 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
920 otx2_err("Failed to set ops for sqe mempool");
923 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
924 otx2_err("Failed to populate sqe mempool");
928 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
929 if (dev->sqb_size != sz.elt_size) {
930 otx2_err("sqe pool block size is not expected %d != %d",
935 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
943 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
945 struct nix_send_ext_s *send_hdr_ext;
946 struct nix_send_hdr_s *send_hdr;
947 struct nix_send_mem_s *send_mem;
948 union nix_send_sg_s *sg;
950 /* Initialize the fields based on basic single segment packet */
951 memset(&txq->cmd, 0, sizeof(txq->cmd));
953 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
954 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
955 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
956 send_hdr->w0.sizem1 = 2;
958 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
959 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
960 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
961 /* Default: one seg packet would have:
962 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
965 send_hdr->w0.sizem1 = 3;
966 send_hdr_ext->w0.tstmp = 1;
968 /* To calculate the offset for send_mem,
969 * send_hdr->w0.sizem1 * 2
971 send_mem = (struct nix_send_mem_s *)(txq->cmd +
972 (send_hdr->w0.sizem1 << 1));
973 send_mem->subdc = NIX_SUBDC_MEM;
974 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
975 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
977 sg = (union nix_send_sg_s *)&txq->cmd[4];
979 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
980 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
981 send_hdr->w0.sizem1 = 1;
982 sg = (union nix_send_sg_s *)&txq->cmd[2];
985 send_hdr->w0.sq = txq->sq;
986 sg->subdc = NIX_SUBDC_SG;
988 sg->ld_type = NIX_SENDLDTYPE_LDD;
994 otx2_nix_tx_queue_release(void *_txq)
996 struct otx2_eth_txq *txq = _txq;
997 struct rte_eth_dev *eth_dev;
1002 eth_dev = txq->dev->eth_dev;
1004 otx2_nix_dbg("Releasing txq %u", txq->sq);
1006 /* Flush and disable tm */
1007 otx2_nix_sq_flush_pre(txq, eth_dev->data->dev_started);
1009 /* Free sqb's and disable sq */
1012 if (txq->sqb_pool) {
1013 rte_mempool_free(txq->sqb_pool);
1014 txq->sqb_pool = NULL;
1016 otx2_nix_sq_flush_post(txq);
1022 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
1023 uint16_t nb_desc, unsigned int socket_id,
1024 const struct rte_eth_txconf *tx_conf)
1026 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1027 const struct rte_memzone *fc;
1028 struct otx2_eth_txq *txq;
1034 /* Compile time check to make sure all fast path elements in a CL */
1035 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
1037 if (tx_conf->tx_deferred_start) {
1038 otx2_err("Tx deferred start is not supported");
1042 /* Free memory prior to re-allocation if needed. */
1043 if (eth_dev->data->tx_queues[sq] != NULL) {
1044 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
1045 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
1046 eth_dev->data->tx_queues[sq] = NULL;
1049 /* Find the expected offloads for this queue */
1050 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
1052 /* Allocating tx queue data structure */
1053 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
1054 OTX2_ALIGN, socket_id);
1056 otx2_err("Failed to alloc txq=%d", sq);
1062 txq->sqb_pool = NULL;
1063 txq->offloads = offloads;
1064 dev->tx_offloads |= offloads;
1067 * Allocate memory for flow control updates from HW.
1068 * Alloc one cache line, so that fits all FC_STYPE modes.
1070 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
1071 OTX2_ALIGN + sizeof(struct npa_aura_s),
1072 OTX2_ALIGN, dev->node);
1074 otx2_err("Failed to allocate mem for fcmem");
1078 txq->fc_iova = fc->iova;
1079 txq->fc_mem = fc->addr;
1081 /* Initialize the aura sqb pool */
1082 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
1084 otx2_err("Failed to alloc sqe pool rc=%d", rc);
1088 /* Initialize the SQ */
1089 rc = nix_sq_init(txq);
1091 otx2_err("Failed to init sq=%d context", sq);
1095 txq->fc_cache_pkts = 0;
1096 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
1097 /* Evenly distribute LMT slot for each sq */
1098 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
1100 txq->qconf.socket_id = socket_id;
1101 txq->qconf.nb_desc = nb_desc;
1102 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
1104 otx2_nix_form_default_desc(txq);
1106 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
1107 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
1108 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
1109 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
1110 eth_dev->data->tx_queues[sq] = txq;
1111 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
1115 otx2_nix_tx_queue_release(txq);
1121 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1123 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1124 struct otx2_eth_qconf *tx_qconf = NULL;
1125 struct otx2_eth_qconf *rx_qconf = NULL;
1126 struct otx2_eth_txq **txq;
1127 struct otx2_eth_rxq **rxq;
1128 int i, nb_rxq, nb_txq;
1130 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1131 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1133 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1134 if (tx_qconf == NULL) {
1135 otx2_err("Failed to allocate memory for tx_qconf");
1139 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1140 if (rx_qconf == NULL) {
1141 otx2_err("Failed to allocate memory for rx_qconf");
1145 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1146 for (i = 0; i < nb_txq; i++) {
1147 if (txq[i] == NULL) {
1148 tx_qconf[i].valid = false;
1149 otx2_info("txq[%d] is already released", i);
1152 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1153 tx_qconf[i].valid = true;
1154 otx2_nix_tx_queue_release(txq[i]);
1155 eth_dev->data->tx_queues[i] = NULL;
1158 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1159 for (i = 0; i < nb_rxq; i++) {
1160 if (rxq[i] == NULL) {
1161 rx_qconf[i].valid = false;
1162 otx2_info("rxq[%d] is already released", i);
1165 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1166 rx_qconf[i].valid = true;
1167 otx2_nix_rx_queue_release(rxq[i]);
1168 eth_dev->data->rx_queues[i] = NULL;
1171 dev->tx_qconf = tx_qconf;
1172 dev->rx_qconf = rx_qconf;
1185 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1187 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1188 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1189 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1190 struct otx2_eth_txq **txq;
1191 struct otx2_eth_rxq **rxq;
1192 int rc, i, nb_rxq, nb_txq;
1194 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1195 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1198 /* Setup tx & rx queues with previous configuration so
1199 * that the queues can be functional in cases like ports
1200 * are started without re configuring queues.
1202 * Usual re config sequence is like below:
1203 * port_configure() {
1208 * queue_configure() {
1215 * In some application's control path, queue_configure() would
1216 * NOT be invoked for TXQs/RXQs in port_configure().
1217 * In such cases, queues can be functional after start as the
1218 * queues are already setup in port_configure().
1220 for (i = 0; i < nb_txq; i++) {
1221 if (!tx_qconf[i].valid)
1223 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1224 tx_qconf[i].socket_id,
1225 &tx_qconf[i].conf.tx);
1227 otx2_err("Failed to setup tx queue rc=%d", rc);
1228 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1229 for (i -= 1; i >= 0; i--)
1230 otx2_nix_tx_queue_release(txq[i]);
1235 free(tx_qconf); tx_qconf = NULL;
1237 for (i = 0; i < nb_rxq; i++) {
1238 if (!rx_qconf[i].valid)
1240 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1241 rx_qconf[i].socket_id,
1242 &rx_qconf[i].conf.rx,
1243 rx_qconf[i].mempool);
1245 otx2_err("Failed to setup rx queue rc=%d", rc);
1246 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1247 for (i -= 1; i >= 0; i--)
1248 otx2_nix_rx_queue_release(rxq[i]);
1249 goto release_tx_queues;
1253 free(rx_qconf); rx_qconf = NULL;
1258 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1259 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1260 otx2_nix_tx_queue_release(txq[i]);
1271 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1273 RTE_SET_USED(queue);
1274 RTE_SET_USED(mbufs);
1281 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1283 /* These dummy functions are required for supporting
1284 * some applications which reconfigure queues without
1285 * stopping tx burst and rx burst threads(eg kni app)
1286 * When the queues context is saved, txq/rxqs are released
1287 * which caused app crash since rx/tx burst is still
1288 * on different lcores
1290 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1291 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1296 nix_lso_tcp(struct nix_lso_format_cfg *req, bool v4)
1298 volatile struct nix_lso_format *field;
1300 /* Format works only with TCP packet marked by OL3/OL4 */
1301 field = (volatile struct nix_lso_format *)&req->fields[0];
1302 req->field_mask = NIX_LSO_FIELD_MASK;
1303 /* Outer IPv4/IPv6 */
1304 field->layer = NIX_TXLAYER_OL3;
1305 field->offset = v4 ? 2 : 4;
1306 field->sizem1 = 1; /* 2B */
1307 field->alg = NIX_LSOALG_ADD_PAYLEN;
1311 field->layer = NIX_TXLAYER_OL3;
1314 /* Incremented linearly per segment */
1315 field->alg = NIX_LSOALG_ADD_SEGNUM;
1319 /* TCP sequence number update */
1320 field->layer = NIX_TXLAYER_OL4;
1322 field->sizem1 = 3; /* 4 bytes */
1323 field->alg = NIX_LSOALG_ADD_OFFSET;
1325 /* TCP flags field */
1326 field->layer = NIX_TXLAYER_OL4;
1329 field->alg = NIX_LSOALG_TCP_FLAGS;
1334 nix_lso_udp_tun_tcp(struct nix_lso_format_cfg *req,
1335 bool outer_v4, bool inner_v4)
1337 volatile struct nix_lso_format *field;
1339 field = (volatile struct nix_lso_format *)&req->fields[0];
1340 req->field_mask = NIX_LSO_FIELD_MASK;
1341 /* Outer IPv4/IPv6 len */
1342 field->layer = NIX_TXLAYER_OL3;
1343 field->offset = outer_v4 ? 2 : 4;
1344 field->sizem1 = 1; /* 2B */
1345 field->alg = NIX_LSOALG_ADD_PAYLEN;
1349 field->layer = NIX_TXLAYER_OL3;
1352 /* Incremented linearly per segment */
1353 field->alg = NIX_LSOALG_ADD_SEGNUM;
1357 /* Outer UDP length */
1358 field->layer = NIX_TXLAYER_OL4;
1361 field->alg = NIX_LSOALG_ADD_PAYLEN;
1364 /* Inner IPv4/IPv6 */
1365 field->layer = NIX_TXLAYER_IL3;
1366 field->offset = inner_v4 ? 2 : 4;
1367 field->sizem1 = 1; /* 2B */
1368 field->alg = NIX_LSOALG_ADD_PAYLEN;
1372 field->layer = NIX_TXLAYER_IL3;
1375 /* Incremented linearly per segment */
1376 field->alg = NIX_LSOALG_ADD_SEGNUM;
1380 /* TCP sequence number update */
1381 field->layer = NIX_TXLAYER_IL4;
1383 field->sizem1 = 3; /* 4 bytes */
1384 field->alg = NIX_LSOALG_ADD_OFFSET;
1387 /* TCP flags field */
1388 field->layer = NIX_TXLAYER_IL4;
1391 field->alg = NIX_LSOALG_TCP_FLAGS;
1396 nix_lso_tun_tcp(struct nix_lso_format_cfg *req,
1397 bool outer_v4, bool inner_v4)
1399 volatile struct nix_lso_format *field;
1401 field = (volatile struct nix_lso_format *)&req->fields[0];
1402 req->field_mask = NIX_LSO_FIELD_MASK;
1403 /* Outer IPv4/IPv6 len */
1404 field->layer = NIX_TXLAYER_OL3;
1405 field->offset = outer_v4 ? 2 : 4;
1406 field->sizem1 = 1; /* 2B */
1407 field->alg = NIX_LSOALG_ADD_PAYLEN;
1411 field->layer = NIX_TXLAYER_OL3;
1414 /* Incremented linearly per segment */
1415 field->alg = NIX_LSOALG_ADD_SEGNUM;
1419 /* Inner IPv4/IPv6 */
1420 field->layer = NIX_TXLAYER_IL3;
1421 field->offset = inner_v4 ? 2 : 4;
1422 field->sizem1 = 1; /* 2B */
1423 field->alg = NIX_LSOALG_ADD_PAYLEN;
1427 field->layer = NIX_TXLAYER_IL3;
1430 /* Incremented linearly per segment */
1431 field->alg = NIX_LSOALG_ADD_SEGNUM;
1435 /* TCP sequence number update */
1436 field->layer = NIX_TXLAYER_IL4;
1438 field->sizem1 = 3; /* 4 bytes */
1439 field->alg = NIX_LSOALG_ADD_OFFSET;
1442 /* TCP flags field */
1443 field->layer = NIX_TXLAYER_IL4;
1446 field->alg = NIX_LSOALG_TCP_FLAGS;
1451 nix_setup_lso_formats(struct otx2_eth_dev *dev)
1453 struct otx2_mbox *mbox = dev->mbox;
1454 struct nix_lso_format_cfg_rsp *rsp;
1455 struct nix_lso_format_cfg *req;
1459 /* Skip if TSO was not requested */
1460 if (!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F))
1465 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1466 nix_lso_tcp(req, true);
1467 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1471 base = rsp->lso_format_idx;
1472 if (base != NIX_LSO_FORMAT_IDX_TSOV4)
1474 dev->lso_base_idx = base;
1475 otx2_nix_dbg("tcpv4 lso fmt=%u", base);
1481 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1482 nix_lso_tcp(req, false);
1483 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1487 if (rsp->lso_format_idx != base + 1)
1489 otx2_nix_dbg("tcpv6 lso fmt=%u\n", base + 1);
1492 * IPv4/UDP/TUN HDR/IPv4/TCP LSO
1494 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1495 nix_lso_udp_tun_tcp(req, true, true);
1496 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1500 if (rsp->lso_format_idx != base + 2)
1502 otx2_nix_dbg("udp tun v4v4 fmt=%u\n", base + 2);
1505 * IPv4/UDP/TUN HDR/IPv6/TCP LSO
1507 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1508 nix_lso_udp_tun_tcp(req, true, false);
1509 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1513 if (rsp->lso_format_idx != base + 3)
1515 otx2_nix_dbg("udp tun v4v6 fmt=%u\n", base + 3);
1518 * IPv6/UDP/TUN HDR/IPv4/TCP LSO
1520 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1521 nix_lso_udp_tun_tcp(req, false, true);
1522 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1526 if (rsp->lso_format_idx != base + 4)
1528 otx2_nix_dbg("udp tun v6v4 fmt=%u\n", base + 4);
1531 * IPv6/UDP/TUN HDR/IPv6/TCP LSO
1533 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1534 nix_lso_udp_tun_tcp(req, false, false);
1535 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1538 if (rsp->lso_format_idx != base + 5)
1540 otx2_nix_dbg("udp tun v6v6 fmt=%u\n", base + 5);
1543 * IPv4/TUN HDR/IPv4/TCP LSO
1545 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1546 nix_lso_tun_tcp(req, true, true);
1547 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1551 if (rsp->lso_format_idx != base + 6)
1553 otx2_nix_dbg("tun v4v4 fmt=%u\n", base + 6);
1556 * IPv4/TUN HDR/IPv6/TCP LSO
1558 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1559 nix_lso_tun_tcp(req, true, false);
1560 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1564 if (rsp->lso_format_idx != base + 7)
1566 otx2_nix_dbg("tun v4v6 fmt=%u\n", base + 7);
1569 * IPv6/TUN HDR/IPv4/TCP LSO
1571 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1572 nix_lso_tun_tcp(req, false, true);
1573 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1577 if (rsp->lso_format_idx != base + 8)
1579 otx2_nix_dbg("tun v6v4 fmt=%u\n", base + 8);
1582 * IPv6/TUN HDR/IPv6/TCP LSO
1584 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1585 nix_lso_tun_tcp(req, false, false);
1586 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1589 if (rsp->lso_format_idx != base + 9)
1591 otx2_nix_dbg("tun v6v6 fmt=%u\n", base + 9);
1596 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1598 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1599 struct rte_eth_dev_data *data = eth_dev->data;
1600 struct rte_eth_conf *conf = &data->dev_conf;
1601 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1602 struct rte_eth_txmode *txmode = &conf->txmode;
1603 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1604 struct rte_ether_addr *ea;
1605 uint8_t nb_rxq, nb_txq;
1611 if (rte_eal_has_hugepages() == 0) {
1612 otx2_err("Huge page is not configured");
1613 goto fail_configure;
1616 if (conf->dcb_capability_en == 1) {
1617 otx2_err("dcb enable is not supported");
1618 goto fail_configure;
1621 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1622 otx2_err("Flow director is not supported");
1623 goto fail_configure;
1626 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1627 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1628 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1629 goto fail_configure;
1632 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1633 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1634 goto fail_configure;
1637 if (otx2_dev_is_Ax(dev) &&
1638 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1639 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1640 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1641 otx2_err("Outer IP and SCTP checksum unsupported");
1642 goto fail_configure;
1645 /* Free the resources allocated from the previous configure */
1646 if (dev->configured == 1) {
1647 otx2_eth_sec_fini(eth_dev);
1648 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1649 otx2_nix_vlan_fini(eth_dev);
1650 otx2_nix_mc_addr_list_uninstall(eth_dev);
1651 otx2_flow_free_all_resources(dev);
1652 oxt2_nix_unregister_queue_irqs(eth_dev);
1653 if (eth_dev->data->dev_conf.intr_conf.rxq)
1654 oxt2_nix_unregister_cq_irqs(eth_dev);
1655 nix_set_nop_rxtx_function(eth_dev);
1656 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1658 goto fail_configure;
1659 otx2_nix_tm_fini(eth_dev);
1663 dev->rx_offloads = rxmode->offloads;
1664 dev->tx_offloads = txmode->offloads;
1665 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1666 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1667 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1669 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1670 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1672 /* Alloc a nix lf */
1673 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1675 otx2_err("Failed to init nix_lf rc=%d", rc);
1679 otx2_nix_err_intr_enb_dis(eth_dev, true);
1680 otx2_nix_ras_intr_enb_dis(eth_dev, true);
1683 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
1684 otx2_err("Both PTP and switch header enabled");
1688 rc = nix_lf_switch_header_type_enable(dev, true);
1690 otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
1694 rc = nix_setup_lso_formats(dev);
1696 otx2_err("failed to setup nix lso format fields, rc=%d", rc);
1701 rc = otx2_nix_rss_config(eth_dev);
1703 otx2_err("Failed to configure rss rc=%d", rc);
1707 /* Init the default TM scheduler hierarchy */
1708 rc = otx2_nix_tm_init_default(eth_dev);
1710 otx2_err("Failed to init traffic manager rc=%d", rc);
1714 rc = otx2_nix_vlan_offload_init(eth_dev);
1716 otx2_err("Failed to init vlan offload rc=%d", rc);
1720 /* Register queue IRQs */
1721 rc = oxt2_nix_register_queue_irqs(eth_dev);
1723 otx2_err("Failed to register queue interrupts rc=%d", rc);
1727 /* Register cq IRQs */
1728 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1729 if (eth_dev->data->nb_rx_queues > dev->cints) {
1730 otx2_err("Rx interrupt cannot be enabled, rxq > %d",
1734 /* Rx interrupt feature cannot work with vector mode because,
1735 * vector mode doesn't process packets unless min 4 pkts are
1736 * received, while cq interrupts are generated even for 1 pkt
1739 dev->scalar_ena = true;
1741 rc = oxt2_nix_register_cq_irqs(eth_dev);
1743 otx2_err("Failed to register CQ interrupts rc=%d", rc);
1748 /* Configure loop back mode */
1749 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1751 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1755 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1757 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1761 /* Enable security */
1762 rc = otx2_eth_sec_init(eth_dev);
1766 rc = otx2_nix_flow_ctrl_init(eth_dev);
1768 otx2_err("Failed to init flow ctrl mode %d", rc);
1772 rc = otx2_nix_mc_addr_list_install(eth_dev);
1774 otx2_err("Failed to install mc address list rc=%d", rc);
1779 * Restore queue config when reconfigure followed by
1780 * reconfigure and no queue configure invoked from application case.
1782 if (dev->configured == 1) {
1783 rc = nix_restore_queue_cfg(eth_dev);
1785 goto uninstall_mc_list;
1788 /* Update the mac address */
1789 ea = eth_dev->data->mac_addrs;
1790 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1791 if (rte_is_zero_ether_addr(ea))
1792 rte_eth_random_addr((uint8_t *)ea);
1794 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1796 /* Apply new link configurations if changed */
1797 rc = otx2_apply_link_speed(eth_dev);
1799 otx2_err("Failed to set link configuration");
1800 goto uninstall_mc_list;
1803 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1804 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1805 " rx_flags=0x%x tx_flags=0x%x",
1806 eth_dev->data->port_id, ea_fmt, nb_rxq,
1807 nb_txq, dev->rx_offloads, dev->tx_offloads,
1808 dev->rx_offload_flags, dev->tx_offload_flags);
1811 dev->configured = 1;
1812 dev->configured_nb_rx_qs = data->nb_rx_queues;
1813 dev->configured_nb_tx_qs = data->nb_tx_queues;
1817 otx2_nix_mc_addr_list_uninstall(eth_dev);
1819 otx2_eth_sec_fini(eth_dev);
1821 oxt2_nix_unregister_cq_irqs(eth_dev);
1823 oxt2_nix_unregister_queue_irqs(eth_dev);
1825 otx2_nix_vlan_fini(eth_dev);
1827 otx2_nix_tm_fini(eth_dev);
1831 dev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);
1832 dev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);
1834 dev->configured = 0;
1839 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1841 struct rte_eth_dev_data *data = eth_dev->data;
1842 struct otx2_eth_txq *txq;
1845 txq = eth_dev->data->tx_queues[qidx];
1847 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1850 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1852 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1857 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1864 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1866 struct rte_eth_dev_data *data = eth_dev->data;
1867 struct otx2_eth_txq *txq;
1870 txq = eth_dev->data->tx_queues[qidx];
1872 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1875 txq->fc_cache_pkts = 0;
1877 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1879 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1884 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1891 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1893 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1894 struct rte_eth_dev_data *data = eth_dev->data;
1897 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1900 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1902 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1906 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1913 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1915 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1916 struct rte_eth_dev_data *data = eth_dev->data;
1919 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1922 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1924 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1928 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1935 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
1937 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1938 struct rte_mbuf *rx_pkts[32];
1939 struct otx2_eth_rxq *rxq;
1940 int count, i, j, rc;
1942 nix_lf_switch_header_type_enable(dev, false);
1943 nix_cgx_stop_link_event(dev);
1944 npc_rx_disable(dev);
1946 /* Stop rx queues and free up pkts pending */
1947 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1948 rc = otx2_nix_rx_queue_stop(eth_dev, i);
1952 rxq = eth_dev->data->rx_queues[i];
1953 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1955 for (j = 0; j < count; j++)
1956 rte_pktmbuf_free(rx_pkts[j]);
1957 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1961 /* Stop tx queues */
1962 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1963 otx2_nix_tx_queue_stop(eth_dev, i);
1967 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
1969 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1972 /* MTU recalculate should be avoided here if PTP is enabled by PF, as
1973 * otx2_nix_recalc_mtu would be invoked during otx2_nix_ptp_enable_vf
1976 if (eth_dev->data->nb_rx_queues != 0 && !otx2_ethdev_is_ptp_en(dev)) {
1977 rc = otx2_nix_recalc_mtu(eth_dev);
1982 /* Start rx queues */
1983 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1984 rc = otx2_nix_rx_queue_start(eth_dev, i);
1989 /* Start tx queues */
1990 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1991 rc = otx2_nix_tx_queue_start(eth_dev, i);
1996 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
1998 otx2_err("Failed to update flow ctrl mode %d", rc);
2002 /* Enable PTP if it was requested by the app or if it is already
2003 * enabled in PF owning this VF
2005 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
2006 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
2007 otx2_ethdev_is_ptp_en(dev))
2008 otx2_nix_timesync_enable(eth_dev);
2010 otx2_nix_timesync_disable(eth_dev);
2012 /* Update VF about data off shifted by 8 bytes if PTP already
2013 * enabled in PF owning this VF
2015 if (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))
2016 otx2_nix_ptp_enable_vf(eth_dev);
2018 rc = npc_rx_enable(dev);
2020 otx2_err("Failed to enable NPC rx %d", rc);
2024 otx2_nix_toggle_flag_link_cfg(dev, true);
2026 rc = nix_cgx_start_link_event(dev);
2028 otx2_err("Failed to start cgx link event %d", rc);
2032 otx2_nix_toggle_flag_link_cfg(dev, false);
2033 otx2_eth_set_tx_function(eth_dev);
2034 otx2_eth_set_rx_function(eth_dev);
2039 npc_rx_disable(dev);
2040 otx2_nix_toggle_flag_link_cfg(dev, false);
2044 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
2045 static void otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
2047 /* Initialize and register driver with DPDK Application */
2048 static const struct eth_dev_ops otx2_eth_dev_ops = {
2049 .dev_infos_get = otx2_nix_info_get,
2050 .dev_configure = otx2_nix_configure,
2051 .link_update = otx2_nix_link_update,
2052 .tx_queue_setup = otx2_nix_tx_queue_setup,
2053 .tx_queue_release = otx2_nix_tx_queue_release,
2054 .tm_ops_get = otx2_nix_tm_ops_get,
2055 .rx_queue_setup = otx2_nix_rx_queue_setup,
2056 .rx_queue_release = otx2_nix_rx_queue_release,
2057 .dev_start = otx2_nix_dev_start,
2058 .dev_stop = otx2_nix_dev_stop,
2059 .dev_close = otx2_nix_dev_close,
2060 .tx_queue_start = otx2_nix_tx_queue_start,
2061 .tx_queue_stop = otx2_nix_tx_queue_stop,
2062 .rx_queue_start = otx2_nix_rx_queue_start,
2063 .rx_queue_stop = otx2_nix_rx_queue_stop,
2064 .dev_set_link_up = otx2_nix_dev_set_link_up,
2065 .dev_set_link_down = otx2_nix_dev_set_link_down,
2066 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
2067 .dev_ptypes_set = otx2_nix_ptypes_set,
2068 .dev_reset = otx2_nix_dev_reset,
2069 .stats_get = otx2_nix_dev_stats_get,
2070 .stats_reset = otx2_nix_dev_stats_reset,
2071 .get_reg = otx2_nix_dev_get_reg,
2072 .mtu_set = otx2_nix_mtu_set,
2073 .mac_addr_add = otx2_nix_mac_addr_add,
2074 .mac_addr_remove = otx2_nix_mac_addr_del,
2075 .mac_addr_set = otx2_nix_mac_addr_set,
2076 .set_mc_addr_list = otx2_nix_set_mc_addr_list,
2077 .promiscuous_enable = otx2_nix_promisc_enable,
2078 .promiscuous_disable = otx2_nix_promisc_disable,
2079 .allmulticast_enable = otx2_nix_allmulticast_enable,
2080 .allmulticast_disable = otx2_nix_allmulticast_disable,
2081 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
2082 .reta_update = otx2_nix_dev_reta_update,
2083 .reta_query = otx2_nix_dev_reta_query,
2084 .rss_hash_update = otx2_nix_rss_hash_update,
2085 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
2086 .xstats_get = otx2_nix_xstats_get,
2087 .xstats_get_names = otx2_nix_xstats_get_names,
2088 .xstats_reset = otx2_nix_xstats_reset,
2089 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
2090 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
2091 .rxq_info_get = otx2_nix_rxq_info_get,
2092 .txq_info_get = otx2_nix_txq_info_get,
2093 .rx_burst_mode_get = otx2_rx_burst_mode_get,
2094 .tx_burst_mode_get = otx2_tx_burst_mode_get,
2095 .rx_queue_count = otx2_nix_rx_queue_count,
2096 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
2097 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
2098 .tx_descriptor_status = otx2_nix_tx_descriptor_status,
2099 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
2100 .set_queue_rate_limit = otx2_nix_tm_set_queue_rate_limit,
2101 .pool_ops_supported = otx2_nix_pool_ops_supported,
2102 .filter_ctrl = otx2_nix_dev_filter_ctrl,
2103 .get_module_info = otx2_nix_get_module_info,
2104 .get_module_eeprom = otx2_nix_get_module_eeprom,
2105 .fw_version_get = otx2_nix_fw_version_get,
2106 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
2107 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
2108 .timesync_enable = otx2_nix_timesync_enable,
2109 .timesync_disable = otx2_nix_timesync_disable,
2110 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
2111 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
2112 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
2113 .timesync_read_time = otx2_nix_timesync_read_time,
2114 .timesync_write_time = otx2_nix_timesync_write_time,
2115 .vlan_offload_set = otx2_nix_vlan_offload_set,
2116 .vlan_filter_set = otx2_nix_vlan_filter_set,
2117 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
2118 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
2119 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
2120 .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
2121 .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
2122 .read_clock = otx2_nix_read_clock,
2126 nix_lf_attach(struct otx2_eth_dev *dev)
2128 struct otx2_mbox *mbox = dev->mbox;
2129 struct rsrc_attach_req *req;
2131 /* Attach NIX(lf) */
2132 req = otx2_mbox_alloc_msg_attach_resources(mbox);
2136 return otx2_mbox_process(mbox);
2140 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
2142 struct otx2_mbox *mbox = dev->mbox;
2143 struct msix_offset_rsp *msix_rsp;
2146 /* Get NPA and NIX MSIX vector offsets */
2147 otx2_mbox_alloc_msg_msix_offset(mbox);
2149 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
2151 dev->nix_msixoff = msix_rsp->nix_msixoff;
2157 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
2159 struct rsrc_detach_req *req;
2161 req = otx2_mbox_alloc_msg_detach_resources(mbox);
2163 /* Detach all except npa lf */
2164 req->partial = true;
2171 return otx2_mbox_process(mbox);
2175 otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
2177 if (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||
2178 pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2184 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
2186 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2187 struct rte_pci_device *pci_dev;
2188 int rc, max_entries;
2190 eth_dev->dev_ops = &otx2_eth_dev_ops;
2192 /* For secondary processes, the primary has done all the work */
2193 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2194 /* Setup callbacks for secondary process */
2195 otx2_eth_set_tx_function(eth_dev);
2196 otx2_eth_set_rx_function(eth_dev);
2200 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2202 rte_eth_copy_pci_info(eth_dev, pci_dev);
2203 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2205 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
2206 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
2207 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
2209 /* Parse devargs string */
2210 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
2212 otx2_err("Failed to parse devargs rc=%d", rc);
2216 if (!dev->mbox_active) {
2217 /* Initialize the base otx2_dev object
2218 * only if already present
2220 rc = otx2_dev_init(pci_dev, dev);
2222 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
2226 if (otx2_eth_dev_is_sdp(pci_dev))
2227 dev->sdp_link = true;
2229 dev->sdp_link = false;
2230 /* Device generic callbacks */
2231 dev->ops = &otx2_dev_ops;
2232 dev->eth_dev = eth_dev;
2234 /* Grab the NPA LF if required */
2235 rc = otx2_npa_lf_init(pci_dev, dev);
2237 goto otx2_dev_uninit;
2239 dev->configured = 0;
2240 dev->drv_inited = true;
2241 dev->ptype_disable = 0;
2242 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
2243 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
2246 rc = nix_lf_attach(dev);
2248 goto otx2_npa_uninit;
2250 /* Get NIX MSIX offset */
2251 rc = nix_lf_get_msix_offset(dev);
2253 goto otx2_npa_uninit;
2255 /* Register LF irq handlers */
2256 rc = otx2_nix_register_irqs(eth_dev);
2260 /* Get maximum number of supported MAC entries */
2261 max_entries = otx2_cgx_mac_max_entries_get(dev);
2262 if (max_entries < 0) {
2263 otx2_err("Failed to get max entries for mac addr");
2265 goto unregister_irq;
2268 /* For VFs, returned max_entries will be 0. But to keep default MAC
2269 * address, one entry must be allocated. So setting up to 1.
2271 if (max_entries == 0)
2274 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
2275 RTE_ETHER_ADDR_LEN, 0);
2276 if (eth_dev->data->mac_addrs == NULL) {
2277 otx2_err("Failed to allocate memory for mac addr");
2279 goto unregister_irq;
2282 dev->max_mac_entries = max_entries;
2284 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
2286 goto free_mac_addrs;
2288 /* Update the mac address */
2289 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
2291 /* Also sync same MAC address to CGX table */
2292 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
2294 /* Initialize the tm data structures */
2295 otx2_nix_tm_conf_init(eth_dev);
2297 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
2298 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
2300 if (otx2_dev_is_96xx_A0(dev) ||
2301 otx2_dev_is_95xx_Ax(dev)) {
2302 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
2303 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
2306 /* Create security ctx */
2307 rc = otx2_eth_sec_ctx_create(eth_dev);
2309 goto free_mac_addrs;
2310 dev->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
2311 dev->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
2313 /* Initialize rte-flow */
2314 rc = otx2_flow_init(dev);
2316 goto sec_ctx_destroy;
2318 otx2_nix_mc_filter_init(dev);
2320 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
2321 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
2322 eth_dev->data->port_id, dev->pf, dev->vf,
2323 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
2324 dev->rx_offload_capa, dev->tx_offload_capa);
2328 otx2_eth_sec_ctx_destroy(eth_dev);
2330 rte_free(eth_dev->data->mac_addrs);
2332 otx2_nix_unregister_irqs(eth_dev);
2334 otx2_eth_dev_lf_detach(dev->mbox);
2338 otx2_dev_fini(pci_dev, dev);
2340 otx2_err("Failed to init nix eth_dev rc=%d", rc);
2345 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
2347 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2348 struct rte_pci_device *pci_dev;
2351 /* Nothing to be done for secondary processes */
2352 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2355 /* Clear the flag since we are closing down */
2356 dev->configured = 0;
2358 /* Disable nix bpid config */
2359 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
2361 npc_rx_disable(dev);
2363 /* Disable vlan offloads */
2364 otx2_nix_vlan_fini(eth_dev);
2366 /* Disable other rte_flow entries */
2367 otx2_flow_fini(dev);
2369 /* Free multicast filter list */
2370 otx2_nix_mc_filter_fini(dev);
2372 /* Disable PTP if already enabled */
2373 if (otx2_ethdev_is_ptp_en(dev))
2374 otx2_nix_timesync_disable(eth_dev);
2376 nix_cgx_stop_link_event(dev);
2379 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
2380 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
2381 eth_dev->data->tx_queues[i] = NULL;
2383 eth_dev->data->nb_tx_queues = 0;
2385 /* Free up RQ's and CQ's */
2386 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2387 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
2388 eth_dev->data->rx_queues[i] = NULL;
2390 eth_dev->data->nb_rx_queues = 0;
2392 /* Free tm resources */
2393 rc = otx2_nix_tm_fini(eth_dev);
2395 otx2_err("Failed to cleanup tm, rc=%d", rc);
2397 /* Unregister queue irqs */
2398 oxt2_nix_unregister_queue_irqs(eth_dev);
2400 /* Unregister cq irqs */
2401 if (eth_dev->data->dev_conf.intr_conf.rxq)
2402 oxt2_nix_unregister_cq_irqs(eth_dev);
2404 rc = nix_lf_free(dev);
2406 otx2_err("Failed to free nix lf, rc=%d", rc);
2408 rc = otx2_npa_lf_fini();
2410 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
2412 /* Disable security */
2413 otx2_eth_sec_fini(eth_dev);
2415 /* Destroy security ctx */
2416 otx2_eth_sec_ctx_destroy(eth_dev);
2418 rte_free(eth_dev->data->mac_addrs);
2419 eth_dev->data->mac_addrs = NULL;
2420 dev->drv_inited = false;
2422 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2423 otx2_nix_unregister_irqs(eth_dev);
2425 rc = otx2_eth_dev_lf_detach(dev->mbox);
2427 otx2_err("Failed to detach resources, rc=%d", rc);
2429 /* Check if mbox close is needed */
2433 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
2434 /* Will be freed later by PMD */
2435 eth_dev->data->dev_private = NULL;
2439 otx2_dev_fini(pci_dev, dev);
2444 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
2446 otx2_eth_dev_uninit(eth_dev, true);
2450 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
2454 rc = otx2_eth_dev_uninit(eth_dev, false);
2458 return otx2_eth_dev_init(eth_dev);
2462 nix_remove(struct rte_pci_device *pci_dev)
2464 struct rte_eth_dev *eth_dev;
2465 struct otx2_idev_cfg *idev;
2466 struct otx2_dev *otx2_dev;
2469 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
2471 /* Cleanup eth dev */
2472 rc = otx2_eth_dev_uninit(eth_dev, true);
2476 rte_eth_dev_pci_release(eth_dev);
2479 /* Nothing to be done for secondary processes */
2480 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2483 /* Check for common resources */
2484 idev = otx2_intra_dev_get_cfg();
2485 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
2488 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
2490 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
2493 /* Safe to cleanup mbox as no more users */
2494 otx2_dev_fini(pci_dev, otx2_dev);
2499 otx2_info("%s: common resource in use by other devices", pci_dev->name);
2504 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
2508 RTE_SET_USED(pci_drv);
2510 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
2513 /* On error on secondary, recheck if port exists in primary or
2514 * in mid of detach state.
2516 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
2517 if (!rte_eth_dev_allocated(pci_dev->device.name))
2522 static const struct rte_pci_id pci_nix_map[] = {
2524 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
2527 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
2530 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2531 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
2534 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2535 PCI_DEVID_OCTEONTX2_RVU_SDP_PF)
2538 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2539 PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2546 static struct rte_pci_driver pci_nix = {
2547 .id_table = pci_nix_map,
2548 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
2549 RTE_PCI_DRV_INTR_LSC,
2551 .remove = nix_remove,
2554 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
2555 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
2556 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");