1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_ethdev_pci.h>
9 #include <rte_malloc.h>
11 #include <rte_mbuf_pool_ops.h>
12 #include <rte_mempool.h>
14 #include "otx2_ethdev.h"
16 static inline uint64_t
17 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
19 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
21 if (otx2_dev_is_vf(dev))
22 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
27 static inline uint64_t
28 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
30 uint64_t capa = NIX_TX_OFFLOAD_CAPA;
32 /* TSO not supported for earlier chip revisions */
33 if (otx2_dev_is_96xx_A0(dev) || otx2_dev_is_95xx_Ax(dev))
34 capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
35 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
36 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
37 DEV_TX_OFFLOAD_GRE_TNL_TSO);
41 static const struct otx2_dev_ops otx2_dev_ops = {
42 .link_status_update = otx2_eth_dev_link_status_update,
43 .ptp_info_update = otx2_eth_dev_ptp_info_update
47 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
49 struct otx2_mbox *mbox = dev->mbox;
50 struct nix_lf_alloc_req *req;
51 struct nix_lf_alloc_rsp *rsp;
54 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
58 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
59 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
60 req->xqe_sz = NIX_XQESZ_W16;
61 req->rss_sz = dev->rss_info.rss_size;
62 req->rss_grps = NIX_RSS_GRPS;
63 req->npa_func = otx2_npa_pf_func_get();
64 req->sso_func = otx2_sso_pf_func_get();
65 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
66 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
67 DEV_RX_OFFLOAD_UDP_CKSUM)) {
68 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
69 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
71 req->rx_cfg |= BIT_ULL(32 /* DROP_RE */);
73 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
77 dev->sqb_size = rsp->sqb_size;
78 dev->tx_chan_base = rsp->tx_chan_base;
79 dev->rx_chan_base = rsp->rx_chan_base;
80 dev->rx_chan_cnt = rsp->rx_chan_cnt;
81 dev->tx_chan_cnt = rsp->tx_chan_cnt;
82 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
83 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
84 dev->lf_tx_stats = rsp->lf_tx_stats;
85 dev->lf_rx_stats = rsp->lf_rx_stats;
86 dev->cints = rsp->cints;
87 dev->qints = rsp->qints;
88 dev->npc_flow.channel = dev->rx_chan_base;
89 dev->ptp_en = rsp->hw_rx_tstamp_en;
95 nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev)
97 struct otx2_mbox *mbox = dev->mbox;
98 struct npc_set_pkind *req;
102 if (dev->npc_flow.switch_header_type == 0)
105 /* Notify AF about higig2 config */
106 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
107 req->mode = dev->npc_flow.switch_header_type;
109 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
112 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
113 req->mode = dev->npc_flow.switch_header_type;
115 return otx2_mbox_process_msg(mbox, (void *)&rsp);
119 nix_lf_free(struct otx2_eth_dev *dev)
121 struct otx2_mbox *mbox = dev->mbox;
122 struct nix_lf_free_req *req;
123 struct ndc_sync_op *ndc_req;
126 /* Sync NDC-NIX for LF */
127 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
128 ndc_req->nix_lf_tx_sync = 1;
129 ndc_req->nix_lf_rx_sync = 1;
130 rc = otx2_mbox_process(mbox);
132 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
134 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
135 /* Let AF driver free all this nix lf's
136 * NPC entries allocated using NPC MBOX.
140 return otx2_mbox_process(mbox);
144 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
146 struct otx2_mbox *mbox = dev->mbox;
148 if (otx2_dev_is_vf_or_sdp(dev))
151 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
153 return otx2_mbox_process(mbox);
157 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
159 struct otx2_mbox *mbox = dev->mbox;
161 if (otx2_dev_is_vf_or_sdp(dev))
164 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
166 return otx2_mbox_process(mbox);
170 npc_rx_enable(struct otx2_eth_dev *dev)
172 struct otx2_mbox *mbox = dev->mbox;
174 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
176 return otx2_mbox_process(mbox);
180 npc_rx_disable(struct otx2_eth_dev *dev)
182 struct otx2_mbox *mbox = dev->mbox;
184 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
186 return otx2_mbox_process(mbox);
190 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
192 struct otx2_mbox *mbox = dev->mbox;
194 if (otx2_dev_is_vf_or_sdp(dev))
197 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
199 return otx2_mbox_process(mbox);
203 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
205 struct otx2_mbox *mbox = dev->mbox;
207 if (en && otx2_dev_is_vf_or_sdp(dev))
211 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
213 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
215 return otx2_mbox_process(mbox);
219 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
221 struct otx2_mbox *mbox = dev->mbox;
223 if (otx2_dev_is_vf_or_sdp(dev))
226 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
228 return otx2_mbox_process(mbox);
232 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
238 static inline uint32_t
239 nix_qsize_to_val(enum nix_q_size_e qsize)
241 return (16UL << (qsize * 2));
244 static inline enum nix_q_size_e
245 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
249 if (otx2_ethdev_fixup_is_min_4k_q(dev))
254 for (; i < nix_q_size_max; i++)
255 if (val <= nix_qsize_to_val(i))
258 if (i >= nix_q_size_max)
259 i = nix_q_size_max - 1;
265 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
266 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
268 struct otx2_mbox *mbox = dev->mbox;
269 const struct rte_memzone *rz;
270 uint32_t ring_size, cq_size;
271 struct nix_aq_enq_req *aq;
276 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
277 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
278 NIX_CQ_ALIGN, dev->node);
280 otx2_err("Failed to allocate mem for cq hw ring");
284 memset(rz->addr, 0, rz->len);
285 rxq->desc = (uintptr_t)rz->addr;
286 rxq->qmask = cq_size - 1;
288 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
290 aq->ctype = NIX_AQ_CTYPE_CQ;
291 aq->op = NIX_AQ_INSTOP_INIT;
295 aq->cq.qsize = rxq->qsize;
296 aq->cq.base = rz->iova;
297 aq->cq.avg_level = 0xff;
298 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
299 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
301 /* Many to one reduction */
302 aq->cq.qint_idx = qid % dev->qints;
303 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
304 aq->cq.cint_idx = qid;
306 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
307 const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
308 uint16_t min_rx_drop;
310 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
311 aq->cq.drop = min_rx_drop;
313 rxq->cq_drop = min_rx_drop;
315 rxq->cq_drop = NIX_CQ_THRESH_LEVEL;
316 aq->cq.drop = rxq->cq_drop;
320 /* TX pause frames enable flowctrl on RX side */
321 if (dev->fc_info.tx_pause) {
322 /* Single bpid is allocated for all rx channels for now */
323 aq->cq.bpid = dev->fc_info.bpid[0];
324 aq->cq.bp = rxq->cq_drop;
328 rc = otx2_mbox_process(mbox);
330 otx2_err("Failed to init cq context");
334 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
336 aq->ctype = NIX_AQ_CTYPE_RQ;
337 aq->op = NIX_AQ_INSTOP_INIT;
340 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
342 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
343 first_skip = (sizeof(struct rte_mbuf));
344 first_skip += RTE_PKTMBUF_HEADROOM;
345 first_skip += rte_pktmbuf_priv_size(mp);
346 rxq->data_off = first_skip;
348 first_skip /= 8; /* Expressed in number of dwords */
349 aq->rq.first_skip = first_skip;
350 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
351 aq->rq.flow_tagw = 32; /* 32-bits */
352 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
353 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
354 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
355 aq->rq.lpb_sizem1 /= 8;
356 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
358 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
359 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
360 aq->rq.rq_int_ena = 0;
361 /* Many to one reduction */
362 aq->rq.qint_idx = qid % dev->qints;
364 aq->rq.xqe_drop_ena = 1;
366 rc = otx2_mbox_process(mbox);
368 otx2_err("Failed to init rq context");
378 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
379 struct otx2_eth_rxq *rxq, const bool enb)
381 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
382 struct otx2_mbox *mbox = dev->mbox;
383 struct nix_aq_enq_req *aq;
385 /* Pkts will be dropped silently if RQ is disabled */
386 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
388 aq->ctype = NIX_AQ_CTYPE_RQ;
389 aq->op = NIX_AQ_INSTOP_WRITE;
392 aq->rq_mask.ena = ~(aq->rq_mask.ena);
394 return otx2_mbox_process(mbox);
398 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
400 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
401 struct otx2_mbox *mbox = dev->mbox;
402 struct nix_aq_enq_req *aq;
405 /* RQ is already disabled */
407 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
409 aq->ctype = NIX_AQ_CTYPE_CQ;
410 aq->op = NIX_AQ_INSTOP_WRITE;
413 aq->cq_mask.ena = ~(aq->cq_mask.ena);
415 rc = otx2_mbox_process(mbox);
417 otx2_err("Failed to disable cq context");
425 nix_get_data_off(struct otx2_eth_dev *dev)
427 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
431 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
433 struct rte_mbuf mb_def;
436 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
437 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
438 offsetof(struct rte_mbuf, data_off) != 2);
439 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
440 offsetof(struct rte_mbuf, data_off) != 4);
441 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
442 offsetof(struct rte_mbuf, data_off) != 6);
444 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
445 mb_def.port = port_id;
446 rte_mbuf_refcnt_set(&mb_def, 1);
448 /* Prevent compiler reordering: rearm_data covers previous fields */
449 rte_compiler_barrier();
450 tmp = (uint64_t *)&mb_def.rearm_data;
456 otx2_nix_rx_queue_release(void *rx_queue)
458 struct otx2_eth_rxq *rxq = rx_queue;
463 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
464 nix_cq_rq_uninit(rxq->eth_dev, rxq);
469 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
470 uint16_t nb_desc, unsigned int socket,
471 const struct rte_eth_rxconf *rx_conf,
472 struct rte_mempool *mp)
474 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
475 struct rte_mempool_ops *ops;
476 struct otx2_eth_rxq *rxq;
477 const char *platform_ops;
478 enum nix_q_size_e qsize;
484 /* Compile time check to make sure all fast path elements in a CL */
485 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
488 if (rx_conf->rx_deferred_start == 1) {
489 otx2_err("Deferred Rx start is not supported");
493 platform_ops = rte_mbuf_platform_mempool_ops();
494 /* This driver needs octeontx2_npa mempool ops to work */
495 ops = rte_mempool_get_ops(mp->ops_index);
496 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
497 otx2_err("mempool ops should be of octeontx2_npa type");
501 if (mp->pool_id == 0) {
502 otx2_err("Invalid pool_id");
506 /* Free memory prior to re-allocation if needed */
507 if (eth_dev->data->rx_queues[rq] != NULL) {
508 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
509 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
510 eth_dev->data->rx_queues[rq] = NULL;
513 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
514 dev->rx_offloads |= offloads;
516 /* Find the CQ queue size */
517 qsize = nix_qsize_clampup_get(dev, nb_desc);
518 /* Allocate rxq memory */
519 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
521 otx2_err("Failed to allocate rq=%d", rq);
526 rxq->eth_dev = eth_dev;
528 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
529 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
530 rxq->wdata = (uint64_t)rq << 32;
531 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
532 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
533 eth_dev->data->port_id);
534 rxq->offloads = offloads;
536 rxq->qlen = nix_qsize_to_val(qsize);
538 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
539 rxq->tstamp = &dev->tstamp;
541 /* Alloc completion queue */
542 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
544 otx2_err("Failed to allocate rxq=%u", rq);
548 rxq->qconf.socket_id = socket;
549 rxq->qconf.nb_desc = nb_desc;
550 rxq->qconf.mempool = mp;
551 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
553 nix_rx_queue_reset(rxq);
554 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
555 rq, mp->name, qsize, nb_desc, rxq->qlen);
557 eth_dev->data->rx_queues[rq] = rxq;
558 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
560 /* Calculating delta and freq mult between PTP HI clock and tsc.
561 * These are needed in deriving raw clock value from tsc counter.
562 * read_clock eth op returns raw clock value.
564 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
565 otx2_ethdev_is_ptp_en(dev)) {
566 rc = otx2_nix_raw_clock_tsc_conv(dev);
568 otx2_err("Failed to calculate delta and freq mult");
576 otx2_nix_rx_queue_release(rxq);
581 static inline uint8_t
582 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
585 * Maximum three segments can be supported with W8, Choose
586 * NIX_MAXSQESZ_W16 for multi segment offload.
588 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
589 return NIX_MAXSQESZ_W16;
591 return NIX_MAXSQESZ_W8;
595 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
597 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
598 struct rte_eth_dev_data *data = eth_dev->data;
599 struct rte_eth_conf *conf = &data->dev_conf;
600 struct rte_eth_rxmode *rxmode = &conf->rxmode;
603 if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
604 (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
605 flags |= NIX_RX_OFFLOAD_RSS_F;
607 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
608 DEV_RX_OFFLOAD_UDP_CKSUM))
609 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
611 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
612 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
613 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
615 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
616 flags |= NIX_RX_MULTI_SEG_F;
618 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
619 DEV_RX_OFFLOAD_QINQ_STRIP))
620 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
622 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
623 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
625 if (!dev->ptype_disable)
626 flags |= NIX_RX_OFFLOAD_PTYPE_F;
632 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
634 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
635 uint64_t conf = dev->tx_offloads;
638 /* Fastpath is dependent on these enums */
639 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
640 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
641 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
642 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
643 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
644 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
645 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
646 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
647 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
648 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
649 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
650 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
651 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
652 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
653 offsetof(struct rte_mbuf, buf_iova) + 8);
654 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
655 offsetof(struct rte_mbuf, buf_iova) + 16);
656 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
657 offsetof(struct rte_mbuf, ol_flags) + 12);
658 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
659 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
661 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
662 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
663 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
665 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
666 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
667 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
669 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
670 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
671 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
672 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
673 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
675 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
676 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
678 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
679 flags |= NIX_TX_MULTI_SEG_F;
681 /* Enable Inner checksum for TSO */
682 if (conf & DEV_TX_OFFLOAD_TCP_TSO)
683 flags |= (NIX_TX_OFFLOAD_TSO_F |
684 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
686 /* Enable Inner and Outer checksum for Tunnel TSO */
687 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
688 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
689 DEV_TX_OFFLOAD_GRE_TNL_TSO))
690 flags |= (NIX_TX_OFFLOAD_TSO_F |
691 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
692 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
694 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
695 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
701 nix_sq_init(struct otx2_eth_txq *txq)
703 struct otx2_eth_dev *dev = txq->dev;
704 struct otx2_mbox *mbox = dev->mbox;
705 struct nix_aq_enq_req *sq;
710 if (txq->sqb_pool->pool_id == 0)
713 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
715 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
719 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
721 sq->ctype = NIX_AQ_CTYPE_SQ;
722 sq->op = NIX_AQ_INSTOP_INIT;
723 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
726 sq->sq.smq_rr_quantum = rr_quantum;
727 sq->sq.default_chan = dev->tx_chan_base;
728 sq->sq.sqe_stype = NIX_STYPE_STF;
730 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
731 sq->sq.sqe_stype = NIX_STYPE_STP;
733 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
734 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
735 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
736 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
737 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
739 /* Many to one reduction */
740 sq->sq.qint_idx = txq->sq % dev->qints;
742 return otx2_mbox_process(mbox);
746 nix_sq_uninit(struct otx2_eth_txq *txq)
748 struct otx2_eth_dev *dev = txq->dev;
749 struct otx2_mbox *mbox = dev->mbox;
750 struct ndc_sync_op *ndc_req;
751 struct nix_aq_enq_rsp *rsp;
752 struct nix_aq_enq_req *aq;
753 uint16_t sqes_per_sqb;
757 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
759 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
761 aq->ctype = NIX_AQ_CTYPE_SQ;
762 aq->op = NIX_AQ_INSTOP_READ;
764 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
768 /* Check if sq is already cleaned up */
773 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
775 aq->ctype = NIX_AQ_CTYPE_SQ;
776 aq->op = NIX_AQ_INSTOP_WRITE;
778 aq->sq_mask.ena = ~aq->sq_mask.ena;
781 rc = otx2_mbox_process(mbox);
785 /* Read SQ and free sqb's */
786 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
788 aq->ctype = NIX_AQ_CTYPE_SQ;
789 aq->op = NIX_AQ_INSTOP_READ;
791 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
796 otx2_err("SQ has pending sqe's");
798 count = aq->sq.sqb_count;
799 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
800 /* Free SQB's that are used */
801 sqb_buf = (void *)rsp->sq.head_sqb;
805 next_sqb = *(void **)((uintptr_t)sqb_buf + (uint32_t)
806 ((sqes_per_sqb - 1) *
807 nix_sq_max_sqe_sz(txq)));
808 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
814 /* Free next to use sqb */
815 if (rsp->sq.next_sqb)
816 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
819 /* Sync NDC-NIX-TX for LF */
820 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
821 ndc_req->nix_lf_tx_sync = 1;
822 rc = otx2_mbox_process(mbox);
824 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
830 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
832 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
833 struct npa_aq_enq_req *aura_req;
835 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
836 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
837 aura_req->ctype = NPA_AQ_CTYPE_AURA;
838 aura_req->op = NPA_AQ_INSTOP_WRITE;
840 aura_req->aura.limit = nb_sqb_bufs;
841 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
843 return otx2_mbox_process(npa_lf->mbox);
847 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
849 struct otx2_eth_dev *dev = txq->dev;
850 uint16_t sqes_per_sqb, nb_sqb_bufs;
851 char name[RTE_MEMPOOL_NAMESIZE];
852 struct rte_mempool_objsz sz;
853 struct npa_aura_s *aura;
854 uint32_t tmp, blk_sz;
856 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
857 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
858 blk_sz = dev->sqb_size;
860 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
861 sqes_per_sqb = (dev->sqb_size / 8) / 16;
863 sqes_per_sqb = (dev->sqb_size / 8) / 8;
865 nb_sqb_bufs = nb_desc / sqes_per_sqb;
866 /* Clamp up to devarg passed SQB count */
867 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_DEF_SQB,
868 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
870 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
872 MEMPOOL_F_NO_SPREAD);
873 txq->nb_sqb_bufs = nb_sqb_bufs;
874 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
875 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
876 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
877 txq->nb_sqb_bufs_adj =
878 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
880 if (txq->sqb_pool == NULL) {
881 otx2_err("Failed to allocate sqe mempool");
885 memset(aura, 0, sizeof(*aura));
887 aura->fc_addr = txq->fc_iova;
888 aura->fc_hyst_bits = 0; /* Store count on all updates */
889 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
890 otx2_err("Failed to set ops for sqe mempool");
893 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
894 otx2_err("Failed to populate sqe mempool");
898 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
899 if (dev->sqb_size != sz.elt_size) {
900 otx2_err("sqe pool block size is not expected %d != %d",
905 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
913 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
915 struct nix_send_ext_s *send_hdr_ext;
916 struct nix_send_hdr_s *send_hdr;
917 struct nix_send_mem_s *send_mem;
918 union nix_send_sg_s *sg;
920 /* Initialize the fields based on basic single segment packet */
921 memset(&txq->cmd, 0, sizeof(txq->cmd));
923 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
924 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
925 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
926 send_hdr->w0.sizem1 = 2;
928 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
929 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
930 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
931 /* Default: one seg packet would have:
932 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
935 send_hdr->w0.sizem1 = 3;
936 send_hdr_ext->w0.tstmp = 1;
938 /* To calculate the offset for send_mem,
939 * send_hdr->w0.sizem1 * 2
941 send_mem = (struct nix_send_mem_s *)(txq->cmd +
942 (send_hdr->w0.sizem1 << 1));
943 send_mem->subdc = NIX_SUBDC_MEM;
944 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
945 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
947 sg = (union nix_send_sg_s *)&txq->cmd[4];
949 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
950 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
951 send_hdr->w0.sizem1 = 1;
952 sg = (union nix_send_sg_s *)&txq->cmd[2];
955 send_hdr->w0.sq = txq->sq;
956 sg->subdc = NIX_SUBDC_SG;
958 sg->ld_type = NIX_SENDLDTYPE_LDD;
964 otx2_nix_tx_queue_release(void *_txq)
966 struct otx2_eth_txq *txq = _txq;
967 struct rte_eth_dev *eth_dev;
972 eth_dev = txq->dev->eth_dev;
974 otx2_nix_dbg("Releasing txq %u", txq->sq);
976 /* Flush and disable tm */
977 otx2_nix_tm_sw_xoff(txq, eth_dev->data->dev_started);
979 /* Free sqb's and disable sq */
983 rte_mempool_free(txq->sqb_pool);
984 txq->sqb_pool = NULL;
991 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
992 uint16_t nb_desc, unsigned int socket_id,
993 const struct rte_eth_txconf *tx_conf)
995 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
996 const struct rte_memzone *fc;
997 struct otx2_eth_txq *txq;
1003 /* Compile time check to make sure all fast path elements in a CL */
1004 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
1006 if (tx_conf->tx_deferred_start) {
1007 otx2_err("Tx deferred start is not supported");
1011 /* Free memory prior to re-allocation if needed. */
1012 if (eth_dev->data->tx_queues[sq] != NULL) {
1013 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
1014 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
1015 eth_dev->data->tx_queues[sq] = NULL;
1018 /* Find the expected offloads for this queue */
1019 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
1021 /* Allocating tx queue data structure */
1022 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
1023 OTX2_ALIGN, socket_id);
1025 otx2_err("Failed to alloc txq=%d", sq);
1031 txq->sqb_pool = NULL;
1032 txq->offloads = offloads;
1033 dev->tx_offloads |= offloads;
1036 * Allocate memory for flow control updates from HW.
1037 * Alloc one cache line, so that fits all FC_STYPE modes.
1039 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
1040 OTX2_ALIGN + sizeof(struct npa_aura_s),
1041 OTX2_ALIGN, dev->node);
1043 otx2_err("Failed to allocate mem for fcmem");
1047 txq->fc_iova = fc->iova;
1048 txq->fc_mem = fc->addr;
1050 /* Initialize the aura sqb pool */
1051 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
1053 otx2_err("Failed to alloc sqe pool rc=%d", rc);
1057 /* Initialize the SQ */
1058 rc = nix_sq_init(txq);
1060 otx2_err("Failed to init sq=%d context", sq);
1064 txq->fc_cache_pkts = 0;
1065 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
1066 /* Evenly distribute LMT slot for each sq */
1067 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
1069 txq->qconf.socket_id = socket_id;
1070 txq->qconf.nb_desc = nb_desc;
1071 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
1073 otx2_nix_form_default_desc(txq);
1075 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
1076 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
1077 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
1078 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
1079 eth_dev->data->tx_queues[sq] = txq;
1080 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
1084 otx2_nix_tx_queue_release(txq);
1090 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1092 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1093 struct otx2_eth_qconf *tx_qconf = NULL;
1094 struct otx2_eth_qconf *rx_qconf = NULL;
1095 struct otx2_eth_txq **txq;
1096 struct otx2_eth_rxq **rxq;
1097 int i, nb_rxq, nb_txq;
1099 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1100 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1102 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1103 if (tx_qconf == NULL) {
1104 otx2_err("Failed to allocate memory for tx_qconf");
1108 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1109 if (rx_qconf == NULL) {
1110 otx2_err("Failed to allocate memory for rx_qconf");
1114 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1115 for (i = 0; i < nb_txq; i++) {
1116 if (txq[i] == NULL) {
1117 otx2_err("txq[%d] is already released", i);
1120 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1121 otx2_nix_tx_queue_release(txq[i]);
1122 eth_dev->data->tx_queues[i] = NULL;
1125 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1126 for (i = 0; i < nb_rxq; i++) {
1127 if (rxq[i] == NULL) {
1128 otx2_err("rxq[%d] is already released", i);
1131 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1132 otx2_nix_rx_queue_release(rxq[i]);
1133 eth_dev->data->rx_queues[i] = NULL;
1136 dev->tx_qconf = tx_qconf;
1137 dev->rx_qconf = rx_qconf;
1150 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1152 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1153 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1154 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1155 struct otx2_eth_txq **txq;
1156 struct otx2_eth_rxq **rxq;
1157 int rc, i, nb_rxq, nb_txq;
1159 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1160 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1163 /* Setup tx & rx queues with previous configuration so
1164 * that the queues can be functional in cases like ports
1165 * are started without re configuring queues.
1167 * Usual re config sequence is like below:
1168 * port_configure() {
1173 * queue_configure() {
1180 * In some application's control path, queue_configure() would
1181 * NOT be invoked for TXQs/RXQs in port_configure().
1182 * In such cases, queues can be functional after start as the
1183 * queues are already setup in port_configure().
1185 for (i = 0; i < nb_txq; i++) {
1186 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1187 tx_qconf[i].socket_id,
1188 &tx_qconf[i].conf.tx);
1190 otx2_err("Failed to setup tx queue rc=%d", rc);
1191 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1192 for (i -= 1; i >= 0; i--)
1193 otx2_nix_tx_queue_release(txq[i]);
1198 free(tx_qconf); tx_qconf = NULL;
1200 for (i = 0; i < nb_rxq; i++) {
1201 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1202 rx_qconf[i].socket_id,
1203 &rx_qconf[i].conf.rx,
1204 rx_qconf[i].mempool);
1206 otx2_err("Failed to setup rx queue rc=%d", rc);
1207 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1208 for (i -= 1; i >= 0; i--)
1209 otx2_nix_rx_queue_release(rxq[i]);
1210 goto release_tx_queues;
1214 free(rx_qconf); rx_qconf = NULL;
1219 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1220 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1221 otx2_nix_tx_queue_release(txq[i]);
1232 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1234 RTE_SET_USED(queue);
1235 RTE_SET_USED(mbufs);
1242 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1244 /* These dummy functions are required for supporting
1245 * some applications which reconfigure queues without
1246 * stopping tx burst and rx burst threads(eg kni app)
1247 * When the queues context is saved, txq/rxqs are released
1248 * which caused app crash since rx/tx burst is still
1249 * on different lcores
1251 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1252 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1257 nix_lso_tcp(struct nix_lso_format_cfg *req, bool v4)
1259 volatile struct nix_lso_format *field;
1261 /* Format works only with TCP packet marked by OL3/OL4 */
1262 field = (volatile struct nix_lso_format *)&req->fields[0];
1263 req->field_mask = NIX_LSO_FIELD_MASK;
1264 /* Outer IPv4/IPv6 */
1265 field->layer = NIX_TXLAYER_OL3;
1266 field->offset = v4 ? 2 : 4;
1267 field->sizem1 = 1; /* 2B */
1268 field->alg = NIX_LSOALG_ADD_PAYLEN;
1272 field->layer = NIX_TXLAYER_OL3;
1275 /* Incremented linearly per segment */
1276 field->alg = NIX_LSOALG_ADD_SEGNUM;
1280 /* TCP sequence number update */
1281 field->layer = NIX_TXLAYER_OL4;
1283 field->sizem1 = 3; /* 4 bytes */
1284 field->alg = NIX_LSOALG_ADD_OFFSET;
1286 /* TCP flags field */
1287 field->layer = NIX_TXLAYER_OL4;
1290 field->alg = NIX_LSOALG_TCP_FLAGS;
1295 nix_lso_udp_tun_tcp(struct nix_lso_format_cfg *req,
1296 bool outer_v4, bool inner_v4)
1298 volatile struct nix_lso_format *field;
1300 field = (volatile struct nix_lso_format *)&req->fields[0];
1301 req->field_mask = NIX_LSO_FIELD_MASK;
1302 /* Outer IPv4/IPv6 len */
1303 field->layer = NIX_TXLAYER_OL3;
1304 field->offset = outer_v4 ? 2 : 4;
1305 field->sizem1 = 1; /* 2B */
1306 field->alg = NIX_LSOALG_ADD_PAYLEN;
1310 field->layer = NIX_TXLAYER_OL3;
1313 /* Incremented linearly per segment */
1314 field->alg = NIX_LSOALG_ADD_SEGNUM;
1318 /* Outer UDP length */
1319 field->layer = NIX_TXLAYER_OL4;
1322 field->alg = NIX_LSOALG_ADD_PAYLEN;
1325 /* Inner IPv4/IPv6 */
1326 field->layer = NIX_TXLAYER_IL3;
1327 field->offset = inner_v4 ? 2 : 4;
1328 field->sizem1 = 1; /* 2B */
1329 field->alg = NIX_LSOALG_ADD_PAYLEN;
1333 field->layer = NIX_TXLAYER_IL3;
1336 /* Incremented linearly per segment */
1337 field->alg = NIX_LSOALG_ADD_SEGNUM;
1341 /* TCP sequence number update */
1342 field->layer = NIX_TXLAYER_IL4;
1344 field->sizem1 = 3; /* 4 bytes */
1345 field->alg = NIX_LSOALG_ADD_OFFSET;
1348 /* TCP flags field */
1349 field->layer = NIX_TXLAYER_IL4;
1352 field->alg = NIX_LSOALG_TCP_FLAGS;
1357 nix_lso_tun_tcp(struct nix_lso_format_cfg *req,
1358 bool outer_v4, bool inner_v4)
1360 volatile struct nix_lso_format *field;
1362 field = (volatile struct nix_lso_format *)&req->fields[0];
1363 req->field_mask = NIX_LSO_FIELD_MASK;
1364 /* Outer IPv4/IPv6 len */
1365 field->layer = NIX_TXLAYER_OL3;
1366 field->offset = outer_v4 ? 2 : 4;
1367 field->sizem1 = 1; /* 2B */
1368 field->alg = NIX_LSOALG_ADD_PAYLEN;
1372 field->layer = NIX_TXLAYER_OL3;
1375 /* Incremented linearly per segment */
1376 field->alg = NIX_LSOALG_ADD_SEGNUM;
1380 /* Inner IPv4/IPv6 */
1381 field->layer = NIX_TXLAYER_IL3;
1382 field->offset = inner_v4 ? 2 : 4;
1383 field->sizem1 = 1; /* 2B */
1384 field->alg = NIX_LSOALG_ADD_PAYLEN;
1388 field->layer = NIX_TXLAYER_IL3;
1391 /* Incremented linearly per segment */
1392 field->alg = NIX_LSOALG_ADD_SEGNUM;
1396 /* TCP sequence number update */
1397 field->layer = NIX_TXLAYER_IL4;
1399 field->sizem1 = 3; /* 4 bytes */
1400 field->alg = NIX_LSOALG_ADD_OFFSET;
1403 /* TCP flags field */
1404 field->layer = NIX_TXLAYER_IL4;
1407 field->alg = NIX_LSOALG_TCP_FLAGS;
1412 nix_setup_lso_formats(struct otx2_eth_dev *dev)
1414 struct otx2_mbox *mbox = dev->mbox;
1415 struct nix_lso_format_cfg_rsp *rsp;
1416 struct nix_lso_format_cfg *req;
1420 /* Skip if TSO was not requested */
1421 if (!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F))
1426 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1427 nix_lso_tcp(req, true);
1428 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1432 base = rsp->lso_format_idx;
1433 if (base != NIX_LSO_FORMAT_IDX_TSOV4)
1435 dev->lso_base_idx = base;
1436 otx2_nix_dbg("tcpv4 lso fmt=%u", base);
1442 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1443 nix_lso_tcp(req, false);
1444 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1448 if (rsp->lso_format_idx != base + 1)
1450 otx2_nix_dbg("tcpv6 lso fmt=%u\n", base + 1);
1453 * IPv4/UDP/TUN HDR/IPv4/TCP LSO
1455 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1456 nix_lso_udp_tun_tcp(req, true, true);
1457 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1461 if (rsp->lso_format_idx != base + 2)
1463 otx2_nix_dbg("udp tun v4v4 fmt=%u\n", base + 2);
1466 * IPv4/UDP/TUN HDR/IPv6/TCP LSO
1468 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1469 nix_lso_udp_tun_tcp(req, true, false);
1470 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1474 if (rsp->lso_format_idx != base + 3)
1476 otx2_nix_dbg("udp tun v4v6 fmt=%u\n", base + 3);
1479 * IPv6/UDP/TUN HDR/IPv4/TCP LSO
1481 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1482 nix_lso_udp_tun_tcp(req, false, true);
1483 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1487 if (rsp->lso_format_idx != base + 4)
1489 otx2_nix_dbg("udp tun v6v4 fmt=%u\n", base + 4);
1492 * IPv6/UDP/TUN HDR/IPv6/TCP LSO
1494 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1495 nix_lso_udp_tun_tcp(req, false, false);
1496 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1499 if (rsp->lso_format_idx != base + 5)
1501 otx2_nix_dbg("udp tun v6v6 fmt=%u\n", base + 5);
1504 * IPv4/TUN HDR/IPv4/TCP LSO
1506 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1507 nix_lso_tun_tcp(req, true, true);
1508 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1512 if (rsp->lso_format_idx != base + 6)
1514 otx2_nix_dbg("tun v4v4 fmt=%u\n", base + 6);
1517 * IPv4/TUN HDR/IPv6/TCP LSO
1519 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1520 nix_lso_tun_tcp(req, true, false);
1521 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1525 if (rsp->lso_format_idx != base + 7)
1527 otx2_nix_dbg("tun v4v6 fmt=%u\n", base + 7);
1530 * IPv6/TUN HDR/IPv4/TCP LSO
1532 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1533 nix_lso_tun_tcp(req, false, true);
1534 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1538 if (rsp->lso_format_idx != base + 8)
1540 otx2_nix_dbg("tun v6v4 fmt=%u\n", base + 8);
1543 * IPv6/TUN HDR/IPv6/TCP LSO
1545 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1546 nix_lso_tun_tcp(req, false, false);
1547 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1550 if (rsp->lso_format_idx != base + 9)
1552 otx2_nix_dbg("tun v6v6 fmt=%u\n", base + 9);
1557 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1559 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1560 struct rte_eth_dev_data *data = eth_dev->data;
1561 struct rte_eth_conf *conf = &data->dev_conf;
1562 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1563 struct rte_eth_txmode *txmode = &conf->txmode;
1564 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1565 struct rte_ether_addr *ea;
1566 uint8_t nb_rxq, nb_txq;
1572 if (rte_eal_has_hugepages() == 0) {
1573 otx2_err("Huge page is not configured");
1574 goto fail_configure;
1577 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1578 otx2_err("Setting link speed/duplex not supported");
1579 goto fail_configure;
1582 if (conf->dcb_capability_en == 1) {
1583 otx2_err("dcb enable is not supported");
1584 goto fail_configure;
1587 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1588 otx2_err("Flow director is not supported");
1589 goto fail_configure;
1592 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1593 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1594 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1595 goto fail_configure;
1598 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1599 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1600 goto fail_configure;
1603 if (otx2_dev_is_Ax(dev) &&
1604 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1605 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1606 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1607 otx2_err("Outer IP and SCTP checksum unsupported");
1608 goto fail_configure;
1611 /* Free the resources allocated from the previous configure */
1612 if (dev->configured == 1) {
1613 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1614 otx2_nix_vlan_fini(eth_dev);
1615 otx2_nix_mc_addr_list_uninstall(eth_dev);
1616 otx2_flow_free_all_resources(dev);
1617 oxt2_nix_unregister_queue_irqs(eth_dev);
1618 if (eth_dev->data->dev_conf.intr_conf.rxq)
1619 oxt2_nix_unregister_cq_irqs(eth_dev);
1620 nix_set_nop_rxtx_function(eth_dev);
1621 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1623 goto fail_configure;
1624 otx2_nix_tm_fini(eth_dev);
1628 dev->rx_offloads = rxmode->offloads;
1629 dev->tx_offloads = txmode->offloads;
1630 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1631 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1632 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1634 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1635 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1637 /* Alloc a nix lf */
1638 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1640 otx2_err("Failed to init nix_lf rc=%d", rc);
1644 rc = nix_lf_switch_header_type_enable(dev);
1646 otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
1650 rc = nix_setup_lso_formats(dev);
1652 otx2_err("failed to setup nix lso format fields, rc=%d", rc);
1657 rc = otx2_nix_rss_config(eth_dev);
1659 otx2_err("Failed to configure rss rc=%d", rc);
1663 /* Init the default TM scheduler hierarchy */
1664 rc = otx2_nix_tm_init_default(eth_dev);
1666 otx2_err("Failed to init traffic manager rc=%d", rc);
1670 rc = otx2_nix_vlan_offload_init(eth_dev);
1672 otx2_err("Failed to init vlan offload rc=%d", rc);
1676 /* Register queue IRQs */
1677 rc = oxt2_nix_register_queue_irqs(eth_dev);
1679 otx2_err("Failed to register queue interrupts rc=%d", rc);
1683 /* Register cq IRQs */
1684 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1685 if (eth_dev->data->nb_rx_queues > dev->cints) {
1686 otx2_err("Rx interrupt cannot be enabled, rxq > %d",
1690 /* Rx interrupt feature cannot work with vector mode because,
1691 * vector mode doesn't process packets unless min 4 pkts are
1692 * received, while cq interrupts are generated even for 1 pkt
1695 dev->scalar_ena = true;
1697 rc = oxt2_nix_register_cq_irqs(eth_dev);
1699 otx2_err("Failed to register CQ interrupts rc=%d", rc);
1704 /* Configure loop back mode */
1705 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1707 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1711 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1713 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1717 rc = otx2_nix_mc_addr_list_install(eth_dev);
1719 otx2_err("Failed to install mc address list rc=%d", rc);
1724 * Restore queue config when reconfigure followed by
1725 * reconfigure and no queue configure invoked from application case.
1727 if (dev->configured == 1) {
1728 rc = nix_restore_queue_cfg(eth_dev);
1730 goto uninstall_mc_list;
1733 /* Update the mac address */
1734 ea = eth_dev->data->mac_addrs;
1735 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1736 if (rte_is_zero_ether_addr(ea))
1737 rte_eth_random_addr((uint8_t *)ea);
1739 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1741 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1742 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1743 " rx_flags=0x%x tx_flags=0x%x",
1744 eth_dev->data->port_id, ea_fmt, nb_rxq,
1745 nb_txq, dev->rx_offloads, dev->tx_offloads,
1746 dev->rx_offload_flags, dev->tx_offload_flags);
1749 dev->configured = 1;
1750 dev->configured_nb_rx_qs = data->nb_rx_queues;
1751 dev->configured_nb_tx_qs = data->nb_tx_queues;
1755 otx2_nix_mc_addr_list_uninstall(eth_dev);
1757 oxt2_nix_unregister_cq_irqs(eth_dev);
1759 oxt2_nix_unregister_queue_irqs(eth_dev);
1761 otx2_nix_vlan_fini(eth_dev);
1763 otx2_nix_tm_fini(eth_dev);
1767 dev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);
1768 dev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);
1770 dev->configured = 0;
1775 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1777 struct rte_eth_dev_data *data = eth_dev->data;
1778 struct otx2_eth_txq *txq;
1781 txq = eth_dev->data->tx_queues[qidx];
1783 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1786 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1788 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1793 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1800 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1802 struct rte_eth_dev_data *data = eth_dev->data;
1803 struct otx2_eth_txq *txq;
1806 txq = eth_dev->data->tx_queues[qidx];
1808 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1811 txq->fc_cache_pkts = 0;
1813 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1815 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1820 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1827 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1829 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1830 struct rte_eth_dev_data *data = eth_dev->data;
1833 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1836 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1838 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1842 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1849 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1851 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1852 struct rte_eth_dev_data *data = eth_dev->data;
1855 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1858 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1860 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1864 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1871 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
1873 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1874 struct rte_mbuf *rx_pkts[32];
1875 struct otx2_eth_rxq *rxq;
1876 int count, i, j, rc;
1878 nix_cgx_stop_link_event(dev);
1879 npc_rx_disable(dev);
1881 /* Stop rx queues and free up pkts pending */
1882 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1883 rc = otx2_nix_rx_queue_stop(eth_dev, i);
1887 rxq = eth_dev->data->rx_queues[i];
1888 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1890 for (j = 0; j < count; j++)
1891 rte_pktmbuf_free(rx_pkts[j]);
1892 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1896 /* Stop tx queues */
1897 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1898 otx2_nix_tx_queue_stop(eth_dev, i);
1902 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
1904 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1907 /* MTU recalculate should be avoided here if PTP is enabled by PF, as
1908 * otx2_nix_recalc_mtu would be invoked during otx2_nix_ptp_enable_vf
1911 if (eth_dev->data->nb_rx_queues != 0 && !otx2_ethdev_is_ptp_en(dev)) {
1912 rc = otx2_nix_recalc_mtu(eth_dev);
1917 /* Start rx queues */
1918 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1919 rc = otx2_nix_rx_queue_start(eth_dev, i);
1924 /* Start tx queues */
1925 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1926 rc = otx2_nix_tx_queue_start(eth_dev, i);
1931 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
1933 otx2_err("Failed to update flow ctrl mode %d", rc);
1937 /* Enable PTP if it was requested by the app or if it is already
1938 * enabled in PF owning this VF
1940 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
1941 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
1942 otx2_ethdev_is_ptp_en(dev))
1943 otx2_nix_timesync_enable(eth_dev);
1945 otx2_nix_timesync_disable(eth_dev);
1947 /* Update VF about data off shifted by 8 bytes if PTP already
1948 * enabled in PF owning this VF
1950 if (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))
1951 otx2_nix_ptp_enable_vf(eth_dev);
1953 rc = npc_rx_enable(dev);
1955 otx2_err("Failed to enable NPC rx %d", rc);
1959 otx2_nix_toggle_flag_link_cfg(dev, true);
1961 rc = nix_cgx_start_link_event(dev);
1963 otx2_err("Failed to start cgx link event %d", rc);
1967 otx2_nix_toggle_flag_link_cfg(dev, false);
1968 otx2_eth_set_tx_function(eth_dev);
1969 otx2_eth_set_rx_function(eth_dev);
1974 npc_rx_disable(dev);
1975 otx2_nix_toggle_flag_link_cfg(dev, false);
1979 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
1980 static void otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
1982 /* Initialize and register driver with DPDK Application */
1983 static const struct eth_dev_ops otx2_eth_dev_ops = {
1984 .dev_infos_get = otx2_nix_info_get,
1985 .dev_configure = otx2_nix_configure,
1986 .link_update = otx2_nix_link_update,
1987 .tx_queue_setup = otx2_nix_tx_queue_setup,
1988 .tx_queue_release = otx2_nix_tx_queue_release,
1989 .rx_queue_setup = otx2_nix_rx_queue_setup,
1990 .rx_queue_release = otx2_nix_rx_queue_release,
1991 .dev_start = otx2_nix_dev_start,
1992 .dev_stop = otx2_nix_dev_stop,
1993 .dev_close = otx2_nix_dev_close,
1994 .tx_queue_start = otx2_nix_tx_queue_start,
1995 .tx_queue_stop = otx2_nix_tx_queue_stop,
1996 .rx_queue_start = otx2_nix_rx_queue_start,
1997 .rx_queue_stop = otx2_nix_rx_queue_stop,
1998 .dev_set_link_up = otx2_nix_dev_set_link_up,
1999 .dev_set_link_down = otx2_nix_dev_set_link_down,
2000 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
2001 .dev_ptypes_set = otx2_nix_ptypes_set,
2002 .dev_reset = otx2_nix_dev_reset,
2003 .stats_get = otx2_nix_dev_stats_get,
2004 .stats_reset = otx2_nix_dev_stats_reset,
2005 .get_reg = otx2_nix_dev_get_reg,
2006 .mtu_set = otx2_nix_mtu_set,
2007 .mac_addr_add = otx2_nix_mac_addr_add,
2008 .mac_addr_remove = otx2_nix_mac_addr_del,
2009 .mac_addr_set = otx2_nix_mac_addr_set,
2010 .set_mc_addr_list = otx2_nix_set_mc_addr_list,
2011 .promiscuous_enable = otx2_nix_promisc_enable,
2012 .promiscuous_disable = otx2_nix_promisc_disable,
2013 .allmulticast_enable = otx2_nix_allmulticast_enable,
2014 .allmulticast_disable = otx2_nix_allmulticast_disable,
2015 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
2016 .reta_update = otx2_nix_dev_reta_update,
2017 .reta_query = otx2_nix_dev_reta_query,
2018 .rss_hash_update = otx2_nix_rss_hash_update,
2019 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
2020 .xstats_get = otx2_nix_xstats_get,
2021 .xstats_get_names = otx2_nix_xstats_get_names,
2022 .xstats_reset = otx2_nix_xstats_reset,
2023 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
2024 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
2025 .rxq_info_get = otx2_nix_rxq_info_get,
2026 .txq_info_get = otx2_nix_txq_info_get,
2027 .rx_burst_mode_get = otx2_rx_burst_mode_get,
2028 .tx_burst_mode_get = otx2_tx_burst_mode_get,
2029 .rx_queue_count = otx2_nix_rx_queue_count,
2030 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
2031 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
2032 .tx_descriptor_status = otx2_nix_tx_descriptor_status,
2033 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
2034 .pool_ops_supported = otx2_nix_pool_ops_supported,
2035 .filter_ctrl = otx2_nix_dev_filter_ctrl,
2036 .get_module_info = otx2_nix_get_module_info,
2037 .get_module_eeprom = otx2_nix_get_module_eeprom,
2038 .fw_version_get = otx2_nix_fw_version_get,
2039 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
2040 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
2041 .timesync_enable = otx2_nix_timesync_enable,
2042 .timesync_disable = otx2_nix_timesync_disable,
2043 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
2044 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
2045 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
2046 .timesync_read_time = otx2_nix_timesync_read_time,
2047 .timesync_write_time = otx2_nix_timesync_write_time,
2048 .vlan_offload_set = otx2_nix_vlan_offload_set,
2049 .vlan_filter_set = otx2_nix_vlan_filter_set,
2050 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
2051 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
2052 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
2053 .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
2054 .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
2055 .read_clock = otx2_nix_read_clock,
2059 nix_lf_attach(struct otx2_eth_dev *dev)
2061 struct otx2_mbox *mbox = dev->mbox;
2062 struct rsrc_attach_req *req;
2064 /* Attach NIX(lf) */
2065 req = otx2_mbox_alloc_msg_attach_resources(mbox);
2069 return otx2_mbox_process(mbox);
2073 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
2075 struct otx2_mbox *mbox = dev->mbox;
2076 struct msix_offset_rsp *msix_rsp;
2079 /* Get NPA and NIX MSIX vector offsets */
2080 otx2_mbox_alloc_msg_msix_offset(mbox);
2082 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
2084 dev->nix_msixoff = msix_rsp->nix_msixoff;
2090 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
2092 struct rsrc_detach_req *req;
2094 req = otx2_mbox_alloc_msg_detach_resources(mbox);
2096 /* Detach all except npa lf */
2097 req->partial = true;
2104 return otx2_mbox_process(mbox);
2108 otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
2110 if (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||
2111 pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2117 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
2119 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2120 struct rte_pci_device *pci_dev;
2121 int rc, max_entries;
2123 eth_dev->dev_ops = &otx2_eth_dev_ops;
2125 /* For secondary processes, the primary has done all the work */
2126 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2127 /* Setup callbacks for secondary process */
2128 otx2_eth_set_tx_function(eth_dev);
2129 otx2_eth_set_rx_function(eth_dev);
2133 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2135 rte_eth_copy_pci_info(eth_dev, pci_dev);
2136 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2138 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
2139 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
2140 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
2142 /* Parse devargs string */
2143 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
2145 otx2_err("Failed to parse devargs rc=%d", rc);
2149 if (!dev->mbox_active) {
2150 /* Initialize the base otx2_dev object
2151 * only if already present
2153 rc = otx2_dev_init(pci_dev, dev);
2155 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
2159 if (otx2_eth_dev_is_sdp(pci_dev))
2160 dev->sdp_link = true;
2162 dev->sdp_link = false;
2163 /* Device generic callbacks */
2164 dev->ops = &otx2_dev_ops;
2165 dev->eth_dev = eth_dev;
2167 /* Grab the NPA LF if required */
2168 rc = otx2_npa_lf_init(pci_dev, dev);
2170 goto otx2_dev_uninit;
2172 dev->configured = 0;
2173 dev->drv_inited = true;
2174 dev->ptype_disable = 0;
2175 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
2176 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
2179 rc = nix_lf_attach(dev);
2181 goto otx2_npa_uninit;
2183 /* Get NIX MSIX offset */
2184 rc = nix_lf_get_msix_offset(dev);
2186 goto otx2_npa_uninit;
2188 /* Register LF irq handlers */
2189 rc = otx2_nix_register_irqs(eth_dev);
2193 /* Get maximum number of supported MAC entries */
2194 max_entries = otx2_cgx_mac_max_entries_get(dev);
2195 if (max_entries < 0) {
2196 otx2_err("Failed to get max entries for mac addr");
2198 goto unregister_irq;
2201 /* For VFs, returned max_entries will be 0. But to keep default MAC
2202 * address, one entry must be allocated. So setting up to 1.
2204 if (max_entries == 0)
2207 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
2208 RTE_ETHER_ADDR_LEN, 0);
2209 if (eth_dev->data->mac_addrs == NULL) {
2210 otx2_err("Failed to allocate memory for mac addr");
2212 goto unregister_irq;
2215 dev->max_mac_entries = max_entries;
2217 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
2219 goto free_mac_addrs;
2221 /* Update the mac address */
2222 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
2224 /* Also sync same MAC address to CGX table */
2225 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
2227 /* Initialize the tm data structures */
2228 otx2_nix_tm_conf_init(eth_dev);
2230 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
2231 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
2233 if (otx2_dev_is_96xx_A0(dev) ||
2234 otx2_dev_is_95xx_Ax(dev)) {
2235 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
2236 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
2239 /* Initialize rte-flow */
2240 rc = otx2_flow_init(dev);
2242 goto free_mac_addrs;
2244 otx2_nix_mc_filter_init(dev);
2246 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
2247 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
2248 eth_dev->data->port_id, dev->pf, dev->vf,
2249 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
2250 dev->rx_offload_capa, dev->tx_offload_capa);
2254 rte_free(eth_dev->data->mac_addrs);
2256 otx2_nix_unregister_irqs(eth_dev);
2258 otx2_eth_dev_lf_detach(dev->mbox);
2262 otx2_dev_fini(pci_dev, dev);
2264 otx2_err("Failed to init nix eth_dev rc=%d", rc);
2269 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
2271 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2272 struct rte_pci_device *pci_dev;
2275 /* Nothing to be done for secondary processes */
2276 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2279 /* Clear the flag since we are closing down */
2280 dev->configured = 0;
2282 /* Disable nix bpid config */
2283 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
2285 npc_rx_disable(dev);
2287 /* Disable vlan offloads */
2288 otx2_nix_vlan_fini(eth_dev);
2290 /* Disable other rte_flow entries */
2291 otx2_flow_fini(dev);
2293 /* Free multicast filter list */
2294 otx2_nix_mc_filter_fini(dev);
2296 /* Disable PTP if already enabled */
2297 if (otx2_ethdev_is_ptp_en(dev))
2298 otx2_nix_timesync_disable(eth_dev);
2300 nix_cgx_stop_link_event(dev);
2303 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
2304 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
2305 eth_dev->data->tx_queues[i] = NULL;
2307 eth_dev->data->nb_tx_queues = 0;
2309 /* Free up RQ's and CQ's */
2310 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2311 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
2312 eth_dev->data->rx_queues[i] = NULL;
2314 eth_dev->data->nb_rx_queues = 0;
2316 /* Free tm resources */
2317 rc = otx2_nix_tm_fini(eth_dev);
2319 otx2_err("Failed to cleanup tm, rc=%d", rc);
2321 /* Unregister queue irqs */
2322 oxt2_nix_unregister_queue_irqs(eth_dev);
2324 /* Unregister cq irqs */
2325 if (eth_dev->data->dev_conf.intr_conf.rxq)
2326 oxt2_nix_unregister_cq_irqs(eth_dev);
2328 rc = nix_lf_free(dev);
2330 otx2_err("Failed to free nix lf, rc=%d", rc);
2332 rc = otx2_npa_lf_fini();
2334 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
2336 rte_free(eth_dev->data->mac_addrs);
2337 eth_dev->data->mac_addrs = NULL;
2338 dev->drv_inited = false;
2340 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2341 otx2_nix_unregister_irqs(eth_dev);
2343 rc = otx2_eth_dev_lf_detach(dev->mbox);
2345 otx2_err("Failed to detach resources, rc=%d", rc);
2347 /* Check if mbox close is needed */
2351 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
2352 /* Will be freed later by PMD */
2353 eth_dev->data->dev_private = NULL;
2357 otx2_dev_fini(pci_dev, dev);
2362 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
2364 otx2_eth_dev_uninit(eth_dev, true);
2368 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
2372 rc = otx2_eth_dev_uninit(eth_dev, false);
2376 return otx2_eth_dev_init(eth_dev);
2380 nix_remove(struct rte_pci_device *pci_dev)
2382 struct rte_eth_dev *eth_dev;
2383 struct otx2_idev_cfg *idev;
2384 struct otx2_dev *otx2_dev;
2387 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
2389 /* Cleanup eth dev */
2390 rc = otx2_eth_dev_uninit(eth_dev, true);
2394 rte_eth_dev_pci_release(eth_dev);
2397 /* Nothing to be done for secondary processes */
2398 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2401 /* Check for common resources */
2402 idev = otx2_intra_dev_get_cfg();
2403 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
2406 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
2408 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
2411 /* Safe to cleanup mbox as no more users */
2412 otx2_dev_fini(pci_dev, otx2_dev);
2417 otx2_info("%s: common resource in use by other devices", pci_dev->name);
2422 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
2426 RTE_SET_USED(pci_drv);
2428 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
2431 /* On error on secondary, recheck if port exists in primary or
2432 * in mid of detach state.
2434 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
2435 if (!rte_eth_dev_allocated(pci_dev->device.name))
2440 static const struct rte_pci_id pci_nix_map[] = {
2442 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
2445 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
2448 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2449 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
2452 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2453 PCI_DEVID_OCTEONTX2_RVU_SDP_PF)
2456 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2457 PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2464 static struct rte_pci_driver pci_nix = {
2465 .id_table = pci_nix_map,
2466 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
2467 RTE_PCI_DRV_INTR_LSC,
2469 .remove = nix_remove,
2472 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
2473 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
2474 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");