1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
8 #include <rte_ethdev_pci.h>
10 #include <rte_malloc.h>
12 #include <rte_mbuf_pool_ops.h>
13 #include <rte_mempool.h>
15 #include "otx2_ethdev.h"
17 static inline uint64_t
18 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
20 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
22 if (otx2_dev_is_vf(dev))
23 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
28 static inline uint64_t
29 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
33 return NIX_TX_OFFLOAD_CAPA;
36 static const struct otx2_dev_ops otx2_dev_ops = {
37 .link_status_update = otx2_eth_dev_link_status_update,
38 .ptp_info_update = otx2_eth_dev_ptp_info_update
42 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
44 struct otx2_mbox *mbox = dev->mbox;
45 struct nix_lf_alloc_req *req;
46 struct nix_lf_alloc_rsp *rsp;
49 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
53 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
54 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
55 req->xqe_sz = NIX_XQESZ_W16;
56 req->rss_sz = dev->rss_info.rss_size;
57 req->rss_grps = NIX_RSS_GRPS;
58 req->npa_func = otx2_npa_pf_func_get();
59 req->sso_func = otx2_sso_pf_func_get();
60 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
61 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
62 DEV_RX_OFFLOAD_UDP_CKSUM)) {
63 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
64 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
67 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
71 dev->sqb_size = rsp->sqb_size;
72 dev->tx_chan_base = rsp->tx_chan_base;
73 dev->rx_chan_base = rsp->rx_chan_base;
74 dev->rx_chan_cnt = rsp->rx_chan_cnt;
75 dev->tx_chan_cnt = rsp->tx_chan_cnt;
76 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
77 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
78 dev->lf_tx_stats = rsp->lf_tx_stats;
79 dev->lf_rx_stats = rsp->lf_rx_stats;
80 dev->cints = rsp->cints;
81 dev->qints = rsp->qints;
82 dev->npc_flow.channel = dev->rx_chan_base;
88 nix_lf_free(struct otx2_eth_dev *dev)
90 struct otx2_mbox *mbox = dev->mbox;
91 struct nix_lf_free_req *req;
92 struct ndc_sync_op *ndc_req;
95 /* Sync NDC-NIX for LF */
96 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
97 ndc_req->nix_lf_tx_sync = 1;
98 ndc_req->nix_lf_rx_sync = 1;
99 rc = otx2_mbox_process(mbox);
101 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
103 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
104 /* Let AF driver free all this nix lf's
105 * NPC entries allocated using NPC MBOX.
109 return otx2_mbox_process(mbox);
113 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
115 struct otx2_mbox *mbox = dev->mbox;
117 if (otx2_dev_is_vf(dev))
120 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
122 return otx2_mbox_process(mbox);
126 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
128 struct otx2_mbox *mbox = dev->mbox;
130 if (otx2_dev_is_vf(dev))
133 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
135 return otx2_mbox_process(mbox);
139 npc_rx_enable(struct otx2_eth_dev *dev)
141 struct otx2_mbox *mbox = dev->mbox;
143 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
145 return otx2_mbox_process(mbox);
149 npc_rx_disable(struct otx2_eth_dev *dev)
151 struct otx2_mbox *mbox = dev->mbox;
153 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
155 return otx2_mbox_process(mbox);
159 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
161 struct otx2_mbox *mbox = dev->mbox;
163 if (otx2_dev_is_vf(dev))
166 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
168 return otx2_mbox_process(mbox);
172 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
174 struct otx2_mbox *mbox = dev->mbox;
176 if (otx2_dev_is_vf(dev))
180 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
182 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
184 return otx2_mbox_process(mbox);
188 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
190 struct otx2_mbox *mbox = dev->mbox;
192 if (otx2_dev_is_vf(dev))
195 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
197 return otx2_mbox_process(mbox);
201 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
207 static inline uint32_t
208 nix_qsize_to_val(enum nix_q_size_e qsize)
210 return (16UL << (qsize * 2));
213 static inline enum nix_q_size_e
214 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
218 if (otx2_ethdev_fixup_is_min_4k_q(dev))
223 for (; i < nix_q_size_max; i++)
224 if (val <= nix_qsize_to_val(i))
227 if (i >= nix_q_size_max)
228 i = nix_q_size_max - 1;
234 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
235 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
237 struct otx2_mbox *mbox = dev->mbox;
238 const struct rte_memzone *rz;
239 uint32_t ring_size, cq_size;
240 struct nix_aq_enq_req *aq;
245 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
246 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
247 NIX_CQ_ALIGN, dev->node);
249 otx2_err("Failed to allocate mem for cq hw ring");
253 memset(rz->addr, 0, rz->len);
254 rxq->desc = (uintptr_t)rz->addr;
255 rxq->qmask = cq_size - 1;
257 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
259 aq->ctype = NIX_AQ_CTYPE_CQ;
260 aq->op = NIX_AQ_INSTOP_INIT;
264 aq->cq.qsize = rxq->qsize;
265 aq->cq.base = rz->iova;
266 aq->cq.avg_level = 0xff;
267 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
268 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
270 /* TX pause frames enable flowctrl on RX side */
271 if (dev->fc_info.tx_pause) {
272 /* Single bpid is allocated for all rx channels for now */
273 aq->cq.bpid = dev->fc_info.bpid[0];
274 aq->cq.bp = NIX_CQ_BP_LEVEL;
278 /* Many to one reduction */
279 aq->cq.qint_idx = qid % dev->qints;
280 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
281 aq->cq.cint_idx = qid;
283 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
284 uint16_t min_rx_drop;
285 const float rx_cq_skid = 1024 * 256;
287 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
288 aq->cq.drop = min_rx_drop;
292 rc = otx2_mbox_process(mbox);
294 otx2_err("Failed to init cq context");
298 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
300 aq->ctype = NIX_AQ_CTYPE_RQ;
301 aq->op = NIX_AQ_INSTOP_INIT;
304 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
306 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
307 first_skip = (sizeof(struct rte_mbuf));
308 first_skip += RTE_PKTMBUF_HEADROOM;
309 first_skip += rte_pktmbuf_priv_size(mp);
310 rxq->data_off = first_skip;
312 first_skip /= 8; /* Expressed in number of dwords */
313 aq->rq.first_skip = first_skip;
314 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
315 aq->rq.flow_tagw = 32; /* 32-bits */
316 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
317 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
318 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
319 aq->rq.lpb_sizem1 /= 8;
320 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
322 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
323 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
324 aq->rq.rq_int_ena = 0;
325 /* Many to one reduction */
326 aq->rq.qint_idx = qid % dev->qints;
328 if (otx2_ethdev_fixup_is_limit_cq_full(dev))
329 aq->rq.xqe_drop_ena = 1;
331 rc = otx2_mbox_process(mbox);
333 otx2_err("Failed to init rq context");
343 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
344 struct otx2_eth_rxq *rxq, const bool enb)
346 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
347 struct otx2_mbox *mbox = dev->mbox;
348 struct nix_aq_enq_req *aq;
350 /* Pkts will be dropped silently if RQ is disabled */
351 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
353 aq->ctype = NIX_AQ_CTYPE_RQ;
354 aq->op = NIX_AQ_INSTOP_WRITE;
357 aq->rq_mask.ena = ~(aq->rq_mask.ena);
359 return otx2_mbox_process(mbox);
363 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
365 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
366 struct otx2_mbox *mbox = dev->mbox;
367 struct nix_aq_enq_req *aq;
370 /* RQ is already disabled */
372 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
374 aq->ctype = NIX_AQ_CTYPE_CQ;
375 aq->op = NIX_AQ_INSTOP_WRITE;
378 aq->cq_mask.ena = ~(aq->cq_mask.ena);
380 rc = otx2_mbox_process(mbox);
382 otx2_err("Failed to disable cq context");
390 nix_get_data_off(struct otx2_eth_dev *dev)
392 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
396 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
398 struct rte_mbuf mb_def;
401 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
402 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
403 offsetof(struct rte_mbuf, data_off) != 2);
404 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
405 offsetof(struct rte_mbuf, data_off) != 4);
406 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
407 offsetof(struct rte_mbuf, data_off) != 6);
409 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
410 mb_def.port = port_id;
411 rte_mbuf_refcnt_set(&mb_def, 1);
413 /* Prevent compiler reordering: rearm_data covers previous fields */
414 rte_compiler_barrier();
415 tmp = (uint64_t *)&mb_def.rearm_data;
421 otx2_nix_rx_queue_release(void *rx_queue)
423 struct otx2_eth_rxq *rxq = rx_queue;
428 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
429 nix_cq_rq_uninit(rxq->eth_dev, rxq);
434 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
435 uint16_t nb_desc, unsigned int socket,
436 const struct rte_eth_rxconf *rx_conf,
437 struct rte_mempool *mp)
439 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
440 struct rte_mempool_ops *ops;
441 struct otx2_eth_rxq *rxq;
442 const char *platform_ops;
443 enum nix_q_size_e qsize;
449 /* Compile time check to make sure all fast path elements in a CL */
450 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
453 if (rx_conf->rx_deferred_start == 1) {
454 otx2_err("Deferred Rx start is not supported");
458 platform_ops = rte_mbuf_platform_mempool_ops();
459 /* This driver needs octeontx2_npa mempool ops to work */
460 ops = rte_mempool_get_ops(mp->ops_index);
461 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
462 otx2_err("mempool ops should be of octeontx2_npa type");
466 if (mp->pool_id == 0) {
467 otx2_err("Invalid pool_id");
471 /* Free memory prior to re-allocation if needed */
472 if (eth_dev->data->rx_queues[rq] != NULL) {
473 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
474 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
475 eth_dev->data->rx_queues[rq] = NULL;
478 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
479 dev->rx_offloads |= offloads;
481 /* Find the CQ queue size */
482 qsize = nix_qsize_clampup_get(dev, nb_desc);
483 /* Allocate rxq memory */
484 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
486 otx2_err("Failed to allocate rq=%d", rq);
491 rxq->eth_dev = eth_dev;
493 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
494 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
495 rxq->wdata = (uint64_t)rq << 32;
496 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
497 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
498 eth_dev->data->port_id);
499 rxq->offloads = offloads;
501 rxq->qlen = nix_qsize_to_val(qsize);
503 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
504 rxq->tstamp = &dev->tstamp;
506 /* Alloc completion queue */
507 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
509 otx2_err("Failed to allocate rxq=%u", rq);
513 rxq->qconf.socket_id = socket;
514 rxq->qconf.nb_desc = nb_desc;
515 rxq->qconf.mempool = mp;
516 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
518 nix_rx_queue_reset(rxq);
519 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
520 rq, mp->name, qsize, nb_desc, rxq->qlen);
522 eth_dev->data->rx_queues[rq] = rxq;
523 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
527 otx2_nix_rx_queue_release(rxq);
532 static inline uint8_t
533 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
536 * Maximum three segments can be supported with W8, Choose
537 * NIX_MAXSQESZ_W16 for multi segment offload.
539 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
540 return NIX_MAXSQESZ_W16;
542 return NIX_MAXSQESZ_W8;
546 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
548 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
549 struct rte_eth_dev_data *data = eth_dev->data;
550 struct rte_eth_conf *conf = &data->dev_conf;
551 struct rte_eth_rxmode *rxmode = &conf->rxmode;
554 if (rxmode->mq_mode == ETH_MQ_RX_RSS)
555 flags |= NIX_RX_OFFLOAD_RSS_F;
557 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
558 DEV_RX_OFFLOAD_UDP_CKSUM))
559 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
561 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
562 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
563 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
565 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
566 flags |= NIX_RX_MULTI_SEG_F;
568 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
569 DEV_RX_OFFLOAD_QINQ_STRIP))
570 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
572 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
573 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
579 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
581 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
582 uint64_t conf = dev->tx_offloads;
585 /* Fastpath is dependent on these enums */
586 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
587 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
588 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
589 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
590 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
591 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
592 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
593 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
594 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
595 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
596 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
597 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
598 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
599 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
600 offsetof(struct rte_mbuf, buf_iova) + 8);
601 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
602 offsetof(struct rte_mbuf, buf_iova) + 16);
603 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
604 offsetof(struct rte_mbuf, ol_flags) + 12);
605 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
606 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
608 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
609 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
610 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
612 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
613 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
614 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
616 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
617 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
618 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
619 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
620 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
622 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
623 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
625 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
626 flags |= NIX_TX_MULTI_SEG_F;
628 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
629 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
635 nix_sq_init(struct otx2_eth_txq *txq)
637 struct otx2_eth_dev *dev = txq->dev;
638 struct otx2_mbox *mbox = dev->mbox;
639 struct nix_aq_enq_req *sq;
644 if (txq->sqb_pool->pool_id == 0)
647 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
649 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
653 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
655 sq->ctype = NIX_AQ_CTYPE_SQ;
656 sq->op = NIX_AQ_INSTOP_INIT;
657 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
660 sq->sq.smq_rr_quantum = rr_quantum;
661 sq->sq.default_chan = dev->tx_chan_base;
662 sq->sq.sqe_stype = NIX_STYPE_STF;
664 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
665 sq->sq.sqe_stype = NIX_STYPE_STP;
667 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
668 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
669 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
670 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
671 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
673 /* Many to one reduction */
674 sq->sq.qint_idx = txq->sq % dev->qints;
676 return otx2_mbox_process(mbox);
680 nix_sq_uninit(struct otx2_eth_txq *txq)
682 struct otx2_eth_dev *dev = txq->dev;
683 struct otx2_mbox *mbox = dev->mbox;
684 struct ndc_sync_op *ndc_req;
685 struct nix_aq_enq_rsp *rsp;
686 struct nix_aq_enq_req *aq;
687 uint16_t sqes_per_sqb;
691 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
693 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
695 aq->ctype = NIX_AQ_CTYPE_SQ;
696 aq->op = NIX_AQ_INSTOP_READ;
698 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
702 /* Check if sq is already cleaned up */
707 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
709 aq->ctype = NIX_AQ_CTYPE_SQ;
710 aq->op = NIX_AQ_INSTOP_WRITE;
712 aq->sq_mask.ena = ~aq->sq_mask.ena;
715 rc = otx2_mbox_process(mbox);
719 /* Read SQ and free sqb's */
720 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
722 aq->ctype = NIX_AQ_CTYPE_SQ;
723 aq->op = NIX_AQ_INSTOP_READ;
725 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
730 otx2_err("SQ has pending sqe's");
732 count = aq->sq.sqb_count;
733 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
734 /* Free SQB's that are used */
735 sqb_buf = (void *)rsp->sq.head_sqb;
739 next_sqb = *(void **)((uintptr_t)sqb_buf + ((sqes_per_sqb - 1) *
740 nix_sq_max_sqe_sz(txq)));
741 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
747 /* Free next to use sqb */
748 if (rsp->sq.next_sqb)
749 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
752 /* Sync NDC-NIX-TX for LF */
753 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
754 ndc_req->nix_lf_tx_sync = 1;
755 rc = otx2_mbox_process(mbox);
757 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
763 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
765 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
766 struct npa_aq_enq_req *aura_req;
768 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
769 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
770 aura_req->ctype = NPA_AQ_CTYPE_AURA;
771 aura_req->op = NPA_AQ_INSTOP_WRITE;
773 aura_req->aura.limit = nb_sqb_bufs;
774 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
776 return otx2_mbox_process(npa_lf->mbox);
780 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
782 struct otx2_eth_dev *dev = txq->dev;
783 uint16_t sqes_per_sqb, nb_sqb_bufs;
784 char name[RTE_MEMPOOL_NAMESIZE];
785 struct rte_mempool_objsz sz;
786 struct npa_aura_s *aura;
787 uint32_t tmp, blk_sz;
789 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
790 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
791 blk_sz = dev->sqb_size;
793 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
794 sqes_per_sqb = (dev->sqb_size / 8) / 16;
796 sqes_per_sqb = (dev->sqb_size / 8) / 8;
798 nb_sqb_bufs = nb_desc / sqes_per_sqb;
799 /* Clamp up to devarg passed SQB count */
800 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_MIN_SQB,
801 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
803 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
805 MEMPOOL_F_NO_SPREAD);
806 txq->nb_sqb_bufs = nb_sqb_bufs;
807 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
808 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
809 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
810 txq->nb_sqb_bufs_adj =
811 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
813 if (txq->sqb_pool == NULL) {
814 otx2_err("Failed to allocate sqe mempool");
818 memset(aura, 0, sizeof(*aura));
820 aura->fc_addr = txq->fc_iova;
821 aura->fc_hyst_bits = 0; /* Store count on all updates */
822 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
823 otx2_err("Failed to set ops for sqe mempool");
826 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
827 otx2_err("Failed to populate sqe mempool");
831 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
832 if (dev->sqb_size != sz.elt_size) {
833 otx2_err("sqe pool block size is not expected %d != %d",
838 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
846 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
848 struct nix_send_ext_s *send_hdr_ext;
849 struct nix_send_hdr_s *send_hdr;
850 struct nix_send_mem_s *send_mem;
851 union nix_send_sg_s *sg;
853 /* Initialize the fields based on basic single segment packet */
854 memset(&txq->cmd, 0, sizeof(txq->cmd));
856 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
857 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
858 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
859 send_hdr->w0.sizem1 = 2;
861 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
862 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
863 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
864 /* Default: one seg packet would have:
865 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
868 send_hdr->w0.sizem1 = 3;
869 send_hdr_ext->w0.tstmp = 1;
871 /* To calculate the offset for send_mem,
872 * send_hdr->w0.sizem1 * 2
874 send_mem = (struct nix_send_mem_s *)(txq->cmd +
875 (send_hdr->w0.sizem1 << 1));
876 send_mem->subdc = NIX_SUBDC_MEM;
877 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
878 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
880 sg = (union nix_send_sg_s *)&txq->cmd[4];
882 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
883 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
884 send_hdr->w0.sizem1 = 1;
885 sg = (union nix_send_sg_s *)&txq->cmd[2];
888 send_hdr->w0.sq = txq->sq;
889 sg->subdc = NIX_SUBDC_SG;
891 sg->ld_type = NIX_SENDLDTYPE_LDD;
897 otx2_nix_tx_queue_release(void *_txq)
899 struct otx2_eth_txq *txq = _txq;
900 struct rte_eth_dev *eth_dev;
905 eth_dev = txq->dev->eth_dev;
907 otx2_nix_dbg("Releasing txq %u", txq->sq);
909 /* Flush and disable tm */
910 otx2_nix_tm_sw_xoff(txq, eth_dev->data->dev_started);
912 /* Free sqb's and disable sq */
916 rte_mempool_free(txq->sqb_pool);
917 txq->sqb_pool = NULL;
924 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
925 uint16_t nb_desc, unsigned int socket_id,
926 const struct rte_eth_txconf *tx_conf)
928 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
929 const struct rte_memzone *fc;
930 struct otx2_eth_txq *txq;
936 /* Compile time check to make sure all fast path elements in a CL */
937 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
939 if (tx_conf->tx_deferred_start) {
940 otx2_err("Tx deferred start is not supported");
944 /* Free memory prior to re-allocation if needed. */
945 if (eth_dev->data->tx_queues[sq] != NULL) {
946 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
947 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
948 eth_dev->data->tx_queues[sq] = NULL;
951 /* Find the expected offloads for this queue */
952 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
954 /* Allocating tx queue data structure */
955 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
956 OTX2_ALIGN, socket_id);
958 otx2_err("Failed to alloc txq=%d", sq);
964 txq->sqb_pool = NULL;
965 txq->offloads = offloads;
966 dev->tx_offloads |= offloads;
969 * Allocate memory for flow control updates from HW.
970 * Alloc one cache line, so that fits all FC_STYPE modes.
972 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
973 OTX2_ALIGN + sizeof(struct npa_aura_s),
974 OTX2_ALIGN, dev->node);
976 otx2_err("Failed to allocate mem for fcmem");
980 txq->fc_iova = fc->iova;
981 txq->fc_mem = fc->addr;
983 /* Initialize the aura sqb pool */
984 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
986 otx2_err("Failed to alloc sqe pool rc=%d", rc);
990 /* Initialize the SQ */
991 rc = nix_sq_init(txq);
993 otx2_err("Failed to init sq=%d context", sq);
997 txq->fc_cache_pkts = 0;
998 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
999 /* Evenly distribute LMT slot for each sq */
1000 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
1002 txq->qconf.socket_id = socket_id;
1003 txq->qconf.nb_desc = nb_desc;
1004 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
1006 otx2_nix_form_default_desc(txq);
1008 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
1009 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
1010 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
1011 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
1012 eth_dev->data->tx_queues[sq] = txq;
1013 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
1017 otx2_nix_tx_queue_release(txq);
1023 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1025 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1026 struct otx2_eth_qconf *tx_qconf = NULL;
1027 struct otx2_eth_qconf *rx_qconf = NULL;
1028 struct otx2_eth_txq **txq;
1029 struct otx2_eth_rxq **rxq;
1030 int i, nb_rxq, nb_txq;
1032 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1033 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1035 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1036 if (tx_qconf == NULL) {
1037 otx2_err("Failed to allocate memory for tx_qconf");
1041 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1042 if (rx_qconf == NULL) {
1043 otx2_err("Failed to allocate memory for rx_qconf");
1047 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1048 for (i = 0; i < nb_txq; i++) {
1049 if (txq[i] == NULL) {
1050 otx2_err("txq[%d] is already released", i);
1053 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1054 otx2_nix_tx_queue_release(txq[i]);
1055 eth_dev->data->tx_queues[i] = NULL;
1058 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1059 for (i = 0; i < nb_rxq; i++) {
1060 if (rxq[i] == NULL) {
1061 otx2_err("rxq[%d] is already released", i);
1064 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1065 otx2_nix_rx_queue_release(rxq[i]);
1066 eth_dev->data->rx_queues[i] = NULL;
1069 dev->tx_qconf = tx_qconf;
1070 dev->rx_qconf = rx_qconf;
1083 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1085 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1086 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1087 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1088 struct otx2_eth_txq **txq;
1089 struct otx2_eth_rxq **rxq;
1090 int rc, i, nb_rxq, nb_txq;
1092 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1093 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1096 /* Setup tx & rx queues with previous configuration so
1097 * that the queues can be functional in cases like ports
1098 * are started without re configuring queues.
1100 * Usual re config sequence is like below:
1101 * port_configure() {
1106 * queue_configure() {
1113 * In some application's control path, queue_configure() would
1114 * NOT be invoked for TXQs/RXQs in port_configure().
1115 * In such cases, queues can be functional after start as the
1116 * queues are already setup in port_configure().
1118 for (i = 0; i < nb_txq; i++) {
1119 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1120 tx_qconf[i].socket_id,
1121 &tx_qconf[i].conf.tx);
1123 otx2_err("Failed to setup tx queue rc=%d", rc);
1124 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1125 for (i -= 1; i >= 0; i--)
1126 otx2_nix_tx_queue_release(txq[i]);
1131 free(tx_qconf); tx_qconf = NULL;
1133 for (i = 0; i < nb_rxq; i++) {
1134 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1135 rx_qconf[i].socket_id,
1136 &rx_qconf[i].conf.rx,
1137 rx_qconf[i].mempool);
1139 otx2_err("Failed to setup rx queue rc=%d", rc);
1140 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1141 for (i -= 1; i >= 0; i--)
1142 otx2_nix_rx_queue_release(rxq[i]);
1143 goto release_tx_queues;
1147 free(rx_qconf); rx_qconf = NULL;
1152 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1153 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1154 otx2_nix_tx_queue_release(txq[i]);
1165 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1167 RTE_SET_USED(queue);
1168 RTE_SET_USED(mbufs);
1175 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1177 /* These dummy functions are required for supporting
1178 * some applications which reconfigure queues without
1179 * stopping tx burst and rx burst threads(eg kni app)
1180 * When the queues context is saved, txq/rxqs are released
1181 * which caused app crash since rx/tx burst is still
1182 * on different lcores
1184 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1185 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1190 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1192 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1193 struct rte_eth_dev_data *data = eth_dev->data;
1194 struct rte_eth_conf *conf = &data->dev_conf;
1195 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1196 struct rte_eth_txmode *txmode = &conf->txmode;
1197 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1198 struct rte_ether_addr *ea;
1199 uint8_t nb_rxq, nb_txq;
1205 if (rte_eal_has_hugepages() == 0) {
1206 otx2_err("Huge page is not configured");
1207 goto fail_configure;
1210 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1211 otx2_err("Setting link speed/duplex not supported");
1212 goto fail_configure;
1215 if (conf->dcb_capability_en == 1) {
1216 otx2_err("dcb enable is not supported");
1217 goto fail_configure;
1220 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1221 otx2_err("Flow director is not supported");
1222 goto fail_configure;
1225 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1226 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1227 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1228 goto fail_configure;
1231 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1232 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1233 goto fail_configure;
1236 if (otx2_dev_is_Ax(dev) &&
1237 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1238 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1239 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1240 otx2_err("Outer IP and SCTP checksum unsupported");
1241 goto fail_configure;
1244 /* Free the resources allocated from the previous configure */
1245 if (dev->configured == 1) {
1246 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1247 otx2_nix_vlan_fini(eth_dev);
1248 otx2_flow_free_all_resources(dev);
1249 oxt2_nix_unregister_queue_irqs(eth_dev);
1250 if (eth_dev->data->dev_conf.intr_conf.rxq)
1251 oxt2_nix_unregister_cq_irqs(eth_dev);
1252 nix_set_nop_rxtx_function(eth_dev);
1253 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1255 goto fail_configure;
1256 otx2_nix_tm_fini(eth_dev);
1260 dev->rx_offloads = rxmode->offloads;
1261 dev->tx_offloads = txmode->offloads;
1262 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1263 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1264 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1266 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1267 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1269 /* Alloc a nix lf */
1270 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1272 otx2_err("Failed to init nix_lf rc=%d", rc);
1277 rc = otx2_nix_rss_config(eth_dev);
1279 otx2_err("Failed to configure rss rc=%d", rc);
1283 /* Init the default TM scheduler hierarchy */
1284 rc = otx2_nix_tm_init_default(eth_dev);
1286 otx2_err("Failed to init traffic manager rc=%d", rc);
1290 rc = otx2_nix_vlan_offload_init(eth_dev);
1292 otx2_err("Failed to init vlan offload rc=%d", rc);
1296 /* Register queue IRQs */
1297 rc = oxt2_nix_register_queue_irqs(eth_dev);
1299 otx2_err("Failed to register queue interrupts rc=%d", rc);
1303 /* Register cq IRQs */
1304 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1305 if (eth_dev->data->nb_rx_queues > dev->cints) {
1306 otx2_err("Rx interrupt cannot be enabled, rxq > %d",
1310 /* Rx interrupt feature cannot work with vector mode because,
1311 * vector mode doesn't process packets unless min 4 pkts are
1312 * received, while cq interrupts are generated even for 1 pkt
1315 dev->scalar_ena = true;
1317 rc = oxt2_nix_register_cq_irqs(eth_dev);
1319 otx2_err("Failed to register CQ interrupts rc=%d", rc);
1324 /* Configure loop back mode */
1325 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1327 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1331 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1333 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1338 * Restore queue config when reconfigure followed by
1339 * reconfigure and no queue configure invoked from application case.
1341 if (dev->configured == 1) {
1342 rc = nix_restore_queue_cfg(eth_dev);
1347 /* Update the mac address */
1348 ea = eth_dev->data->mac_addrs;
1349 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1350 if (rte_is_zero_ether_addr(ea))
1351 rte_eth_random_addr((uint8_t *)ea);
1353 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1355 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1356 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1357 " rx_flags=0x%x tx_flags=0x%x",
1358 eth_dev->data->port_id, ea_fmt, nb_rxq,
1359 nb_txq, dev->rx_offloads, dev->tx_offloads,
1360 dev->rx_offload_flags, dev->tx_offload_flags);
1363 dev->configured = 1;
1364 dev->configured_nb_rx_qs = data->nb_rx_queues;
1365 dev->configured_nb_tx_qs = data->nb_tx_queues;
1369 oxt2_nix_unregister_cq_irqs(eth_dev);
1371 oxt2_nix_unregister_queue_irqs(eth_dev);
1373 otx2_nix_vlan_fini(eth_dev);
1375 otx2_nix_tm_fini(eth_dev);
1379 dev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);
1380 dev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);
1382 dev->configured = 0;
1387 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1389 struct rte_eth_dev_data *data = eth_dev->data;
1390 struct otx2_eth_txq *txq;
1393 txq = eth_dev->data->tx_queues[qidx];
1395 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1398 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1400 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1405 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1412 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1414 struct rte_eth_dev_data *data = eth_dev->data;
1415 struct otx2_eth_txq *txq;
1418 txq = eth_dev->data->tx_queues[qidx];
1420 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1423 txq->fc_cache_pkts = 0;
1425 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1427 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1432 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1439 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1441 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1442 struct rte_eth_dev_data *data = eth_dev->data;
1445 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1448 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1450 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1454 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1461 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1463 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1464 struct rte_eth_dev_data *data = eth_dev->data;
1467 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1470 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1472 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1476 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1483 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
1485 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1486 struct rte_mbuf *rx_pkts[32];
1487 struct otx2_eth_rxq *rxq;
1488 int count, i, j, rc;
1490 nix_cgx_stop_link_event(dev);
1491 npc_rx_disable(dev);
1493 /* Stop rx queues and free up pkts pending */
1494 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1495 rc = otx2_nix_rx_queue_stop(eth_dev, i);
1499 rxq = eth_dev->data->rx_queues[i];
1500 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1502 for (j = 0; j < count; j++)
1503 rte_pktmbuf_free(rx_pkts[j]);
1504 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1508 /* Stop tx queues */
1509 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1510 otx2_nix_tx_queue_stop(eth_dev, i);
1514 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
1516 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1519 if (eth_dev->data->nb_rx_queues != 0) {
1520 rc = otx2_nix_recalc_mtu(eth_dev);
1525 /* Start rx queues */
1526 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1527 rc = otx2_nix_rx_queue_start(eth_dev, i);
1532 /* Start tx queues */
1533 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1534 rc = otx2_nix_tx_queue_start(eth_dev, i);
1539 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
1541 otx2_err("Failed to update flow ctrl mode %d", rc);
1545 /* Enable PTP if it was requested by the app or if it is already
1546 * enabled in PF owning this VF
1548 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
1549 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
1550 otx2_ethdev_is_ptp_en(dev))
1551 otx2_nix_timesync_enable(eth_dev);
1553 otx2_nix_timesync_disable(eth_dev);
1555 rc = npc_rx_enable(dev);
1557 otx2_err("Failed to enable NPC rx %d", rc);
1561 otx2_nix_toggle_flag_link_cfg(dev, true);
1563 rc = nix_cgx_start_link_event(dev);
1565 otx2_err("Failed to start cgx link event %d", rc);
1569 otx2_nix_toggle_flag_link_cfg(dev, false);
1570 otx2_eth_set_tx_function(eth_dev);
1571 otx2_eth_set_rx_function(eth_dev);
1576 npc_rx_disable(dev);
1577 otx2_nix_toggle_flag_link_cfg(dev, false);
1581 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
1582 static void otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
1584 /* Initialize and register driver with DPDK Application */
1585 static const struct eth_dev_ops otx2_eth_dev_ops = {
1586 .dev_infos_get = otx2_nix_info_get,
1587 .dev_configure = otx2_nix_configure,
1588 .link_update = otx2_nix_link_update,
1589 .tx_queue_setup = otx2_nix_tx_queue_setup,
1590 .tx_queue_release = otx2_nix_tx_queue_release,
1591 .rx_queue_setup = otx2_nix_rx_queue_setup,
1592 .rx_queue_release = otx2_nix_rx_queue_release,
1593 .dev_start = otx2_nix_dev_start,
1594 .dev_stop = otx2_nix_dev_stop,
1595 .dev_close = otx2_nix_dev_close,
1596 .tx_queue_start = otx2_nix_tx_queue_start,
1597 .tx_queue_stop = otx2_nix_tx_queue_stop,
1598 .rx_queue_start = otx2_nix_rx_queue_start,
1599 .rx_queue_stop = otx2_nix_rx_queue_stop,
1600 .dev_set_link_up = otx2_nix_dev_set_link_up,
1601 .dev_set_link_down = otx2_nix_dev_set_link_down,
1602 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
1603 .dev_reset = otx2_nix_dev_reset,
1604 .stats_get = otx2_nix_dev_stats_get,
1605 .stats_reset = otx2_nix_dev_stats_reset,
1606 .get_reg = otx2_nix_dev_get_reg,
1607 .mtu_set = otx2_nix_mtu_set,
1608 .mac_addr_add = otx2_nix_mac_addr_add,
1609 .mac_addr_remove = otx2_nix_mac_addr_del,
1610 .mac_addr_set = otx2_nix_mac_addr_set,
1611 .promiscuous_enable = otx2_nix_promisc_enable,
1612 .promiscuous_disable = otx2_nix_promisc_disable,
1613 .allmulticast_enable = otx2_nix_allmulticast_enable,
1614 .allmulticast_disable = otx2_nix_allmulticast_disable,
1615 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
1616 .reta_update = otx2_nix_dev_reta_update,
1617 .reta_query = otx2_nix_dev_reta_query,
1618 .rss_hash_update = otx2_nix_rss_hash_update,
1619 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
1620 .xstats_get = otx2_nix_xstats_get,
1621 .xstats_get_names = otx2_nix_xstats_get_names,
1622 .xstats_reset = otx2_nix_xstats_reset,
1623 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
1624 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
1625 .rxq_info_get = otx2_nix_rxq_info_get,
1626 .txq_info_get = otx2_nix_txq_info_get,
1627 .rx_queue_count = otx2_nix_rx_queue_count,
1628 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
1629 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
1630 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
1631 .pool_ops_supported = otx2_nix_pool_ops_supported,
1632 .filter_ctrl = otx2_nix_dev_filter_ctrl,
1633 .get_module_info = otx2_nix_get_module_info,
1634 .get_module_eeprom = otx2_nix_get_module_eeprom,
1635 .fw_version_get = otx2_nix_fw_version_get,
1636 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
1637 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
1638 .timesync_enable = otx2_nix_timesync_enable,
1639 .timesync_disable = otx2_nix_timesync_disable,
1640 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
1641 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
1642 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
1643 .timesync_read_time = otx2_nix_timesync_read_time,
1644 .timesync_write_time = otx2_nix_timesync_write_time,
1645 .vlan_offload_set = otx2_nix_vlan_offload_set,
1646 .vlan_filter_set = otx2_nix_vlan_filter_set,
1647 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
1648 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
1649 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
1650 .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
1651 .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
1655 nix_lf_attach(struct otx2_eth_dev *dev)
1657 struct otx2_mbox *mbox = dev->mbox;
1658 struct rsrc_attach_req *req;
1660 /* Attach NIX(lf) */
1661 req = otx2_mbox_alloc_msg_attach_resources(mbox);
1665 return otx2_mbox_process(mbox);
1669 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
1671 struct otx2_mbox *mbox = dev->mbox;
1672 struct msix_offset_rsp *msix_rsp;
1675 /* Get NPA and NIX MSIX vector offsets */
1676 otx2_mbox_alloc_msg_msix_offset(mbox);
1678 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
1680 dev->nix_msixoff = msix_rsp->nix_msixoff;
1686 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
1688 struct rsrc_detach_req *req;
1690 req = otx2_mbox_alloc_msg_detach_resources(mbox);
1692 /* Detach all except npa lf */
1693 req->partial = true;
1700 return otx2_mbox_process(mbox);
1704 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
1706 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1707 struct rte_pci_device *pci_dev;
1708 int rc, max_entries;
1710 eth_dev->dev_ops = &otx2_eth_dev_ops;
1712 /* For secondary processes, the primary has done all the work */
1713 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1714 /* Setup callbacks for secondary process */
1715 otx2_eth_set_tx_function(eth_dev);
1716 otx2_eth_set_rx_function(eth_dev);
1720 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1722 rte_eth_copy_pci_info(eth_dev, pci_dev);
1723 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1725 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
1726 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
1727 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
1729 /* Parse devargs string */
1730 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1732 otx2_err("Failed to parse devargs rc=%d", rc);
1736 if (!dev->mbox_active) {
1737 /* Initialize the base otx2_dev object
1738 * only if already present
1740 rc = otx2_dev_init(pci_dev, dev);
1742 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1746 /* Device generic callbacks */
1747 dev->ops = &otx2_dev_ops;
1748 dev->eth_dev = eth_dev;
1750 /* Grab the NPA LF if required */
1751 rc = otx2_npa_lf_init(pci_dev, dev);
1753 goto otx2_dev_uninit;
1755 dev->configured = 0;
1756 dev->drv_inited = true;
1757 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
1758 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
1761 rc = nix_lf_attach(dev);
1763 goto otx2_npa_uninit;
1765 /* Get NIX MSIX offset */
1766 rc = nix_lf_get_msix_offset(dev);
1768 goto otx2_npa_uninit;
1770 /* Register LF irq handlers */
1771 rc = otx2_nix_register_irqs(eth_dev);
1775 /* Get maximum number of supported MAC entries */
1776 max_entries = otx2_cgx_mac_max_entries_get(dev);
1777 if (max_entries < 0) {
1778 otx2_err("Failed to get max entries for mac addr");
1780 goto unregister_irq;
1783 /* For VFs, returned max_entries will be 0. But to keep default MAC
1784 * address, one entry must be allocated. So setting up to 1.
1786 if (max_entries == 0)
1789 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
1790 RTE_ETHER_ADDR_LEN, 0);
1791 if (eth_dev->data->mac_addrs == NULL) {
1792 otx2_err("Failed to allocate memory for mac addr");
1794 goto unregister_irq;
1797 dev->max_mac_entries = max_entries;
1799 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
1801 goto free_mac_addrs;
1803 /* Update the mac address */
1804 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1806 /* Also sync same MAC address to CGX table */
1807 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
1809 /* Initialize the tm data structures */
1810 otx2_nix_tm_conf_init(eth_dev);
1812 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1813 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1815 if (otx2_dev_is_Ax(dev)) {
1816 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
1817 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
1820 /* Initialize rte-flow */
1821 rc = otx2_flow_init(dev);
1823 goto free_mac_addrs;
1825 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
1826 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1827 eth_dev->data->port_id, dev->pf, dev->vf,
1828 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
1829 dev->rx_offload_capa, dev->tx_offload_capa);
1833 rte_free(eth_dev->data->mac_addrs);
1835 otx2_nix_unregister_irqs(eth_dev);
1837 otx2_eth_dev_lf_detach(dev->mbox);
1841 otx2_dev_fini(pci_dev, dev);
1843 otx2_err("Failed to init nix eth_dev rc=%d", rc);
1848 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
1850 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1851 struct rte_pci_device *pci_dev;
1854 /* Nothing to be done for secondary processes */
1855 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1858 /* Clear the flag since we are closing down */
1859 dev->configured = 0;
1861 /* Disable nix bpid config */
1862 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1864 npc_rx_disable(dev);
1866 /* Disable vlan offloads */
1867 otx2_nix_vlan_fini(eth_dev);
1869 /* Disable other rte_flow entries */
1870 otx2_flow_fini(dev);
1872 /* Disable PTP if already enabled */
1873 if (otx2_ethdev_is_ptp_en(dev))
1874 otx2_nix_timesync_disable(eth_dev);
1876 nix_cgx_stop_link_event(dev);
1879 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1880 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
1881 eth_dev->data->tx_queues[i] = NULL;
1883 eth_dev->data->nb_tx_queues = 0;
1885 /* Free up RQ's and CQ's */
1886 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1887 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
1888 eth_dev->data->rx_queues[i] = NULL;
1890 eth_dev->data->nb_rx_queues = 0;
1892 /* Free tm resources */
1893 rc = otx2_nix_tm_fini(eth_dev);
1895 otx2_err("Failed to cleanup tm, rc=%d", rc);
1897 /* Unregister queue irqs */
1898 oxt2_nix_unregister_queue_irqs(eth_dev);
1900 /* Unregister cq irqs */
1901 if (eth_dev->data->dev_conf.intr_conf.rxq)
1902 oxt2_nix_unregister_cq_irqs(eth_dev);
1904 rc = nix_lf_free(dev);
1906 otx2_err("Failed to free nix lf, rc=%d", rc);
1908 rc = otx2_npa_lf_fini();
1910 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
1912 rte_free(eth_dev->data->mac_addrs);
1913 eth_dev->data->mac_addrs = NULL;
1914 dev->drv_inited = false;
1916 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1917 otx2_nix_unregister_irqs(eth_dev);
1919 rc = otx2_eth_dev_lf_detach(dev->mbox);
1921 otx2_err("Failed to detach resources, rc=%d", rc);
1923 /* Check if mbox close is needed */
1927 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
1928 /* Will be freed later by PMD */
1929 eth_dev->data->dev_private = NULL;
1933 otx2_dev_fini(pci_dev, dev);
1938 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
1940 otx2_eth_dev_uninit(eth_dev, true);
1944 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
1948 rc = otx2_eth_dev_uninit(eth_dev, false);
1952 return otx2_eth_dev_init(eth_dev);
1956 nix_remove(struct rte_pci_device *pci_dev)
1958 struct rte_eth_dev *eth_dev;
1959 struct otx2_idev_cfg *idev;
1960 struct otx2_dev *otx2_dev;
1963 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1965 /* Cleanup eth dev */
1966 rc = otx2_eth_dev_uninit(eth_dev, true);
1970 rte_eth_dev_pci_release(eth_dev);
1973 /* Nothing to be done for secondary processes */
1974 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1977 /* Check for common resources */
1978 idev = otx2_intra_dev_get_cfg();
1979 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
1982 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
1984 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
1987 /* Safe to cleanup mbox as no more users */
1988 otx2_dev_fini(pci_dev, otx2_dev);
1993 otx2_info("%s: common resource in use by other devices", pci_dev->name);
1998 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
2002 RTE_SET_USED(pci_drv);
2004 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
2007 /* On error on secondary, recheck if port exists in primary or
2008 * in mid of detach state.
2010 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
2011 if (!rte_eth_dev_allocated(pci_dev->device.name))
2016 static const struct rte_pci_id pci_nix_map[] = {
2018 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
2021 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
2024 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2025 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
2032 static struct rte_pci_driver pci_nix = {
2033 .id_table = pci_nix_map,
2034 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
2035 RTE_PCI_DRV_INTR_LSC,
2037 .remove = nix_remove,
2040 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
2041 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
2042 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");