1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
8 #include <rte_ethdev_pci.h>
10 #include <rte_malloc.h>
12 #include <rte_mbuf_pool_ops.h>
13 #include <rte_mempool.h>
15 #include "otx2_ethdev.h"
18 otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev)
20 RTE_SET_USED(eth_dev);
24 otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev)
26 RTE_SET_USED(eth_dev);
29 static inline uint64_t
30 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
32 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
34 if (otx2_dev_is_vf(dev))
35 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
40 static inline uint64_t
41 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
45 return NIX_TX_OFFLOAD_CAPA;
48 static const struct otx2_dev_ops otx2_dev_ops = {
49 .link_status_update = otx2_eth_dev_link_status_update,
50 .ptp_info_update = otx2_eth_dev_ptp_info_update
54 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
56 struct otx2_mbox *mbox = dev->mbox;
57 struct nix_lf_alloc_req *req;
58 struct nix_lf_alloc_rsp *rsp;
61 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
65 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
66 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
67 req->xqe_sz = NIX_XQESZ_W16;
68 req->rss_sz = dev->rss_info.rss_size;
69 req->rss_grps = NIX_RSS_GRPS;
70 req->npa_func = otx2_npa_pf_func_get();
71 req->sso_func = otx2_sso_pf_func_get();
72 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
73 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
74 DEV_RX_OFFLOAD_UDP_CKSUM)) {
75 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
76 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
79 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
83 dev->sqb_size = rsp->sqb_size;
84 dev->tx_chan_base = rsp->tx_chan_base;
85 dev->rx_chan_base = rsp->rx_chan_base;
86 dev->rx_chan_cnt = rsp->rx_chan_cnt;
87 dev->tx_chan_cnt = rsp->tx_chan_cnt;
88 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
89 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
90 dev->lf_tx_stats = rsp->lf_tx_stats;
91 dev->lf_rx_stats = rsp->lf_rx_stats;
92 dev->cints = rsp->cints;
93 dev->qints = rsp->qints;
94 dev->npc_flow.channel = dev->rx_chan_base;
100 nix_lf_free(struct otx2_eth_dev *dev)
102 struct otx2_mbox *mbox = dev->mbox;
103 struct nix_lf_free_req *req;
104 struct ndc_sync_op *ndc_req;
107 /* Sync NDC-NIX for LF */
108 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
109 ndc_req->nix_lf_tx_sync = 1;
110 ndc_req->nix_lf_rx_sync = 1;
111 rc = otx2_mbox_process(mbox);
113 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
115 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
116 /* Let AF driver free all this nix lf's
117 * NPC entries allocated using NPC MBOX.
121 return otx2_mbox_process(mbox);
125 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
127 struct otx2_mbox *mbox = dev->mbox;
129 if (otx2_dev_is_vf(dev))
132 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
134 return otx2_mbox_process(mbox);
138 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
140 struct otx2_mbox *mbox = dev->mbox;
142 if (otx2_dev_is_vf(dev))
145 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
147 return otx2_mbox_process(mbox);
151 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
157 static inline uint32_t
158 nix_qsize_to_val(enum nix_q_size_e qsize)
160 return (16UL << (qsize * 2));
163 static inline enum nix_q_size_e
164 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
168 if (otx2_ethdev_fixup_is_min_4k_q(dev))
173 for (; i < nix_q_size_max; i++)
174 if (val <= nix_qsize_to_val(i))
177 if (i >= nix_q_size_max)
178 i = nix_q_size_max - 1;
184 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
185 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
187 struct otx2_mbox *mbox = dev->mbox;
188 const struct rte_memzone *rz;
189 uint32_t ring_size, cq_size;
190 struct nix_aq_enq_req *aq;
195 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
196 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
197 NIX_CQ_ALIGN, dev->node);
199 otx2_err("Failed to allocate mem for cq hw ring");
203 memset(rz->addr, 0, rz->len);
204 rxq->desc = (uintptr_t)rz->addr;
205 rxq->qmask = cq_size - 1;
207 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
209 aq->ctype = NIX_AQ_CTYPE_CQ;
210 aq->op = NIX_AQ_INSTOP_INIT;
214 aq->cq.qsize = rxq->qsize;
215 aq->cq.base = rz->iova;
216 aq->cq.avg_level = 0xff;
217 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
218 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
220 /* TX pause frames enable flowctrl on RX side */
221 if (dev->fc_info.tx_pause) {
222 /* Single bpid is allocated for all rx channels for now */
223 aq->cq.bpid = dev->fc_info.bpid[0];
224 aq->cq.bp = NIX_CQ_BP_LEVEL;
228 /* Many to one reduction */
229 aq->cq.qint_idx = qid % dev->qints;
231 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
232 uint16_t min_rx_drop;
233 const float rx_cq_skid = 1024 * 256;
235 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
236 aq->cq.drop = min_rx_drop;
240 rc = otx2_mbox_process(mbox);
242 otx2_err("Failed to init cq context");
246 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
248 aq->ctype = NIX_AQ_CTYPE_RQ;
249 aq->op = NIX_AQ_INSTOP_INIT;
252 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
254 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
255 first_skip = (sizeof(struct rte_mbuf));
256 first_skip += RTE_PKTMBUF_HEADROOM;
257 first_skip += rte_pktmbuf_priv_size(mp);
258 rxq->data_off = first_skip;
260 first_skip /= 8; /* Expressed in number of dwords */
261 aq->rq.first_skip = first_skip;
262 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
263 aq->rq.flow_tagw = 32; /* 32-bits */
264 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
265 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
266 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
267 aq->rq.lpb_sizem1 /= 8;
268 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
270 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
271 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
272 aq->rq.rq_int_ena = 0;
273 /* Many to one reduction */
274 aq->rq.qint_idx = qid % dev->qints;
276 if (otx2_ethdev_fixup_is_limit_cq_full(dev))
277 aq->rq.xqe_drop_ena = 1;
279 rc = otx2_mbox_process(mbox);
281 otx2_err("Failed to init rq context");
291 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
292 struct otx2_eth_rxq *rxq, const bool enb)
294 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
295 struct otx2_mbox *mbox = dev->mbox;
296 struct nix_aq_enq_req *aq;
298 /* Pkts will be dropped silently if RQ is disabled */
299 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
301 aq->ctype = NIX_AQ_CTYPE_RQ;
302 aq->op = NIX_AQ_INSTOP_WRITE;
305 aq->rq_mask.ena = ~(aq->rq_mask.ena);
307 return otx2_mbox_process(mbox);
311 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
313 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
314 struct otx2_mbox *mbox = dev->mbox;
315 struct nix_aq_enq_req *aq;
318 /* RQ is already disabled */
320 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
322 aq->ctype = NIX_AQ_CTYPE_CQ;
323 aq->op = NIX_AQ_INSTOP_WRITE;
326 aq->cq_mask.ena = ~(aq->cq_mask.ena);
328 rc = otx2_mbox_process(mbox);
330 otx2_err("Failed to disable cq context");
338 nix_get_data_off(struct otx2_eth_dev *dev)
340 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
344 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
346 struct rte_mbuf mb_def;
349 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
350 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
351 offsetof(struct rte_mbuf, data_off) != 2);
352 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
353 offsetof(struct rte_mbuf, data_off) != 4);
354 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
355 offsetof(struct rte_mbuf, data_off) != 6);
357 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
358 mb_def.port = port_id;
359 rte_mbuf_refcnt_set(&mb_def, 1);
361 /* Prevent compiler reordering: rearm_data covers previous fields */
362 rte_compiler_barrier();
363 tmp = (uint64_t *)&mb_def.rearm_data;
369 otx2_nix_rx_queue_release(void *rx_queue)
371 struct otx2_eth_rxq *rxq = rx_queue;
376 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
377 nix_cq_rq_uninit(rxq->eth_dev, rxq);
382 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
383 uint16_t nb_desc, unsigned int socket,
384 const struct rte_eth_rxconf *rx_conf,
385 struct rte_mempool *mp)
387 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
388 struct rte_mempool_ops *ops;
389 struct otx2_eth_rxq *rxq;
390 const char *platform_ops;
391 enum nix_q_size_e qsize;
397 /* Compile time check to make sure all fast path elements in a CL */
398 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
401 if (rx_conf->rx_deferred_start == 1) {
402 otx2_err("Deferred Rx start is not supported");
406 platform_ops = rte_mbuf_platform_mempool_ops();
407 /* This driver needs octeontx2_npa mempool ops to work */
408 ops = rte_mempool_get_ops(mp->ops_index);
409 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
410 otx2_err("mempool ops should be of octeontx2_npa type");
414 if (mp->pool_id == 0) {
415 otx2_err("Invalid pool_id");
419 /* Free memory prior to re-allocation if needed */
420 if (eth_dev->data->rx_queues[rq] != NULL) {
421 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
422 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
423 eth_dev->data->rx_queues[rq] = NULL;
426 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
427 dev->rx_offloads |= offloads;
429 /* Find the CQ queue size */
430 qsize = nix_qsize_clampup_get(dev, nb_desc);
431 /* Allocate rxq memory */
432 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
434 otx2_err("Failed to allocate rq=%d", rq);
439 rxq->eth_dev = eth_dev;
441 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
442 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
443 rxq->wdata = (uint64_t)rq << 32;
444 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
445 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
446 eth_dev->data->port_id);
447 rxq->offloads = offloads;
449 rxq->qlen = nix_qsize_to_val(qsize);
451 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
452 rxq->tstamp = &dev->tstamp;
454 /* Alloc completion queue */
455 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
457 otx2_err("Failed to allocate rxq=%u", rq);
461 rxq->qconf.socket_id = socket;
462 rxq->qconf.nb_desc = nb_desc;
463 rxq->qconf.mempool = mp;
464 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
466 nix_rx_queue_reset(rxq);
467 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
468 rq, mp->name, qsize, nb_desc, rxq->qlen);
470 eth_dev->data->rx_queues[rq] = rxq;
471 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
475 otx2_nix_rx_queue_release(rxq);
480 static inline uint8_t
481 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
484 * Maximum three segments can be supported with W8, Choose
485 * NIX_MAXSQESZ_W16 for multi segment offload.
487 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
488 return NIX_MAXSQESZ_W16;
490 return NIX_MAXSQESZ_W8;
494 nix_sq_init(struct otx2_eth_txq *txq)
496 struct otx2_eth_dev *dev = txq->dev;
497 struct otx2_mbox *mbox = dev->mbox;
498 struct nix_aq_enq_req *sq;
503 if (txq->sqb_pool->pool_id == 0)
506 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
508 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
512 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
514 sq->ctype = NIX_AQ_CTYPE_SQ;
515 sq->op = NIX_AQ_INSTOP_INIT;
516 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
519 sq->sq.smq_rr_quantum = rr_quantum;
520 sq->sq.default_chan = dev->tx_chan_base;
521 sq->sq.sqe_stype = NIX_STYPE_STF;
523 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
524 sq->sq.sqe_stype = NIX_STYPE_STP;
526 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
527 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
528 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
529 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
530 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
532 /* Many to one reduction */
533 sq->sq.qint_idx = txq->sq % dev->qints;
535 return otx2_mbox_process(mbox);
539 nix_sq_uninit(struct otx2_eth_txq *txq)
541 struct otx2_eth_dev *dev = txq->dev;
542 struct otx2_mbox *mbox = dev->mbox;
543 struct ndc_sync_op *ndc_req;
544 struct nix_aq_enq_rsp *rsp;
545 struct nix_aq_enq_req *aq;
546 uint16_t sqes_per_sqb;
550 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
552 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
554 aq->ctype = NIX_AQ_CTYPE_SQ;
555 aq->op = NIX_AQ_INSTOP_READ;
557 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
561 /* Check if sq is already cleaned up */
566 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
568 aq->ctype = NIX_AQ_CTYPE_SQ;
569 aq->op = NIX_AQ_INSTOP_WRITE;
571 aq->sq_mask.ena = ~aq->sq_mask.ena;
574 rc = otx2_mbox_process(mbox);
578 /* Read SQ and free sqb's */
579 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
581 aq->ctype = NIX_AQ_CTYPE_SQ;
582 aq->op = NIX_AQ_INSTOP_READ;
584 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
589 otx2_err("SQ has pending sqe's");
591 count = aq->sq.sqb_count;
592 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
593 /* Free SQB's that are used */
594 sqb_buf = (void *)rsp->sq.head_sqb;
598 next_sqb = *(void **)((uintptr_t)sqb_buf + ((sqes_per_sqb - 1) *
599 nix_sq_max_sqe_sz(txq)));
600 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
606 /* Free next to use sqb */
607 if (rsp->sq.next_sqb)
608 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
611 /* Sync NDC-NIX-TX for LF */
612 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
613 ndc_req->nix_lf_tx_sync = 1;
614 rc = otx2_mbox_process(mbox);
616 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
622 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
624 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
625 struct npa_aq_enq_req *aura_req;
627 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
628 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
629 aura_req->ctype = NPA_AQ_CTYPE_AURA;
630 aura_req->op = NPA_AQ_INSTOP_WRITE;
632 aura_req->aura.limit = nb_sqb_bufs;
633 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
635 return otx2_mbox_process(npa_lf->mbox);
639 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
641 struct otx2_eth_dev *dev = txq->dev;
642 uint16_t sqes_per_sqb, nb_sqb_bufs;
643 char name[RTE_MEMPOOL_NAMESIZE];
644 struct rte_mempool_objsz sz;
645 struct npa_aura_s *aura;
646 uint32_t tmp, blk_sz;
648 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
649 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
650 blk_sz = dev->sqb_size;
652 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
653 sqes_per_sqb = (dev->sqb_size / 8) / 16;
655 sqes_per_sqb = (dev->sqb_size / 8) / 8;
657 nb_sqb_bufs = nb_desc / sqes_per_sqb;
658 /* Clamp up to devarg passed SQB count */
659 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_MIN_SQB,
660 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
662 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
664 MEMPOOL_F_NO_SPREAD);
665 txq->nb_sqb_bufs = nb_sqb_bufs;
666 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
667 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
668 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
669 txq->nb_sqb_bufs_adj =
670 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
672 if (txq->sqb_pool == NULL) {
673 otx2_err("Failed to allocate sqe mempool");
677 memset(aura, 0, sizeof(*aura));
679 aura->fc_addr = txq->fc_iova;
680 aura->fc_hyst_bits = 0; /* Store count on all updates */
681 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
682 otx2_err("Failed to set ops for sqe mempool");
685 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
686 otx2_err("Failed to populate sqe mempool");
690 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
691 if (dev->sqb_size != sz.elt_size) {
692 otx2_err("sqe pool block size is not expected %d != %d",
697 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
705 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
707 struct nix_send_ext_s *send_hdr_ext;
708 struct nix_send_hdr_s *send_hdr;
709 struct nix_send_mem_s *send_mem;
710 union nix_send_sg_s *sg;
712 /* Initialize the fields based on basic single segment packet */
713 memset(&txq->cmd, 0, sizeof(txq->cmd));
715 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
716 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
717 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
718 send_hdr->w0.sizem1 = 2;
720 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
721 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
722 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
723 /* Default: one seg packet would have:
724 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
727 send_hdr->w0.sizem1 = 3;
728 send_hdr_ext->w0.tstmp = 1;
730 /* To calculate the offset for send_mem,
731 * send_hdr->w0.sizem1 * 2
733 send_mem = (struct nix_send_mem_s *)(txq->cmd +
734 (send_hdr->w0.sizem1 << 1));
735 send_mem->subdc = NIX_SUBDC_MEM;
737 send_mem->wmem = 0x1;
738 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
739 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
741 sg = (union nix_send_sg_s *)&txq->cmd[4];
743 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
744 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
745 send_hdr->w0.sizem1 = 1;
746 sg = (union nix_send_sg_s *)&txq->cmd[2];
749 send_hdr->w0.sq = txq->sq;
750 sg->subdc = NIX_SUBDC_SG;
752 sg->ld_type = NIX_SENDLDTYPE_LDD;
758 otx2_nix_tx_queue_release(void *_txq)
760 struct otx2_eth_txq *txq = _txq;
761 struct rte_eth_dev *eth_dev;
766 eth_dev = txq->dev->eth_dev;
768 otx2_nix_dbg("Releasing txq %u", txq->sq);
770 /* Flush and disable tm */
771 otx2_nix_tm_sw_xoff(txq, eth_dev->data->dev_started);
773 /* Free sqb's and disable sq */
777 rte_mempool_free(txq->sqb_pool);
778 txq->sqb_pool = NULL;
785 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
786 uint16_t nb_desc, unsigned int socket_id,
787 const struct rte_eth_txconf *tx_conf)
789 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
790 const struct rte_memzone *fc;
791 struct otx2_eth_txq *txq;
797 /* Compile time check to make sure all fast path elements in a CL */
798 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
800 if (tx_conf->tx_deferred_start) {
801 otx2_err("Tx deferred start is not supported");
805 /* Free memory prior to re-allocation if needed. */
806 if (eth_dev->data->tx_queues[sq] != NULL) {
807 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
808 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
809 eth_dev->data->tx_queues[sq] = NULL;
812 /* Find the expected offloads for this queue */
813 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
815 /* Allocating tx queue data structure */
816 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
817 OTX2_ALIGN, socket_id);
819 otx2_err("Failed to alloc txq=%d", sq);
825 txq->sqb_pool = NULL;
826 txq->offloads = offloads;
827 dev->tx_offloads |= offloads;
830 * Allocate memory for flow control updates from HW.
831 * Alloc one cache line, so that fits all FC_STYPE modes.
833 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
834 OTX2_ALIGN + sizeof(struct npa_aura_s),
835 OTX2_ALIGN, dev->node);
837 otx2_err("Failed to allocate mem for fcmem");
841 txq->fc_iova = fc->iova;
842 txq->fc_mem = fc->addr;
844 /* Initialize the aura sqb pool */
845 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
847 otx2_err("Failed to alloc sqe pool rc=%d", rc);
851 /* Initialize the SQ */
852 rc = nix_sq_init(txq);
854 otx2_err("Failed to init sq=%d context", sq);
858 txq->fc_cache_pkts = 0;
859 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
860 /* Evenly distribute LMT slot for each sq */
861 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
863 txq->qconf.socket_id = socket_id;
864 txq->qconf.nb_desc = nb_desc;
865 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
867 otx2_nix_form_default_desc(txq);
869 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
870 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
871 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
872 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
873 eth_dev->data->tx_queues[sq] = txq;
874 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
878 otx2_nix_tx_queue_release(txq);
884 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
886 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
887 struct otx2_eth_qconf *tx_qconf = NULL;
888 struct otx2_eth_qconf *rx_qconf = NULL;
889 struct otx2_eth_txq **txq;
890 struct otx2_eth_rxq **rxq;
891 int i, nb_rxq, nb_txq;
893 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
894 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
896 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
897 if (tx_qconf == NULL) {
898 otx2_err("Failed to allocate memory for tx_qconf");
902 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
903 if (rx_qconf == NULL) {
904 otx2_err("Failed to allocate memory for rx_qconf");
908 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
909 for (i = 0; i < nb_txq; i++) {
910 if (txq[i] == NULL) {
911 otx2_err("txq[%d] is already released", i);
914 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
915 otx2_nix_tx_queue_release(txq[i]);
916 eth_dev->data->tx_queues[i] = NULL;
919 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
920 for (i = 0; i < nb_rxq; i++) {
921 if (rxq[i] == NULL) {
922 otx2_err("rxq[%d] is already released", i);
925 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
926 otx2_nix_rx_queue_release(rxq[i]);
927 eth_dev->data->rx_queues[i] = NULL;
930 dev->tx_qconf = tx_qconf;
931 dev->rx_qconf = rx_qconf;
944 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
946 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
947 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
948 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
949 struct otx2_eth_txq **txq;
950 struct otx2_eth_rxq **rxq;
951 int rc, i, nb_rxq, nb_txq;
953 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
954 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
957 /* Setup tx & rx queues with previous configuration so
958 * that the queues can be functional in cases like ports
959 * are started without re configuring queues.
961 * Usual re config sequence is like below:
967 * queue_configure() {
974 * In some application's control path, queue_configure() would
975 * NOT be invoked for TXQs/RXQs in port_configure().
976 * In such cases, queues can be functional after start as the
977 * queues are already setup in port_configure().
979 for (i = 0; i < nb_txq; i++) {
980 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
981 tx_qconf[i].socket_id,
982 &tx_qconf[i].conf.tx);
984 otx2_err("Failed to setup tx queue rc=%d", rc);
985 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
986 for (i -= 1; i >= 0; i--)
987 otx2_nix_tx_queue_release(txq[i]);
992 free(tx_qconf); tx_qconf = NULL;
994 for (i = 0; i < nb_rxq; i++) {
995 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
996 rx_qconf[i].socket_id,
997 &rx_qconf[i].conf.rx,
998 rx_qconf[i].mempool);
1000 otx2_err("Failed to setup rx queue rc=%d", rc);
1001 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1002 for (i -= 1; i >= 0; i--)
1003 otx2_nix_rx_queue_release(rxq[i]);
1004 goto release_tx_queues;
1008 free(rx_qconf); rx_qconf = NULL;
1013 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1014 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1015 otx2_nix_tx_queue_release(txq[i]);
1026 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1028 RTE_SET_USED(queue);
1029 RTE_SET_USED(mbufs);
1036 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1038 /* These dummy functions are required for supporting
1039 * some applications which reconfigure queues without
1040 * stopping tx burst and rx burst threads(eg kni app)
1041 * When the queues context is saved, txq/rxqs are released
1042 * which caused app crash since rx/tx burst is still
1043 * on different lcores
1045 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1046 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1051 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1053 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1054 struct rte_eth_dev_data *data = eth_dev->data;
1055 struct rte_eth_conf *conf = &data->dev_conf;
1056 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1057 struct rte_eth_txmode *txmode = &conf->txmode;
1058 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1059 struct rte_ether_addr *ea;
1060 uint8_t nb_rxq, nb_txq;
1066 if (rte_eal_has_hugepages() == 0) {
1067 otx2_err("Huge page is not configured");
1071 if (rte_eal_iova_mode() != RTE_IOVA_VA) {
1072 otx2_err("iova mode should be va");
1076 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1077 otx2_err("Setting link speed/duplex not supported");
1081 if (conf->dcb_capability_en == 1) {
1082 otx2_err("dcb enable is not supported");
1086 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1087 otx2_err("Flow director is not supported");
1091 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1092 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1093 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1097 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1098 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1102 /* Free the resources allocated from the previous configure */
1103 if (dev->configured == 1) {
1104 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1105 oxt2_nix_unregister_queue_irqs(eth_dev);
1106 nix_set_nop_rxtx_function(eth_dev);
1107 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1110 otx2_nix_tm_fini(eth_dev);
1114 if (otx2_dev_is_A0(dev) &&
1115 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1116 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1117 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1118 otx2_err("Outer IP and SCTP checksum unsupported");
1123 dev->rx_offloads = rxmode->offloads;
1124 dev->tx_offloads = txmode->offloads;
1125 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1127 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1128 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1130 /* Alloc a nix lf */
1131 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1133 otx2_err("Failed to init nix_lf rc=%d", rc);
1138 rc = otx2_nix_rss_config(eth_dev);
1140 otx2_err("Failed to configure rss rc=%d", rc);
1144 /* Init the default TM scheduler hierarchy */
1145 rc = otx2_nix_tm_init_default(eth_dev);
1147 otx2_err("Failed to init traffic manager rc=%d", rc);
1151 /* Register queue IRQs */
1152 rc = oxt2_nix_register_queue_irqs(eth_dev);
1154 otx2_err("Failed to register queue interrupts rc=%d", rc);
1158 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1160 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1164 /* Enable PTP if it was requested by the app or if it is already
1165 * enabled in PF owning this VF
1167 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
1168 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
1169 otx2_ethdev_is_ptp_en(dev))
1170 otx2_nix_timesync_enable(eth_dev);
1172 otx2_nix_timesync_disable(eth_dev);
1175 * Restore queue config when reconfigure followed by
1176 * reconfigure and no queue configure invoked from application case.
1178 if (dev->configured == 1) {
1179 rc = nix_restore_queue_cfg(eth_dev);
1184 /* Update the mac address */
1185 ea = eth_dev->data->mac_addrs;
1186 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1187 if (rte_is_zero_ether_addr(ea))
1188 rte_eth_random_addr((uint8_t *)ea);
1190 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1192 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1193 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1194 " rx_flags=0x%x tx_flags=0x%x",
1195 eth_dev->data->port_id, ea_fmt, nb_rxq,
1196 nb_txq, dev->rx_offloads, dev->tx_offloads,
1197 dev->rx_offload_flags, dev->tx_offload_flags);
1200 dev->configured = 1;
1201 dev->configured_nb_rx_qs = data->nb_rx_queues;
1202 dev->configured_nb_tx_qs = data->nb_tx_queues;
1206 rc = nix_lf_free(dev);
1212 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1214 struct rte_eth_dev_data *data = eth_dev->data;
1215 struct otx2_eth_txq *txq;
1218 txq = eth_dev->data->tx_queues[qidx];
1220 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1223 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1225 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1230 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1237 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1239 struct rte_eth_dev_data *data = eth_dev->data;
1240 struct otx2_eth_txq *txq;
1243 txq = eth_dev->data->tx_queues[qidx];
1245 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1248 txq->fc_cache_pkts = 0;
1250 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1252 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1257 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1264 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1266 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1267 struct rte_eth_dev_data *data = eth_dev->data;
1270 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1273 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1275 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1279 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1286 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1288 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1289 struct rte_eth_dev_data *data = eth_dev->data;
1292 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1295 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1297 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1301 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1307 /* Initialize and register driver with DPDK Application */
1308 static const struct eth_dev_ops otx2_eth_dev_ops = {
1309 .dev_infos_get = otx2_nix_info_get,
1310 .dev_configure = otx2_nix_configure,
1311 .link_update = otx2_nix_link_update,
1312 .tx_queue_setup = otx2_nix_tx_queue_setup,
1313 .tx_queue_release = otx2_nix_tx_queue_release,
1314 .rx_queue_setup = otx2_nix_rx_queue_setup,
1315 .rx_queue_release = otx2_nix_rx_queue_release,
1316 .tx_queue_start = otx2_nix_tx_queue_start,
1317 .tx_queue_stop = otx2_nix_tx_queue_stop,
1318 .rx_queue_start = otx2_nix_rx_queue_start,
1319 .rx_queue_stop = otx2_nix_rx_queue_stop,
1320 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
1321 .stats_get = otx2_nix_dev_stats_get,
1322 .stats_reset = otx2_nix_dev_stats_reset,
1323 .get_reg = otx2_nix_dev_get_reg,
1324 .mac_addr_add = otx2_nix_mac_addr_add,
1325 .mac_addr_remove = otx2_nix_mac_addr_del,
1326 .mac_addr_set = otx2_nix_mac_addr_set,
1327 .promiscuous_enable = otx2_nix_promisc_enable,
1328 .promiscuous_disable = otx2_nix_promisc_disable,
1329 .allmulticast_enable = otx2_nix_allmulticast_enable,
1330 .allmulticast_disable = otx2_nix_allmulticast_disable,
1331 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
1332 .reta_update = otx2_nix_dev_reta_update,
1333 .reta_query = otx2_nix_dev_reta_query,
1334 .rss_hash_update = otx2_nix_rss_hash_update,
1335 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
1336 .xstats_get = otx2_nix_xstats_get,
1337 .xstats_get_names = otx2_nix_xstats_get_names,
1338 .xstats_reset = otx2_nix_xstats_reset,
1339 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
1340 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
1341 .rxq_info_get = otx2_nix_rxq_info_get,
1342 .txq_info_get = otx2_nix_txq_info_get,
1343 .rx_queue_count = otx2_nix_rx_queue_count,
1344 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
1345 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
1346 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
1347 .pool_ops_supported = otx2_nix_pool_ops_supported,
1348 .filter_ctrl = otx2_nix_dev_filter_ctrl,
1349 .get_module_info = otx2_nix_get_module_info,
1350 .get_module_eeprom = otx2_nix_get_module_eeprom,
1351 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
1352 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
1353 .timesync_enable = otx2_nix_timesync_enable,
1354 .timesync_disable = otx2_nix_timesync_disable,
1355 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
1356 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
1357 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
1358 .timesync_read_time = otx2_nix_timesync_read_time,
1359 .timesync_write_time = otx2_nix_timesync_write_time,
1363 nix_lf_attach(struct otx2_eth_dev *dev)
1365 struct otx2_mbox *mbox = dev->mbox;
1366 struct rsrc_attach_req *req;
1368 /* Attach NIX(lf) */
1369 req = otx2_mbox_alloc_msg_attach_resources(mbox);
1373 return otx2_mbox_process(mbox);
1377 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
1379 struct otx2_mbox *mbox = dev->mbox;
1380 struct msix_offset_rsp *msix_rsp;
1383 /* Get NPA and NIX MSIX vector offsets */
1384 otx2_mbox_alloc_msg_msix_offset(mbox);
1386 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
1388 dev->nix_msixoff = msix_rsp->nix_msixoff;
1394 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
1396 struct rsrc_detach_req *req;
1398 req = otx2_mbox_alloc_msg_detach_resources(mbox);
1400 /* Detach all except npa lf */
1401 req->partial = true;
1408 return otx2_mbox_process(mbox);
1412 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
1414 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1415 struct rte_pci_device *pci_dev;
1416 int rc, max_entries;
1418 eth_dev->dev_ops = &otx2_eth_dev_ops;
1420 /* For secondary processes, the primary has done all the work */
1421 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1422 /* Setup callbacks for secondary process */
1423 otx2_eth_set_tx_function(eth_dev);
1424 otx2_eth_set_rx_function(eth_dev);
1428 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1430 rte_eth_copy_pci_info(eth_dev, pci_dev);
1431 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1433 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
1434 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
1435 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
1437 /* Parse devargs string */
1438 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1440 otx2_err("Failed to parse devargs rc=%d", rc);
1444 if (!dev->mbox_active) {
1445 /* Initialize the base otx2_dev object
1446 * only if already present
1448 rc = otx2_dev_init(pci_dev, dev);
1450 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1454 /* Device generic callbacks */
1455 dev->ops = &otx2_dev_ops;
1456 dev->eth_dev = eth_dev;
1458 /* Grab the NPA LF if required */
1459 rc = otx2_npa_lf_init(pci_dev, dev);
1461 goto otx2_dev_uninit;
1463 dev->configured = 0;
1464 dev->drv_inited = true;
1465 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
1466 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
1469 rc = nix_lf_attach(dev);
1471 goto otx2_npa_uninit;
1473 /* Get NIX MSIX offset */
1474 rc = nix_lf_get_msix_offset(dev);
1476 goto otx2_npa_uninit;
1478 /* Register LF irq handlers */
1479 rc = otx2_nix_register_irqs(eth_dev);
1483 /* Get maximum number of supported MAC entries */
1484 max_entries = otx2_cgx_mac_max_entries_get(dev);
1485 if (max_entries < 0) {
1486 otx2_err("Failed to get max entries for mac addr");
1488 goto unregister_irq;
1491 /* For VFs, returned max_entries will be 0. But to keep default MAC
1492 * address, one entry must be allocated. So setting up to 1.
1494 if (max_entries == 0)
1497 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
1498 RTE_ETHER_ADDR_LEN, 0);
1499 if (eth_dev->data->mac_addrs == NULL) {
1500 otx2_err("Failed to allocate memory for mac addr");
1502 goto unregister_irq;
1505 dev->max_mac_entries = max_entries;
1507 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
1509 goto free_mac_addrs;
1511 /* Update the mac address */
1512 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1514 /* Also sync same MAC address to CGX table */
1515 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
1517 /* Initialize the tm data structures */
1518 otx2_nix_tm_conf_init(eth_dev);
1520 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1521 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1523 if (otx2_dev_is_A0(dev)) {
1524 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
1525 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
1528 /* Initialize rte-flow */
1529 rc = otx2_flow_init(dev);
1531 goto free_mac_addrs;
1533 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
1534 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1535 eth_dev->data->port_id, dev->pf, dev->vf,
1536 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
1537 dev->rx_offload_capa, dev->tx_offload_capa);
1541 rte_free(eth_dev->data->mac_addrs);
1543 otx2_nix_unregister_irqs(eth_dev);
1545 otx2_eth_dev_lf_detach(dev->mbox);
1549 otx2_dev_fini(pci_dev, dev);
1551 otx2_err("Failed to init nix eth_dev rc=%d", rc);
1556 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
1558 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1559 struct rte_pci_device *pci_dev;
1562 /* Nothing to be done for secondary processes */
1563 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1566 /* Disable nix bpid config */
1567 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1569 /* Disable other rte_flow entries */
1570 otx2_flow_fini(dev);
1572 /* Disable PTP if already enabled */
1573 if (otx2_ethdev_is_ptp_en(dev))
1574 otx2_nix_timesync_disable(eth_dev);
1577 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1578 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
1579 eth_dev->data->tx_queues[i] = NULL;
1581 eth_dev->data->nb_tx_queues = 0;
1583 /* Free up RQ's and CQ's */
1584 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1585 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
1586 eth_dev->data->rx_queues[i] = NULL;
1588 eth_dev->data->nb_rx_queues = 0;
1590 /* Free tm resources */
1591 rc = otx2_nix_tm_fini(eth_dev);
1593 otx2_err("Failed to cleanup tm, rc=%d", rc);
1595 /* Unregister queue irqs */
1596 oxt2_nix_unregister_queue_irqs(eth_dev);
1598 rc = nix_lf_free(dev);
1600 otx2_err("Failed to free nix lf, rc=%d", rc);
1602 rc = otx2_npa_lf_fini();
1604 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
1606 rte_free(eth_dev->data->mac_addrs);
1607 eth_dev->data->mac_addrs = NULL;
1608 dev->drv_inited = false;
1610 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1611 otx2_nix_unregister_irqs(eth_dev);
1613 rc = otx2_eth_dev_lf_detach(dev->mbox);
1615 otx2_err("Failed to detach resources, rc=%d", rc);
1617 /* Check if mbox close is needed */
1621 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
1622 /* Will be freed later by PMD */
1623 eth_dev->data->dev_private = NULL;
1627 otx2_dev_fini(pci_dev, dev);
1632 nix_remove(struct rte_pci_device *pci_dev)
1634 struct rte_eth_dev *eth_dev;
1635 struct otx2_idev_cfg *idev;
1636 struct otx2_dev *otx2_dev;
1639 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1641 /* Cleanup eth dev */
1642 rc = otx2_eth_dev_uninit(eth_dev, true);
1646 rte_eth_dev_pci_release(eth_dev);
1649 /* Nothing to be done for secondary processes */
1650 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1653 /* Check for common resources */
1654 idev = otx2_intra_dev_get_cfg();
1655 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
1658 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
1660 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
1663 /* Safe to cleanup mbox as no more users */
1664 otx2_dev_fini(pci_dev, otx2_dev);
1669 otx2_info("%s: common resource in use by other devices", pci_dev->name);
1674 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1678 RTE_SET_USED(pci_drv);
1680 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
1683 /* On error on secondary, recheck if port exists in primary or
1684 * in mid of detach state.
1686 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1687 if (!rte_eth_dev_allocated(pci_dev->device.name))
1692 static const struct rte_pci_id pci_nix_map[] = {
1694 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
1697 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
1700 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1701 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
1708 static struct rte_pci_driver pci_nix = {
1709 .id_table = pci_nix_map,
1710 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA |
1711 RTE_PCI_DRV_INTR_LSC,
1713 .remove = nix_remove,
1716 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
1717 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
1718 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");