1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
8 #include <rte_ethdev_pci.h>
10 #include <rte_malloc.h>
12 #include <rte_mbuf_pool_ops.h>
13 #include <rte_mempool.h>
15 #include "otx2_ethdev.h"
17 static inline uint64_t
18 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
20 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
22 if (otx2_dev_is_vf(dev))
23 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
28 static inline uint64_t
29 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
33 return NIX_TX_OFFLOAD_CAPA;
36 static const struct otx2_dev_ops otx2_dev_ops = {
37 .link_status_update = otx2_eth_dev_link_status_update,
38 .ptp_info_update = otx2_eth_dev_ptp_info_update
42 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
44 struct otx2_mbox *mbox = dev->mbox;
45 struct nix_lf_alloc_req *req;
46 struct nix_lf_alloc_rsp *rsp;
49 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
53 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
54 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
55 req->xqe_sz = NIX_XQESZ_W16;
56 req->rss_sz = dev->rss_info.rss_size;
57 req->rss_grps = NIX_RSS_GRPS;
58 req->npa_func = otx2_npa_pf_func_get();
59 req->sso_func = otx2_sso_pf_func_get();
60 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
61 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
62 DEV_RX_OFFLOAD_UDP_CKSUM)) {
63 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
64 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
67 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
71 dev->sqb_size = rsp->sqb_size;
72 dev->tx_chan_base = rsp->tx_chan_base;
73 dev->rx_chan_base = rsp->rx_chan_base;
74 dev->rx_chan_cnt = rsp->rx_chan_cnt;
75 dev->tx_chan_cnt = rsp->tx_chan_cnt;
76 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
77 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
78 dev->lf_tx_stats = rsp->lf_tx_stats;
79 dev->lf_rx_stats = rsp->lf_rx_stats;
80 dev->cints = rsp->cints;
81 dev->qints = rsp->qints;
82 dev->npc_flow.channel = dev->rx_chan_base;
88 nix_lf_free(struct otx2_eth_dev *dev)
90 struct otx2_mbox *mbox = dev->mbox;
91 struct nix_lf_free_req *req;
92 struct ndc_sync_op *ndc_req;
95 /* Sync NDC-NIX for LF */
96 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
97 ndc_req->nix_lf_tx_sync = 1;
98 ndc_req->nix_lf_rx_sync = 1;
99 rc = otx2_mbox_process(mbox);
101 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
103 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
104 /* Let AF driver free all this nix lf's
105 * NPC entries allocated using NPC MBOX.
109 return otx2_mbox_process(mbox);
113 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
115 struct otx2_mbox *mbox = dev->mbox;
117 if (otx2_dev_is_vf(dev))
120 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
122 return otx2_mbox_process(mbox);
126 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
128 struct otx2_mbox *mbox = dev->mbox;
130 if (otx2_dev_is_vf(dev))
133 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
135 return otx2_mbox_process(mbox);
139 npc_rx_enable(struct otx2_eth_dev *dev)
141 struct otx2_mbox *mbox = dev->mbox;
143 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
145 return otx2_mbox_process(mbox);
149 npc_rx_disable(struct otx2_eth_dev *dev)
151 struct otx2_mbox *mbox = dev->mbox;
153 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
155 return otx2_mbox_process(mbox);
159 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
161 struct otx2_mbox *mbox = dev->mbox;
163 if (otx2_dev_is_vf(dev))
166 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
168 return otx2_mbox_process(mbox);
172 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
174 struct otx2_mbox *mbox = dev->mbox;
176 if (otx2_dev_is_vf(dev))
180 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
182 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
184 return otx2_mbox_process(mbox);
188 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
190 struct otx2_mbox *mbox = dev->mbox;
192 if (otx2_dev_is_vf(dev))
195 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
197 return otx2_mbox_process(mbox);
201 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
207 static inline uint32_t
208 nix_qsize_to_val(enum nix_q_size_e qsize)
210 return (16UL << (qsize * 2));
213 static inline enum nix_q_size_e
214 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
218 if (otx2_ethdev_fixup_is_min_4k_q(dev))
223 for (; i < nix_q_size_max; i++)
224 if (val <= nix_qsize_to_val(i))
227 if (i >= nix_q_size_max)
228 i = nix_q_size_max - 1;
234 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
235 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
237 struct otx2_mbox *mbox = dev->mbox;
238 const struct rte_memzone *rz;
239 uint32_t ring_size, cq_size;
240 struct nix_aq_enq_req *aq;
245 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
246 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
247 NIX_CQ_ALIGN, dev->node);
249 otx2_err("Failed to allocate mem for cq hw ring");
253 memset(rz->addr, 0, rz->len);
254 rxq->desc = (uintptr_t)rz->addr;
255 rxq->qmask = cq_size - 1;
257 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
259 aq->ctype = NIX_AQ_CTYPE_CQ;
260 aq->op = NIX_AQ_INSTOP_INIT;
264 aq->cq.qsize = rxq->qsize;
265 aq->cq.base = rz->iova;
266 aq->cq.avg_level = 0xff;
267 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
268 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
270 /* TX pause frames enable flowctrl on RX side */
271 if (dev->fc_info.tx_pause) {
272 /* Single bpid is allocated for all rx channels for now */
273 aq->cq.bpid = dev->fc_info.bpid[0];
274 aq->cq.bp = NIX_CQ_BP_LEVEL;
278 /* Many to one reduction */
279 aq->cq.qint_idx = qid % dev->qints;
281 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
282 uint16_t min_rx_drop;
283 const float rx_cq_skid = 1024 * 256;
285 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
286 aq->cq.drop = min_rx_drop;
290 rc = otx2_mbox_process(mbox);
292 otx2_err("Failed to init cq context");
296 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
298 aq->ctype = NIX_AQ_CTYPE_RQ;
299 aq->op = NIX_AQ_INSTOP_INIT;
302 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
304 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
305 first_skip = (sizeof(struct rte_mbuf));
306 first_skip += RTE_PKTMBUF_HEADROOM;
307 first_skip += rte_pktmbuf_priv_size(mp);
308 rxq->data_off = first_skip;
310 first_skip /= 8; /* Expressed in number of dwords */
311 aq->rq.first_skip = first_skip;
312 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
313 aq->rq.flow_tagw = 32; /* 32-bits */
314 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
315 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
316 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
317 aq->rq.lpb_sizem1 /= 8;
318 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
320 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
321 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
322 aq->rq.rq_int_ena = 0;
323 /* Many to one reduction */
324 aq->rq.qint_idx = qid % dev->qints;
326 if (otx2_ethdev_fixup_is_limit_cq_full(dev))
327 aq->rq.xqe_drop_ena = 1;
329 rc = otx2_mbox_process(mbox);
331 otx2_err("Failed to init rq context");
341 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
342 struct otx2_eth_rxq *rxq, const bool enb)
344 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
345 struct otx2_mbox *mbox = dev->mbox;
346 struct nix_aq_enq_req *aq;
348 /* Pkts will be dropped silently if RQ is disabled */
349 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
351 aq->ctype = NIX_AQ_CTYPE_RQ;
352 aq->op = NIX_AQ_INSTOP_WRITE;
355 aq->rq_mask.ena = ~(aq->rq_mask.ena);
357 return otx2_mbox_process(mbox);
361 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
363 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
364 struct otx2_mbox *mbox = dev->mbox;
365 struct nix_aq_enq_req *aq;
368 /* RQ is already disabled */
370 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
372 aq->ctype = NIX_AQ_CTYPE_CQ;
373 aq->op = NIX_AQ_INSTOP_WRITE;
376 aq->cq_mask.ena = ~(aq->cq_mask.ena);
378 rc = otx2_mbox_process(mbox);
380 otx2_err("Failed to disable cq context");
388 nix_get_data_off(struct otx2_eth_dev *dev)
390 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
394 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
396 struct rte_mbuf mb_def;
399 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
400 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
401 offsetof(struct rte_mbuf, data_off) != 2);
402 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
403 offsetof(struct rte_mbuf, data_off) != 4);
404 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
405 offsetof(struct rte_mbuf, data_off) != 6);
407 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
408 mb_def.port = port_id;
409 rte_mbuf_refcnt_set(&mb_def, 1);
411 /* Prevent compiler reordering: rearm_data covers previous fields */
412 rte_compiler_barrier();
413 tmp = (uint64_t *)&mb_def.rearm_data;
419 otx2_nix_rx_queue_release(void *rx_queue)
421 struct otx2_eth_rxq *rxq = rx_queue;
426 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
427 nix_cq_rq_uninit(rxq->eth_dev, rxq);
432 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
433 uint16_t nb_desc, unsigned int socket,
434 const struct rte_eth_rxconf *rx_conf,
435 struct rte_mempool *mp)
437 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
438 struct rte_mempool_ops *ops;
439 struct otx2_eth_rxq *rxq;
440 const char *platform_ops;
441 enum nix_q_size_e qsize;
447 /* Compile time check to make sure all fast path elements in a CL */
448 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
451 if (rx_conf->rx_deferred_start == 1) {
452 otx2_err("Deferred Rx start is not supported");
456 platform_ops = rte_mbuf_platform_mempool_ops();
457 /* This driver needs octeontx2_npa mempool ops to work */
458 ops = rte_mempool_get_ops(mp->ops_index);
459 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
460 otx2_err("mempool ops should be of octeontx2_npa type");
464 if (mp->pool_id == 0) {
465 otx2_err("Invalid pool_id");
469 /* Free memory prior to re-allocation if needed */
470 if (eth_dev->data->rx_queues[rq] != NULL) {
471 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
472 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
473 eth_dev->data->rx_queues[rq] = NULL;
476 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
477 dev->rx_offloads |= offloads;
479 /* Find the CQ queue size */
480 qsize = nix_qsize_clampup_get(dev, nb_desc);
481 /* Allocate rxq memory */
482 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
484 otx2_err("Failed to allocate rq=%d", rq);
489 rxq->eth_dev = eth_dev;
491 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
492 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
493 rxq->wdata = (uint64_t)rq << 32;
494 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
495 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
496 eth_dev->data->port_id);
497 rxq->offloads = offloads;
499 rxq->qlen = nix_qsize_to_val(qsize);
501 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
502 rxq->tstamp = &dev->tstamp;
504 /* Alloc completion queue */
505 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
507 otx2_err("Failed to allocate rxq=%u", rq);
511 rxq->qconf.socket_id = socket;
512 rxq->qconf.nb_desc = nb_desc;
513 rxq->qconf.mempool = mp;
514 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
516 nix_rx_queue_reset(rxq);
517 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
518 rq, mp->name, qsize, nb_desc, rxq->qlen);
520 eth_dev->data->rx_queues[rq] = rxq;
521 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
525 otx2_nix_rx_queue_release(rxq);
530 static inline uint8_t
531 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
534 * Maximum three segments can be supported with W8, Choose
535 * NIX_MAXSQESZ_W16 for multi segment offload.
537 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
538 return NIX_MAXSQESZ_W16;
540 return NIX_MAXSQESZ_W8;
544 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
546 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
547 struct rte_eth_dev_data *data = eth_dev->data;
548 struct rte_eth_conf *conf = &data->dev_conf;
549 struct rte_eth_rxmode *rxmode = &conf->rxmode;
552 if (rxmode->mq_mode == ETH_MQ_RX_RSS)
553 flags |= NIX_RX_OFFLOAD_RSS_F;
555 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
556 DEV_RX_OFFLOAD_UDP_CKSUM))
557 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
559 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
560 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
561 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
563 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
564 flags |= NIX_RX_MULTI_SEG_F;
566 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
567 DEV_RX_OFFLOAD_QINQ_STRIP))
568 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
570 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
571 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
577 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
579 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
580 uint64_t conf = dev->tx_offloads;
583 /* Fastpath is dependent on these enums */
584 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
585 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
586 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
588 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
589 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
590 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
592 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
593 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
594 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
596 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
597 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
598 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
599 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
600 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
602 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
603 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
605 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
606 flags |= NIX_TX_MULTI_SEG_F;
612 nix_sq_init(struct otx2_eth_txq *txq)
614 struct otx2_eth_dev *dev = txq->dev;
615 struct otx2_mbox *mbox = dev->mbox;
616 struct nix_aq_enq_req *sq;
621 if (txq->sqb_pool->pool_id == 0)
624 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
626 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
630 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
632 sq->ctype = NIX_AQ_CTYPE_SQ;
633 sq->op = NIX_AQ_INSTOP_INIT;
634 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
637 sq->sq.smq_rr_quantum = rr_quantum;
638 sq->sq.default_chan = dev->tx_chan_base;
639 sq->sq.sqe_stype = NIX_STYPE_STF;
641 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
642 sq->sq.sqe_stype = NIX_STYPE_STP;
644 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
645 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
646 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
647 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
648 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
650 /* Many to one reduction */
651 sq->sq.qint_idx = txq->sq % dev->qints;
653 return otx2_mbox_process(mbox);
657 nix_sq_uninit(struct otx2_eth_txq *txq)
659 struct otx2_eth_dev *dev = txq->dev;
660 struct otx2_mbox *mbox = dev->mbox;
661 struct ndc_sync_op *ndc_req;
662 struct nix_aq_enq_rsp *rsp;
663 struct nix_aq_enq_req *aq;
664 uint16_t sqes_per_sqb;
668 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
670 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
672 aq->ctype = NIX_AQ_CTYPE_SQ;
673 aq->op = NIX_AQ_INSTOP_READ;
675 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
679 /* Check if sq is already cleaned up */
684 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
686 aq->ctype = NIX_AQ_CTYPE_SQ;
687 aq->op = NIX_AQ_INSTOP_WRITE;
689 aq->sq_mask.ena = ~aq->sq_mask.ena;
692 rc = otx2_mbox_process(mbox);
696 /* Read SQ and free sqb's */
697 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
699 aq->ctype = NIX_AQ_CTYPE_SQ;
700 aq->op = NIX_AQ_INSTOP_READ;
702 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
707 otx2_err("SQ has pending sqe's");
709 count = aq->sq.sqb_count;
710 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
711 /* Free SQB's that are used */
712 sqb_buf = (void *)rsp->sq.head_sqb;
716 next_sqb = *(void **)((uintptr_t)sqb_buf + ((sqes_per_sqb - 1) *
717 nix_sq_max_sqe_sz(txq)));
718 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
724 /* Free next to use sqb */
725 if (rsp->sq.next_sqb)
726 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
729 /* Sync NDC-NIX-TX for LF */
730 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
731 ndc_req->nix_lf_tx_sync = 1;
732 rc = otx2_mbox_process(mbox);
734 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
740 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
742 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
743 struct npa_aq_enq_req *aura_req;
745 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
746 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
747 aura_req->ctype = NPA_AQ_CTYPE_AURA;
748 aura_req->op = NPA_AQ_INSTOP_WRITE;
750 aura_req->aura.limit = nb_sqb_bufs;
751 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
753 return otx2_mbox_process(npa_lf->mbox);
757 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
759 struct otx2_eth_dev *dev = txq->dev;
760 uint16_t sqes_per_sqb, nb_sqb_bufs;
761 char name[RTE_MEMPOOL_NAMESIZE];
762 struct rte_mempool_objsz sz;
763 struct npa_aura_s *aura;
764 uint32_t tmp, blk_sz;
766 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
767 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
768 blk_sz = dev->sqb_size;
770 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
771 sqes_per_sqb = (dev->sqb_size / 8) / 16;
773 sqes_per_sqb = (dev->sqb_size / 8) / 8;
775 nb_sqb_bufs = nb_desc / sqes_per_sqb;
776 /* Clamp up to devarg passed SQB count */
777 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_MIN_SQB,
778 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
780 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
782 MEMPOOL_F_NO_SPREAD);
783 txq->nb_sqb_bufs = nb_sqb_bufs;
784 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
785 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
786 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
787 txq->nb_sqb_bufs_adj =
788 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
790 if (txq->sqb_pool == NULL) {
791 otx2_err("Failed to allocate sqe mempool");
795 memset(aura, 0, sizeof(*aura));
797 aura->fc_addr = txq->fc_iova;
798 aura->fc_hyst_bits = 0; /* Store count on all updates */
799 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
800 otx2_err("Failed to set ops for sqe mempool");
803 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
804 otx2_err("Failed to populate sqe mempool");
808 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
809 if (dev->sqb_size != sz.elt_size) {
810 otx2_err("sqe pool block size is not expected %d != %d",
815 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
823 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
825 struct nix_send_ext_s *send_hdr_ext;
826 struct nix_send_hdr_s *send_hdr;
827 struct nix_send_mem_s *send_mem;
828 union nix_send_sg_s *sg;
830 /* Initialize the fields based on basic single segment packet */
831 memset(&txq->cmd, 0, sizeof(txq->cmd));
833 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
834 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
835 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
836 send_hdr->w0.sizem1 = 2;
838 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
839 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
840 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
841 /* Default: one seg packet would have:
842 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
845 send_hdr->w0.sizem1 = 3;
846 send_hdr_ext->w0.tstmp = 1;
848 /* To calculate the offset for send_mem,
849 * send_hdr->w0.sizem1 * 2
851 send_mem = (struct nix_send_mem_s *)(txq->cmd +
852 (send_hdr->w0.sizem1 << 1));
853 send_mem->subdc = NIX_SUBDC_MEM;
855 send_mem->wmem = 0x1;
856 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
857 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
859 sg = (union nix_send_sg_s *)&txq->cmd[4];
861 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
862 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
863 send_hdr->w0.sizem1 = 1;
864 sg = (union nix_send_sg_s *)&txq->cmd[2];
867 send_hdr->w0.sq = txq->sq;
868 sg->subdc = NIX_SUBDC_SG;
870 sg->ld_type = NIX_SENDLDTYPE_LDD;
876 otx2_nix_tx_queue_release(void *_txq)
878 struct otx2_eth_txq *txq = _txq;
879 struct rte_eth_dev *eth_dev;
884 eth_dev = txq->dev->eth_dev;
886 otx2_nix_dbg("Releasing txq %u", txq->sq);
888 /* Flush and disable tm */
889 otx2_nix_tm_sw_xoff(txq, eth_dev->data->dev_started);
891 /* Free sqb's and disable sq */
895 rte_mempool_free(txq->sqb_pool);
896 txq->sqb_pool = NULL;
903 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
904 uint16_t nb_desc, unsigned int socket_id,
905 const struct rte_eth_txconf *tx_conf)
907 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
908 const struct rte_memzone *fc;
909 struct otx2_eth_txq *txq;
915 /* Compile time check to make sure all fast path elements in a CL */
916 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
918 if (tx_conf->tx_deferred_start) {
919 otx2_err("Tx deferred start is not supported");
923 /* Free memory prior to re-allocation if needed. */
924 if (eth_dev->data->tx_queues[sq] != NULL) {
925 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
926 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
927 eth_dev->data->tx_queues[sq] = NULL;
930 /* Find the expected offloads for this queue */
931 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
933 /* Allocating tx queue data structure */
934 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
935 OTX2_ALIGN, socket_id);
937 otx2_err("Failed to alloc txq=%d", sq);
943 txq->sqb_pool = NULL;
944 txq->offloads = offloads;
945 dev->tx_offloads |= offloads;
948 * Allocate memory for flow control updates from HW.
949 * Alloc one cache line, so that fits all FC_STYPE modes.
951 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
952 OTX2_ALIGN + sizeof(struct npa_aura_s),
953 OTX2_ALIGN, dev->node);
955 otx2_err("Failed to allocate mem for fcmem");
959 txq->fc_iova = fc->iova;
960 txq->fc_mem = fc->addr;
962 /* Initialize the aura sqb pool */
963 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
965 otx2_err("Failed to alloc sqe pool rc=%d", rc);
969 /* Initialize the SQ */
970 rc = nix_sq_init(txq);
972 otx2_err("Failed to init sq=%d context", sq);
976 txq->fc_cache_pkts = 0;
977 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
978 /* Evenly distribute LMT slot for each sq */
979 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
981 txq->qconf.socket_id = socket_id;
982 txq->qconf.nb_desc = nb_desc;
983 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
985 otx2_nix_form_default_desc(txq);
987 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
988 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
989 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
990 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
991 eth_dev->data->tx_queues[sq] = txq;
992 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
996 otx2_nix_tx_queue_release(txq);
1002 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1004 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1005 struct otx2_eth_qconf *tx_qconf = NULL;
1006 struct otx2_eth_qconf *rx_qconf = NULL;
1007 struct otx2_eth_txq **txq;
1008 struct otx2_eth_rxq **rxq;
1009 int i, nb_rxq, nb_txq;
1011 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1012 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1014 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1015 if (tx_qconf == NULL) {
1016 otx2_err("Failed to allocate memory for tx_qconf");
1020 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1021 if (rx_qconf == NULL) {
1022 otx2_err("Failed to allocate memory for rx_qconf");
1026 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1027 for (i = 0; i < nb_txq; i++) {
1028 if (txq[i] == NULL) {
1029 otx2_err("txq[%d] is already released", i);
1032 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1033 otx2_nix_tx_queue_release(txq[i]);
1034 eth_dev->data->tx_queues[i] = NULL;
1037 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1038 for (i = 0; i < nb_rxq; i++) {
1039 if (rxq[i] == NULL) {
1040 otx2_err("rxq[%d] is already released", i);
1043 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1044 otx2_nix_rx_queue_release(rxq[i]);
1045 eth_dev->data->rx_queues[i] = NULL;
1048 dev->tx_qconf = tx_qconf;
1049 dev->rx_qconf = rx_qconf;
1062 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1064 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1065 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1066 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1067 struct otx2_eth_txq **txq;
1068 struct otx2_eth_rxq **rxq;
1069 int rc, i, nb_rxq, nb_txq;
1071 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1072 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1075 /* Setup tx & rx queues with previous configuration so
1076 * that the queues can be functional in cases like ports
1077 * are started without re configuring queues.
1079 * Usual re config sequence is like below:
1080 * port_configure() {
1085 * queue_configure() {
1092 * In some application's control path, queue_configure() would
1093 * NOT be invoked for TXQs/RXQs in port_configure().
1094 * In such cases, queues can be functional after start as the
1095 * queues are already setup in port_configure().
1097 for (i = 0; i < nb_txq; i++) {
1098 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1099 tx_qconf[i].socket_id,
1100 &tx_qconf[i].conf.tx);
1102 otx2_err("Failed to setup tx queue rc=%d", rc);
1103 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1104 for (i -= 1; i >= 0; i--)
1105 otx2_nix_tx_queue_release(txq[i]);
1110 free(tx_qconf); tx_qconf = NULL;
1112 for (i = 0; i < nb_rxq; i++) {
1113 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1114 rx_qconf[i].socket_id,
1115 &rx_qconf[i].conf.rx,
1116 rx_qconf[i].mempool);
1118 otx2_err("Failed to setup rx queue rc=%d", rc);
1119 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1120 for (i -= 1; i >= 0; i--)
1121 otx2_nix_rx_queue_release(rxq[i]);
1122 goto release_tx_queues;
1126 free(rx_qconf); rx_qconf = NULL;
1131 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1132 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1133 otx2_nix_tx_queue_release(txq[i]);
1144 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1146 RTE_SET_USED(queue);
1147 RTE_SET_USED(mbufs);
1154 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1156 /* These dummy functions are required for supporting
1157 * some applications which reconfigure queues without
1158 * stopping tx burst and rx burst threads(eg kni app)
1159 * When the queues context is saved, txq/rxqs are released
1160 * which caused app crash since rx/tx burst is still
1161 * on different lcores
1163 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1164 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1169 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1171 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1172 struct rte_eth_dev_data *data = eth_dev->data;
1173 struct rte_eth_conf *conf = &data->dev_conf;
1174 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1175 struct rte_eth_txmode *txmode = &conf->txmode;
1176 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1177 struct rte_ether_addr *ea;
1178 uint8_t nb_rxq, nb_txq;
1184 if (rte_eal_has_hugepages() == 0) {
1185 otx2_err("Huge page is not configured");
1189 if (rte_eal_iova_mode() != RTE_IOVA_VA) {
1190 otx2_err("iova mode should be va");
1194 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1195 otx2_err("Setting link speed/duplex not supported");
1199 if (conf->dcb_capability_en == 1) {
1200 otx2_err("dcb enable is not supported");
1204 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1205 otx2_err("Flow director is not supported");
1209 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1210 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1211 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1215 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1216 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1220 /* Free the resources allocated from the previous configure */
1221 if (dev->configured == 1) {
1222 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1223 otx2_nix_vlan_fini(eth_dev);
1224 otx2_flow_free_all_resources(dev);
1225 oxt2_nix_unregister_queue_irqs(eth_dev);
1226 nix_set_nop_rxtx_function(eth_dev);
1227 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1230 otx2_nix_tm_fini(eth_dev);
1234 if (otx2_dev_is_A0(dev) &&
1235 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1236 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1237 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1238 otx2_err("Outer IP and SCTP checksum unsupported");
1243 dev->rx_offloads = rxmode->offloads;
1244 dev->tx_offloads = txmode->offloads;
1245 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1246 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1247 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1249 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1250 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1252 /* Alloc a nix lf */
1253 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1255 otx2_err("Failed to init nix_lf rc=%d", rc);
1260 rc = otx2_nix_rss_config(eth_dev);
1262 otx2_err("Failed to configure rss rc=%d", rc);
1266 /* Init the default TM scheduler hierarchy */
1267 rc = otx2_nix_tm_init_default(eth_dev);
1269 otx2_err("Failed to init traffic manager rc=%d", rc);
1273 rc = otx2_nix_vlan_offload_init(eth_dev);
1275 otx2_err("Failed to init vlan offload rc=%d", rc);
1279 /* Register queue IRQs */
1280 rc = oxt2_nix_register_queue_irqs(eth_dev);
1282 otx2_err("Failed to register queue interrupts rc=%d", rc);
1286 /* Configure loop back mode */
1287 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1289 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1293 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1295 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1299 /* Enable PTP if it was requested by the app or if it is already
1300 * enabled in PF owning this VF
1302 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
1303 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
1304 otx2_ethdev_is_ptp_en(dev))
1305 otx2_nix_timesync_enable(eth_dev);
1307 otx2_nix_timesync_disable(eth_dev);
1310 * Restore queue config when reconfigure followed by
1311 * reconfigure and no queue configure invoked from application case.
1313 if (dev->configured == 1) {
1314 rc = nix_restore_queue_cfg(eth_dev);
1319 /* Update the mac address */
1320 ea = eth_dev->data->mac_addrs;
1321 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1322 if (rte_is_zero_ether_addr(ea))
1323 rte_eth_random_addr((uint8_t *)ea);
1325 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1327 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1328 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1329 " rx_flags=0x%x tx_flags=0x%x",
1330 eth_dev->data->port_id, ea_fmt, nb_rxq,
1331 nb_txq, dev->rx_offloads, dev->tx_offloads,
1332 dev->rx_offload_flags, dev->tx_offload_flags);
1335 dev->configured = 1;
1336 dev->configured_nb_rx_qs = data->nb_rx_queues;
1337 dev->configured_nb_tx_qs = data->nb_tx_queues;
1341 rc = nix_lf_free(dev);
1347 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1349 struct rte_eth_dev_data *data = eth_dev->data;
1350 struct otx2_eth_txq *txq;
1353 txq = eth_dev->data->tx_queues[qidx];
1355 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1358 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1360 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1365 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1372 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1374 struct rte_eth_dev_data *data = eth_dev->data;
1375 struct otx2_eth_txq *txq;
1378 txq = eth_dev->data->tx_queues[qidx];
1380 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1383 txq->fc_cache_pkts = 0;
1385 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1387 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1392 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1399 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1401 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1402 struct rte_eth_dev_data *data = eth_dev->data;
1405 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1408 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1410 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1414 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1421 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1423 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1424 struct rte_eth_dev_data *data = eth_dev->data;
1427 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1430 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1432 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1436 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1443 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
1445 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1446 struct rte_mbuf *rx_pkts[32];
1447 struct otx2_eth_rxq *rxq;
1448 int count, i, j, rc;
1450 nix_cgx_stop_link_event(dev);
1451 npc_rx_disable(dev);
1453 /* Stop rx queues and free up pkts pending */
1454 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1455 rc = otx2_nix_rx_queue_stop(eth_dev, i);
1459 rxq = eth_dev->data->rx_queues[i];
1460 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1462 for (j = 0; j < count; j++)
1463 rte_pktmbuf_free(rx_pkts[j]);
1464 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1468 /* Stop tx queues */
1469 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1470 otx2_nix_tx_queue_stop(eth_dev, i);
1474 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
1476 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1479 if (eth_dev->data->nb_rx_queues != 0) {
1480 rc = otx2_nix_recalc_mtu(eth_dev);
1485 /* Start rx queues */
1486 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1487 rc = otx2_nix_rx_queue_start(eth_dev, i);
1492 /* Start tx queues */
1493 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1494 rc = otx2_nix_tx_queue_start(eth_dev, i);
1499 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
1501 otx2_err("Failed to update flow ctrl mode %d", rc);
1505 rc = npc_rx_enable(dev);
1507 otx2_err("Failed to enable NPC rx %d", rc);
1511 otx2_nix_toggle_flag_link_cfg(dev, true);
1513 rc = nix_cgx_start_link_event(dev);
1515 otx2_err("Failed to start cgx link event %d", rc);
1519 otx2_nix_toggle_flag_link_cfg(dev, false);
1520 otx2_eth_set_tx_function(eth_dev);
1521 otx2_eth_set_rx_function(eth_dev);
1526 npc_rx_disable(dev);
1527 otx2_nix_toggle_flag_link_cfg(dev, false);
1531 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
1532 static void otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
1534 /* Initialize and register driver with DPDK Application */
1535 static const struct eth_dev_ops otx2_eth_dev_ops = {
1536 .dev_infos_get = otx2_nix_info_get,
1537 .dev_configure = otx2_nix_configure,
1538 .link_update = otx2_nix_link_update,
1539 .tx_queue_setup = otx2_nix_tx_queue_setup,
1540 .tx_queue_release = otx2_nix_tx_queue_release,
1541 .rx_queue_setup = otx2_nix_rx_queue_setup,
1542 .rx_queue_release = otx2_nix_rx_queue_release,
1543 .dev_start = otx2_nix_dev_start,
1544 .dev_stop = otx2_nix_dev_stop,
1545 .dev_close = otx2_nix_dev_close,
1546 .tx_queue_start = otx2_nix_tx_queue_start,
1547 .tx_queue_stop = otx2_nix_tx_queue_stop,
1548 .rx_queue_start = otx2_nix_rx_queue_start,
1549 .rx_queue_stop = otx2_nix_rx_queue_stop,
1550 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
1551 .dev_reset = otx2_nix_dev_reset,
1552 .stats_get = otx2_nix_dev_stats_get,
1553 .stats_reset = otx2_nix_dev_stats_reset,
1554 .get_reg = otx2_nix_dev_get_reg,
1555 .mtu_set = otx2_nix_mtu_set,
1556 .mac_addr_add = otx2_nix_mac_addr_add,
1557 .mac_addr_remove = otx2_nix_mac_addr_del,
1558 .mac_addr_set = otx2_nix_mac_addr_set,
1559 .promiscuous_enable = otx2_nix_promisc_enable,
1560 .promiscuous_disable = otx2_nix_promisc_disable,
1561 .allmulticast_enable = otx2_nix_allmulticast_enable,
1562 .allmulticast_disable = otx2_nix_allmulticast_disable,
1563 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
1564 .reta_update = otx2_nix_dev_reta_update,
1565 .reta_query = otx2_nix_dev_reta_query,
1566 .rss_hash_update = otx2_nix_rss_hash_update,
1567 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
1568 .xstats_get = otx2_nix_xstats_get,
1569 .xstats_get_names = otx2_nix_xstats_get_names,
1570 .xstats_reset = otx2_nix_xstats_reset,
1571 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
1572 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
1573 .rxq_info_get = otx2_nix_rxq_info_get,
1574 .txq_info_get = otx2_nix_txq_info_get,
1575 .rx_queue_count = otx2_nix_rx_queue_count,
1576 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
1577 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
1578 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
1579 .pool_ops_supported = otx2_nix_pool_ops_supported,
1580 .filter_ctrl = otx2_nix_dev_filter_ctrl,
1581 .get_module_info = otx2_nix_get_module_info,
1582 .get_module_eeprom = otx2_nix_get_module_eeprom,
1583 .fw_version_get = otx2_nix_fw_version_get,
1584 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
1585 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
1586 .timesync_enable = otx2_nix_timesync_enable,
1587 .timesync_disable = otx2_nix_timesync_disable,
1588 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
1589 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
1590 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
1591 .timesync_read_time = otx2_nix_timesync_read_time,
1592 .timesync_write_time = otx2_nix_timesync_write_time,
1593 .vlan_offload_set = otx2_nix_vlan_offload_set,
1594 .vlan_filter_set = otx2_nix_vlan_filter_set,
1595 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
1596 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
1597 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
1601 nix_lf_attach(struct otx2_eth_dev *dev)
1603 struct otx2_mbox *mbox = dev->mbox;
1604 struct rsrc_attach_req *req;
1606 /* Attach NIX(lf) */
1607 req = otx2_mbox_alloc_msg_attach_resources(mbox);
1611 return otx2_mbox_process(mbox);
1615 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
1617 struct otx2_mbox *mbox = dev->mbox;
1618 struct msix_offset_rsp *msix_rsp;
1621 /* Get NPA and NIX MSIX vector offsets */
1622 otx2_mbox_alloc_msg_msix_offset(mbox);
1624 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
1626 dev->nix_msixoff = msix_rsp->nix_msixoff;
1632 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
1634 struct rsrc_detach_req *req;
1636 req = otx2_mbox_alloc_msg_detach_resources(mbox);
1638 /* Detach all except npa lf */
1639 req->partial = true;
1646 return otx2_mbox_process(mbox);
1650 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
1652 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1653 struct rte_pci_device *pci_dev;
1654 int rc, max_entries;
1656 eth_dev->dev_ops = &otx2_eth_dev_ops;
1658 /* For secondary processes, the primary has done all the work */
1659 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1660 /* Setup callbacks for secondary process */
1661 otx2_eth_set_tx_function(eth_dev);
1662 otx2_eth_set_rx_function(eth_dev);
1666 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1668 rte_eth_copy_pci_info(eth_dev, pci_dev);
1669 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1671 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
1672 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
1673 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
1675 /* Parse devargs string */
1676 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1678 otx2_err("Failed to parse devargs rc=%d", rc);
1682 if (!dev->mbox_active) {
1683 /* Initialize the base otx2_dev object
1684 * only if already present
1686 rc = otx2_dev_init(pci_dev, dev);
1688 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1692 /* Device generic callbacks */
1693 dev->ops = &otx2_dev_ops;
1694 dev->eth_dev = eth_dev;
1696 /* Grab the NPA LF if required */
1697 rc = otx2_npa_lf_init(pci_dev, dev);
1699 goto otx2_dev_uninit;
1701 dev->configured = 0;
1702 dev->drv_inited = true;
1703 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
1704 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
1707 rc = nix_lf_attach(dev);
1709 goto otx2_npa_uninit;
1711 /* Get NIX MSIX offset */
1712 rc = nix_lf_get_msix_offset(dev);
1714 goto otx2_npa_uninit;
1716 /* Register LF irq handlers */
1717 rc = otx2_nix_register_irqs(eth_dev);
1721 /* Get maximum number of supported MAC entries */
1722 max_entries = otx2_cgx_mac_max_entries_get(dev);
1723 if (max_entries < 0) {
1724 otx2_err("Failed to get max entries for mac addr");
1726 goto unregister_irq;
1729 /* For VFs, returned max_entries will be 0. But to keep default MAC
1730 * address, one entry must be allocated. So setting up to 1.
1732 if (max_entries == 0)
1735 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
1736 RTE_ETHER_ADDR_LEN, 0);
1737 if (eth_dev->data->mac_addrs == NULL) {
1738 otx2_err("Failed to allocate memory for mac addr");
1740 goto unregister_irq;
1743 dev->max_mac_entries = max_entries;
1745 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
1747 goto free_mac_addrs;
1749 /* Update the mac address */
1750 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1752 /* Also sync same MAC address to CGX table */
1753 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
1755 /* Initialize the tm data structures */
1756 otx2_nix_tm_conf_init(eth_dev);
1758 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1759 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1761 if (otx2_dev_is_A0(dev)) {
1762 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
1763 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
1766 /* Initialize rte-flow */
1767 rc = otx2_flow_init(dev);
1769 goto free_mac_addrs;
1771 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
1772 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1773 eth_dev->data->port_id, dev->pf, dev->vf,
1774 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
1775 dev->rx_offload_capa, dev->tx_offload_capa);
1779 rte_free(eth_dev->data->mac_addrs);
1781 otx2_nix_unregister_irqs(eth_dev);
1783 otx2_eth_dev_lf_detach(dev->mbox);
1787 otx2_dev_fini(pci_dev, dev);
1789 otx2_err("Failed to init nix eth_dev rc=%d", rc);
1794 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
1796 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1797 struct rte_pci_device *pci_dev;
1800 /* Nothing to be done for secondary processes */
1801 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1804 /* Clear the flag since we are closing down */
1805 dev->configured = 0;
1807 /* Disable nix bpid config */
1808 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1810 npc_rx_disable(dev);
1812 /* Disable vlan offloads */
1813 otx2_nix_vlan_fini(eth_dev);
1815 /* Disable other rte_flow entries */
1816 otx2_flow_fini(dev);
1818 /* Disable PTP if already enabled */
1819 if (otx2_ethdev_is_ptp_en(dev))
1820 otx2_nix_timesync_disable(eth_dev);
1822 nix_cgx_stop_link_event(dev);
1825 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1826 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
1827 eth_dev->data->tx_queues[i] = NULL;
1829 eth_dev->data->nb_tx_queues = 0;
1831 /* Free up RQ's and CQ's */
1832 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1833 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
1834 eth_dev->data->rx_queues[i] = NULL;
1836 eth_dev->data->nb_rx_queues = 0;
1838 /* Free tm resources */
1839 rc = otx2_nix_tm_fini(eth_dev);
1841 otx2_err("Failed to cleanup tm, rc=%d", rc);
1843 /* Unregister queue irqs */
1844 oxt2_nix_unregister_queue_irqs(eth_dev);
1846 rc = nix_lf_free(dev);
1848 otx2_err("Failed to free nix lf, rc=%d", rc);
1850 rc = otx2_npa_lf_fini();
1852 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
1854 rte_free(eth_dev->data->mac_addrs);
1855 eth_dev->data->mac_addrs = NULL;
1856 dev->drv_inited = false;
1858 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1859 otx2_nix_unregister_irqs(eth_dev);
1861 rc = otx2_eth_dev_lf_detach(dev->mbox);
1863 otx2_err("Failed to detach resources, rc=%d", rc);
1865 /* Check if mbox close is needed */
1869 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
1870 /* Will be freed later by PMD */
1871 eth_dev->data->dev_private = NULL;
1875 otx2_dev_fini(pci_dev, dev);
1880 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
1882 otx2_eth_dev_uninit(eth_dev, true);
1886 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
1890 rc = otx2_eth_dev_uninit(eth_dev, false);
1894 return otx2_eth_dev_init(eth_dev);
1898 nix_remove(struct rte_pci_device *pci_dev)
1900 struct rte_eth_dev *eth_dev;
1901 struct otx2_idev_cfg *idev;
1902 struct otx2_dev *otx2_dev;
1905 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1907 /* Cleanup eth dev */
1908 rc = otx2_eth_dev_uninit(eth_dev, true);
1912 rte_eth_dev_pci_release(eth_dev);
1915 /* Nothing to be done for secondary processes */
1916 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1919 /* Check for common resources */
1920 idev = otx2_intra_dev_get_cfg();
1921 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
1924 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
1926 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
1929 /* Safe to cleanup mbox as no more users */
1930 otx2_dev_fini(pci_dev, otx2_dev);
1935 otx2_info("%s: common resource in use by other devices", pci_dev->name);
1940 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1944 RTE_SET_USED(pci_drv);
1946 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
1949 /* On error on secondary, recheck if port exists in primary or
1950 * in mid of detach state.
1952 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1953 if (!rte_eth_dev_allocated(pci_dev->device.name))
1958 static const struct rte_pci_id pci_nix_map[] = {
1960 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
1963 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
1966 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
1967 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
1974 static struct rte_pci_driver pci_nix = {
1975 .id_table = pci_nix_map,
1976 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA |
1977 RTE_PCI_DRV_INTR_LSC,
1979 .remove = nix_remove,
1982 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
1983 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
1984 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");