1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_ethdev_pci.h>
9 #include <rte_malloc.h>
11 #include <rte_mbuf_pool_ops.h>
12 #include <rte_mempool.h>
14 #include "otx2_ethdev.h"
16 static inline uint64_t
17 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
19 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
21 if (otx2_dev_is_vf(dev))
22 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
27 static inline uint64_t
28 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
30 uint64_t capa = NIX_TX_OFFLOAD_CAPA;
32 /* TSO not supported for earlier chip revisions */
33 if (otx2_dev_is_96xx_A0(dev) || otx2_dev_is_95xx_Ax(dev))
34 capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
35 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
36 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
37 DEV_TX_OFFLOAD_GRE_TNL_TSO);
41 static const struct otx2_dev_ops otx2_dev_ops = {
42 .link_status_update = otx2_eth_dev_link_status_update,
43 .ptp_info_update = otx2_eth_dev_ptp_info_update
47 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
49 struct otx2_mbox *mbox = dev->mbox;
50 struct nix_lf_alloc_req *req;
51 struct nix_lf_alloc_rsp *rsp;
54 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
58 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
59 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
60 req->xqe_sz = NIX_XQESZ_W16;
61 req->rss_sz = dev->rss_info.rss_size;
62 req->rss_grps = NIX_RSS_GRPS;
63 req->npa_func = otx2_npa_pf_func_get();
64 req->sso_func = otx2_sso_pf_func_get();
65 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
66 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
67 DEV_RX_OFFLOAD_UDP_CKSUM)) {
68 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
69 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
71 req->rx_cfg |= BIT_ULL(32 /* DROP_RE */);
73 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
77 dev->sqb_size = rsp->sqb_size;
78 dev->tx_chan_base = rsp->tx_chan_base;
79 dev->rx_chan_base = rsp->rx_chan_base;
80 dev->rx_chan_cnt = rsp->rx_chan_cnt;
81 dev->tx_chan_cnt = rsp->tx_chan_cnt;
82 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
83 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
84 dev->lf_tx_stats = rsp->lf_tx_stats;
85 dev->lf_rx_stats = rsp->lf_rx_stats;
86 dev->cints = rsp->cints;
87 dev->qints = rsp->qints;
88 dev->npc_flow.channel = dev->rx_chan_base;
94 nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev)
96 struct otx2_mbox *mbox = dev->mbox;
97 struct npc_set_pkind *req;
101 if (dev->npc_flow.switch_header_type == 0)
104 /* Notify AF about higig2 config */
105 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
106 req->mode = dev->npc_flow.switch_header_type;
108 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
111 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
112 req->mode = dev->npc_flow.switch_header_type;
114 return otx2_mbox_process_msg(mbox, (void *)&rsp);
118 nix_lf_free(struct otx2_eth_dev *dev)
120 struct otx2_mbox *mbox = dev->mbox;
121 struct nix_lf_free_req *req;
122 struct ndc_sync_op *ndc_req;
125 /* Sync NDC-NIX for LF */
126 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
127 ndc_req->nix_lf_tx_sync = 1;
128 ndc_req->nix_lf_rx_sync = 1;
129 rc = otx2_mbox_process(mbox);
131 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
133 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
134 /* Let AF driver free all this nix lf's
135 * NPC entries allocated using NPC MBOX.
139 return otx2_mbox_process(mbox);
143 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
145 struct otx2_mbox *mbox = dev->mbox;
147 if (otx2_dev_is_vf_or_sdp(dev))
150 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
152 return otx2_mbox_process(mbox);
156 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
158 struct otx2_mbox *mbox = dev->mbox;
160 if (otx2_dev_is_vf_or_sdp(dev))
163 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
165 return otx2_mbox_process(mbox);
169 npc_rx_enable(struct otx2_eth_dev *dev)
171 struct otx2_mbox *mbox = dev->mbox;
173 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
175 return otx2_mbox_process(mbox);
179 npc_rx_disable(struct otx2_eth_dev *dev)
181 struct otx2_mbox *mbox = dev->mbox;
183 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
185 return otx2_mbox_process(mbox);
189 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
191 struct otx2_mbox *mbox = dev->mbox;
193 if (otx2_dev_is_vf_or_sdp(dev))
196 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
198 return otx2_mbox_process(mbox);
202 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
204 struct otx2_mbox *mbox = dev->mbox;
206 if (otx2_dev_is_vf_or_sdp(dev))
210 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
212 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
214 return otx2_mbox_process(mbox);
218 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
220 struct otx2_mbox *mbox = dev->mbox;
222 if (otx2_dev_is_vf_or_sdp(dev))
225 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
227 return otx2_mbox_process(mbox);
231 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
237 static inline uint32_t
238 nix_qsize_to_val(enum nix_q_size_e qsize)
240 return (16UL << (qsize * 2));
243 static inline enum nix_q_size_e
244 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
248 if (otx2_ethdev_fixup_is_min_4k_q(dev))
253 for (; i < nix_q_size_max; i++)
254 if (val <= nix_qsize_to_val(i))
257 if (i >= nix_q_size_max)
258 i = nix_q_size_max - 1;
264 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
265 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
267 struct otx2_mbox *mbox = dev->mbox;
268 const struct rte_memzone *rz;
269 uint32_t ring_size, cq_size;
270 struct nix_aq_enq_req *aq;
275 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
276 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
277 NIX_CQ_ALIGN, dev->node);
279 otx2_err("Failed to allocate mem for cq hw ring");
283 memset(rz->addr, 0, rz->len);
284 rxq->desc = (uintptr_t)rz->addr;
285 rxq->qmask = cq_size - 1;
287 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
289 aq->ctype = NIX_AQ_CTYPE_CQ;
290 aq->op = NIX_AQ_INSTOP_INIT;
294 aq->cq.qsize = rxq->qsize;
295 aq->cq.base = rz->iova;
296 aq->cq.avg_level = 0xff;
297 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
298 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
300 /* Many to one reduction */
301 aq->cq.qint_idx = qid % dev->qints;
302 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
303 aq->cq.cint_idx = qid;
305 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
306 const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
307 uint16_t min_rx_drop;
309 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
310 aq->cq.drop = min_rx_drop;
312 rxq->cq_drop = min_rx_drop;
314 rxq->cq_drop = NIX_CQ_THRESH_LEVEL;
315 aq->cq.drop = rxq->cq_drop;
319 /* TX pause frames enable flowctrl on RX side */
320 if (dev->fc_info.tx_pause) {
321 /* Single bpid is allocated for all rx channels for now */
322 aq->cq.bpid = dev->fc_info.bpid[0];
323 aq->cq.bp = rxq->cq_drop;
327 rc = otx2_mbox_process(mbox);
329 otx2_err("Failed to init cq context");
333 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
335 aq->ctype = NIX_AQ_CTYPE_RQ;
336 aq->op = NIX_AQ_INSTOP_INIT;
339 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
341 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
342 first_skip = (sizeof(struct rte_mbuf));
343 first_skip += RTE_PKTMBUF_HEADROOM;
344 first_skip += rte_pktmbuf_priv_size(mp);
345 rxq->data_off = first_skip;
347 first_skip /= 8; /* Expressed in number of dwords */
348 aq->rq.first_skip = first_skip;
349 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
350 aq->rq.flow_tagw = 32; /* 32-bits */
351 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
352 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
353 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
354 aq->rq.lpb_sizem1 /= 8;
355 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
357 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
358 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
359 aq->rq.rq_int_ena = 0;
360 /* Many to one reduction */
361 aq->rq.qint_idx = qid % dev->qints;
363 aq->rq.xqe_drop_ena = 1;
365 rc = otx2_mbox_process(mbox);
367 otx2_err("Failed to init rq context");
377 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
378 struct otx2_eth_rxq *rxq, const bool enb)
380 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
381 struct otx2_mbox *mbox = dev->mbox;
382 struct nix_aq_enq_req *aq;
384 /* Pkts will be dropped silently if RQ is disabled */
385 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
387 aq->ctype = NIX_AQ_CTYPE_RQ;
388 aq->op = NIX_AQ_INSTOP_WRITE;
391 aq->rq_mask.ena = ~(aq->rq_mask.ena);
393 return otx2_mbox_process(mbox);
397 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
399 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
400 struct otx2_mbox *mbox = dev->mbox;
401 struct nix_aq_enq_req *aq;
404 /* RQ is already disabled */
406 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
408 aq->ctype = NIX_AQ_CTYPE_CQ;
409 aq->op = NIX_AQ_INSTOP_WRITE;
412 aq->cq_mask.ena = ~(aq->cq_mask.ena);
414 rc = otx2_mbox_process(mbox);
416 otx2_err("Failed to disable cq context");
424 nix_get_data_off(struct otx2_eth_dev *dev)
426 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
430 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
432 struct rte_mbuf mb_def;
435 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
436 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
437 offsetof(struct rte_mbuf, data_off) != 2);
438 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
439 offsetof(struct rte_mbuf, data_off) != 4);
440 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
441 offsetof(struct rte_mbuf, data_off) != 6);
443 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
444 mb_def.port = port_id;
445 rte_mbuf_refcnt_set(&mb_def, 1);
447 /* Prevent compiler reordering: rearm_data covers previous fields */
448 rte_compiler_barrier();
449 tmp = (uint64_t *)&mb_def.rearm_data;
455 otx2_nix_rx_queue_release(void *rx_queue)
457 struct otx2_eth_rxq *rxq = rx_queue;
462 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
463 nix_cq_rq_uninit(rxq->eth_dev, rxq);
468 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
469 uint16_t nb_desc, unsigned int socket,
470 const struct rte_eth_rxconf *rx_conf,
471 struct rte_mempool *mp)
473 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
474 struct rte_mempool_ops *ops;
475 struct otx2_eth_rxq *rxq;
476 const char *platform_ops;
477 enum nix_q_size_e qsize;
483 /* Compile time check to make sure all fast path elements in a CL */
484 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
487 if (rx_conf->rx_deferred_start == 1) {
488 otx2_err("Deferred Rx start is not supported");
492 platform_ops = rte_mbuf_platform_mempool_ops();
493 /* This driver needs octeontx2_npa mempool ops to work */
494 ops = rte_mempool_get_ops(mp->ops_index);
495 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
496 otx2_err("mempool ops should be of octeontx2_npa type");
500 if (mp->pool_id == 0) {
501 otx2_err("Invalid pool_id");
505 /* Free memory prior to re-allocation if needed */
506 if (eth_dev->data->rx_queues[rq] != NULL) {
507 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
508 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
509 eth_dev->data->rx_queues[rq] = NULL;
512 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
513 dev->rx_offloads |= offloads;
515 /* Find the CQ queue size */
516 qsize = nix_qsize_clampup_get(dev, nb_desc);
517 /* Allocate rxq memory */
518 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
520 otx2_err("Failed to allocate rq=%d", rq);
525 rxq->eth_dev = eth_dev;
527 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
528 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
529 rxq->wdata = (uint64_t)rq << 32;
530 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
531 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
532 eth_dev->data->port_id);
533 rxq->offloads = offloads;
535 rxq->qlen = nix_qsize_to_val(qsize);
537 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
538 rxq->tstamp = &dev->tstamp;
540 /* Alloc completion queue */
541 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
543 otx2_err("Failed to allocate rxq=%u", rq);
547 rxq->qconf.socket_id = socket;
548 rxq->qconf.nb_desc = nb_desc;
549 rxq->qconf.mempool = mp;
550 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
552 nix_rx_queue_reset(rxq);
553 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
554 rq, mp->name, qsize, nb_desc, rxq->qlen);
556 eth_dev->data->rx_queues[rq] = rxq;
557 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
559 /* Calculating delta and freq mult between PTP HI clock and tsc.
560 * These are needed in deriving raw clock value from tsc counter.
561 * read_clock eth op returns raw clock value.
563 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
564 otx2_ethdev_is_ptp_en(dev)) {
565 rc = otx2_nix_raw_clock_tsc_conv(dev);
567 otx2_err("Failed to calculate delta and freq mult");
575 otx2_nix_rx_queue_release(rxq);
580 static inline uint8_t
581 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
584 * Maximum three segments can be supported with W8, Choose
585 * NIX_MAXSQESZ_W16 for multi segment offload.
587 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
588 return NIX_MAXSQESZ_W16;
590 return NIX_MAXSQESZ_W8;
594 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
596 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
597 struct rte_eth_dev_data *data = eth_dev->data;
598 struct rte_eth_conf *conf = &data->dev_conf;
599 struct rte_eth_rxmode *rxmode = &conf->rxmode;
602 if (rxmode->mq_mode == ETH_MQ_RX_RSS)
603 flags |= NIX_RX_OFFLOAD_RSS_F;
605 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
606 DEV_RX_OFFLOAD_UDP_CKSUM))
607 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
609 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
610 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
611 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
613 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
614 flags |= NIX_RX_MULTI_SEG_F;
616 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
617 DEV_RX_OFFLOAD_QINQ_STRIP))
618 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
620 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
621 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
627 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
629 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
630 uint64_t conf = dev->tx_offloads;
633 /* Fastpath is dependent on these enums */
634 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
635 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
636 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
637 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
638 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
639 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
640 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
641 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
642 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
643 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
644 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
645 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
646 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
647 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
648 offsetof(struct rte_mbuf, buf_iova) + 8);
649 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
650 offsetof(struct rte_mbuf, buf_iova) + 16);
651 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
652 offsetof(struct rte_mbuf, ol_flags) + 12);
653 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
654 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
656 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
657 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
658 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
660 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
661 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
662 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
664 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
665 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
666 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
667 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
668 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
670 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
671 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
673 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
674 flags |= NIX_TX_MULTI_SEG_F;
676 /* Enable Inner checksum for TSO */
677 if (conf & DEV_TX_OFFLOAD_TCP_TSO)
678 flags |= (NIX_TX_OFFLOAD_TSO_F |
679 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
681 /* Enable Inner and Outer checksum for Tunnel TSO */
682 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
683 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
684 DEV_TX_OFFLOAD_GRE_TNL_TSO))
685 flags |= (NIX_TX_OFFLOAD_TSO_F |
686 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
687 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
689 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
690 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
696 nix_sq_init(struct otx2_eth_txq *txq)
698 struct otx2_eth_dev *dev = txq->dev;
699 struct otx2_mbox *mbox = dev->mbox;
700 struct nix_aq_enq_req *sq;
705 if (txq->sqb_pool->pool_id == 0)
708 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
710 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
714 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
716 sq->ctype = NIX_AQ_CTYPE_SQ;
717 sq->op = NIX_AQ_INSTOP_INIT;
718 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
721 sq->sq.smq_rr_quantum = rr_quantum;
722 sq->sq.default_chan = dev->tx_chan_base;
723 sq->sq.sqe_stype = NIX_STYPE_STF;
725 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
726 sq->sq.sqe_stype = NIX_STYPE_STP;
728 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
729 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
730 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
731 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
732 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
734 /* Many to one reduction */
735 sq->sq.qint_idx = txq->sq % dev->qints;
737 return otx2_mbox_process(mbox);
741 nix_sq_uninit(struct otx2_eth_txq *txq)
743 struct otx2_eth_dev *dev = txq->dev;
744 struct otx2_mbox *mbox = dev->mbox;
745 struct ndc_sync_op *ndc_req;
746 struct nix_aq_enq_rsp *rsp;
747 struct nix_aq_enq_req *aq;
748 uint16_t sqes_per_sqb;
752 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
754 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
756 aq->ctype = NIX_AQ_CTYPE_SQ;
757 aq->op = NIX_AQ_INSTOP_READ;
759 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
763 /* Check if sq is already cleaned up */
768 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
770 aq->ctype = NIX_AQ_CTYPE_SQ;
771 aq->op = NIX_AQ_INSTOP_WRITE;
773 aq->sq_mask.ena = ~aq->sq_mask.ena;
776 rc = otx2_mbox_process(mbox);
780 /* Read SQ and free sqb's */
781 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
783 aq->ctype = NIX_AQ_CTYPE_SQ;
784 aq->op = NIX_AQ_INSTOP_READ;
786 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
791 otx2_err("SQ has pending sqe's");
793 count = aq->sq.sqb_count;
794 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
795 /* Free SQB's that are used */
796 sqb_buf = (void *)rsp->sq.head_sqb;
800 next_sqb = *(void **)((uintptr_t)sqb_buf + (uint32_t)
801 ((sqes_per_sqb - 1) *
802 nix_sq_max_sqe_sz(txq)));
803 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
809 /* Free next to use sqb */
810 if (rsp->sq.next_sqb)
811 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
814 /* Sync NDC-NIX-TX for LF */
815 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
816 ndc_req->nix_lf_tx_sync = 1;
817 rc = otx2_mbox_process(mbox);
819 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
825 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
827 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
828 struct npa_aq_enq_req *aura_req;
830 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
831 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
832 aura_req->ctype = NPA_AQ_CTYPE_AURA;
833 aura_req->op = NPA_AQ_INSTOP_WRITE;
835 aura_req->aura.limit = nb_sqb_bufs;
836 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
838 return otx2_mbox_process(npa_lf->mbox);
842 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
844 struct otx2_eth_dev *dev = txq->dev;
845 uint16_t sqes_per_sqb, nb_sqb_bufs;
846 char name[RTE_MEMPOOL_NAMESIZE];
847 struct rte_mempool_objsz sz;
848 struct npa_aura_s *aura;
849 uint32_t tmp, blk_sz;
851 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
852 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
853 blk_sz = dev->sqb_size;
855 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
856 sqes_per_sqb = (dev->sqb_size / 8) / 16;
858 sqes_per_sqb = (dev->sqb_size / 8) / 8;
860 nb_sqb_bufs = nb_desc / sqes_per_sqb;
861 /* Clamp up to devarg passed SQB count */
862 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_DEF_SQB,
863 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
865 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
867 MEMPOOL_F_NO_SPREAD);
868 txq->nb_sqb_bufs = nb_sqb_bufs;
869 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
870 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
871 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
872 txq->nb_sqb_bufs_adj =
873 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
875 if (txq->sqb_pool == NULL) {
876 otx2_err("Failed to allocate sqe mempool");
880 memset(aura, 0, sizeof(*aura));
882 aura->fc_addr = txq->fc_iova;
883 aura->fc_hyst_bits = 0; /* Store count on all updates */
884 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
885 otx2_err("Failed to set ops for sqe mempool");
888 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
889 otx2_err("Failed to populate sqe mempool");
893 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
894 if (dev->sqb_size != sz.elt_size) {
895 otx2_err("sqe pool block size is not expected %d != %d",
900 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
908 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
910 struct nix_send_ext_s *send_hdr_ext;
911 struct nix_send_hdr_s *send_hdr;
912 struct nix_send_mem_s *send_mem;
913 union nix_send_sg_s *sg;
915 /* Initialize the fields based on basic single segment packet */
916 memset(&txq->cmd, 0, sizeof(txq->cmd));
918 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
919 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
920 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
921 send_hdr->w0.sizem1 = 2;
923 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
924 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
925 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
926 /* Default: one seg packet would have:
927 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
930 send_hdr->w0.sizem1 = 3;
931 send_hdr_ext->w0.tstmp = 1;
933 /* To calculate the offset for send_mem,
934 * send_hdr->w0.sizem1 * 2
936 send_mem = (struct nix_send_mem_s *)(txq->cmd +
937 (send_hdr->w0.sizem1 << 1));
938 send_mem->subdc = NIX_SUBDC_MEM;
939 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
940 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
942 sg = (union nix_send_sg_s *)&txq->cmd[4];
944 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
945 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
946 send_hdr->w0.sizem1 = 1;
947 sg = (union nix_send_sg_s *)&txq->cmd[2];
950 send_hdr->w0.sq = txq->sq;
951 sg->subdc = NIX_SUBDC_SG;
953 sg->ld_type = NIX_SENDLDTYPE_LDD;
959 otx2_nix_tx_queue_release(void *_txq)
961 struct otx2_eth_txq *txq = _txq;
962 struct rte_eth_dev *eth_dev;
967 eth_dev = txq->dev->eth_dev;
969 otx2_nix_dbg("Releasing txq %u", txq->sq);
971 /* Flush and disable tm */
972 otx2_nix_tm_sw_xoff(txq, eth_dev->data->dev_started);
974 /* Free sqb's and disable sq */
978 rte_mempool_free(txq->sqb_pool);
979 txq->sqb_pool = NULL;
986 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
987 uint16_t nb_desc, unsigned int socket_id,
988 const struct rte_eth_txconf *tx_conf)
990 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
991 const struct rte_memzone *fc;
992 struct otx2_eth_txq *txq;
998 /* Compile time check to make sure all fast path elements in a CL */
999 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
1001 if (tx_conf->tx_deferred_start) {
1002 otx2_err("Tx deferred start is not supported");
1006 /* Free memory prior to re-allocation if needed. */
1007 if (eth_dev->data->tx_queues[sq] != NULL) {
1008 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
1009 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
1010 eth_dev->data->tx_queues[sq] = NULL;
1013 /* Find the expected offloads for this queue */
1014 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
1016 /* Allocating tx queue data structure */
1017 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
1018 OTX2_ALIGN, socket_id);
1020 otx2_err("Failed to alloc txq=%d", sq);
1026 txq->sqb_pool = NULL;
1027 txq->offloads = offloads;
1028 dev->tx_offloads |= offloads;
1031 * Allocate memory for flow control updates from HW.
1032 * Alloc one cache line, so that fits all FC_STYPE modes.
1034 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
1035 OTX2_ALIGN + sizeof(struct npa_aura_s),
1036 OTX2_ALIGN, dev->node);
1038 otx2_err("Failed to allocate mem for fcmem");
1042 txq->fc_iova = fc->iova;
1043 txq->fc_mem = fc->addr;
1045 /* Initialize the aura sqb pool */
1046 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
1048 otx2_err("Failed to alloc sqe pool rc=%d", rc);
1052 /* Initialize the SQ */
1053 rc = nix_sq_init(txq);
1055 otx2_err("Failed to init sq=%d context", sq);
1059 txq->fc_cache_pkts = 0;
1060 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
1061 /* Evenly distribute LMT slot for each sq */
1062 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
1064 txq->qconf.socket_id = socket_id;
1065 txq->qconf.nb_desc = nb_desc;
1066 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
1068 otx2_nix_form_default_desc(txq);
1070 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
1071 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
1072 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
1073 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
1074 eth_dev->data->tx_queues[sq] = txq;
1075 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
1079 otx2_nix_tx_queue_release(txq);
1085 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1087 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1088 struct otx2_eth_qconf *tx_qconf = NULL;
1089 struct otx2_eth_qconf *rx_qconf = NULL;
1090 struct otx2_eth_txq **txq;
1091 struct otx2_eth_rxq **rxq;
1092 int i, nb_rxq, nb_txq;
1094 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1095 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1097 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1098 if (tx_qconf == NULL) {
1099 otx2_err("Failed to allocate memory for tx_qconf");
1103 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1104 if (rx_qconf == NULL) {
1105 otx2_err("Failed to allocate memory for rx_qconf");
1109 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1110 for (i = 0; i < nb_txq; i++) {
1111 if (txq[i] == NULL) {
1112 otx2_err("txq[%d] is already released", i);
1115 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1116 otx2_nix_tx_queue_release(txq[i]);
1117 eth_dev->data->tx_queues[i] = NULL;
1120 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1121 for (i = 0; i < nb_rxq; i++) {
1122 if (rxq[i] == NULL) {
1123 otx2_err("rxq[%d] is already released", i);
1126 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1127 otx2_nix_rx_queue_release(rxq[i]);
1128 eth_dev->data->rx_queues[i] = NULL;
1131 dev->tx_qconf = tx_qconf;
1132 dev->rx_qconf = rx_qconf;
1145 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1147 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1148 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1149 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1150 struct otx2_eth_txq **txq;
1151 struct otx2_eth_rxq **rxq;
1152 int rc, i, nb_rxq, nb_txq;
1154 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1155 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1158 /* Setup tx & rx queues with previous configuration so
1159 * that the queues can be functional in cases like ports
1160 * are started without re configuring queues.
1162 * Usual re config sequence is like below:
1163 * port_configure() {
1168 * queue_configure() {
1175 * In some application's control path, queue_configure() would
1176 * NOT be invoked for TXQs/RXQs in port_configure().
1177 * In such cases, queues can be functional after start as the
1178 * queues are already setup in port_configure().
1180 for (i = 0; i < nb_txq; i++) {
1181 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1182 tx_qconf[i].socket_id,
1183 &tx_qconf[i].conf.tx);
1185 otx2_err("Failed to setup tx queue rc=%d", rc);
1186 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1187 for (i -= 1; i >= 0; i--)
1188 otx2_nix_tx_queue_release(txq[i]);
1193 free(tx_qconf); tx_qconf = NULL;
1195 for (i = 0; i < nb_rxq; i++) {
1196 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1197 rx_qconf[i].socket_id,
1198 &rx_qconf[i].conf.rx,
1199 rx_qconf[i].mempool);
1201 otx2_err("Failed to setup rx queue rc=%d", rc);
1202 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1203 for (i -= 1; i >= 0; i--)
1204 otx2_nix_rx_queue_release(rxq[i]);
1205 goto release_tx_queues;
1209 free(rx_qconf); rx_qconf = NULL;
1214 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1215 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1216 otx2_nix_tx_queue_release(txq[i]);
1227 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1229 RTE_SET_USED(queue);
1230 RTE_SET_USED(mbufs);
1237 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1239 /* These dummy functions are required for supporting
1240 * some applications which reconfigure queues without
1241 * stopping tx burst and rx burst threads(eg kni app)
1242 * When the queues context is saved, txq/rxqs are released
1243 * which caused app crash since rx/tx burst is still
1244 * on different lcores
1246 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1247 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1252 nix_lso_tcp(struct nix_lso_format_cfg *req, bool v4)
1254 volatile struct nix_lso_format *field;
1256 /* Format works only with TCP packet marked by OL3/OL4 */
1257 field = (volatile struct nix_lso_format *)&req->fields[0];
1258 req->field_mask = NIX_LSO_FIELD_MASK;
1259 /* Outer IPv4/IPv6 */
1260 field->layer = NIX_TXLAYER_OL3;
1261 field->offset = v4 ? 2 : 4;
1262 field->sizem1 = 1; /* 2B */
1263 field->alg = NIX_LSOALG_ADD_PAYLEN;
1267 field->layer = NIX_TXLAYER_OL3;
1270 /* Incremented linearly per segment */
1271 field->alg = NIX_LSOALG_ADD_SEGNUM;
1275 /* TCP sequence number update */
1276 field->layer = NIX_TXLAYER_OL4;
1278 field->sizem1 = 3; /* 4 bytes */
1279 field->alg = NIX_LSOALG_ADD_OFFSET;
1281 /* TCP flags field */
1282 field->layer = NIX_TXLAYER_OL4;
1285 field->alg = NIX_LSOALG_TCP_FLAGS;
1290 nix_lso_udp_tun_tcp(struct nix_lso_format_cfg *req,
1291 bool outer_v4, bool inner_v4)
1293 volatile struct nix_lso_format *field;
1295 field = (volatile struct nix_lso_format *)&req->fields[0];
1296 req->field_mask = NIX_LSO_FIELD_MASK;
1297 /* Outer IPv4/IPv6 len */
1298 field->layer = NIX_TXLAYER_OL3;
1299 field->offset = outer_v4 ? 2 : 4;
1300 field->sizem1 = 1; /* 2B */
1301 field->alg = NIX_LSOALG_ADD_PAYLEN;
1305 field->layer = NIX_TXLAYER_OL3;
1308 /* Incremented linearly per segment */
1309 field->alg = NIX_LSOALG_ADD_SEGNUM;
1313 /* Outer UDP length */
1314 field->layer = NIX_TXLAYER_OL4;
1317 field->alg = NIX_LSOALG_ADD_PAYLEN;
1320 /* Inner IPv4/IPv6 */
1321 field->layer = NIX_TXLAYER_IL3;
1322 field->offset = inner_v4 ? 2 : 4;
1323 field->sizem1 = 1; /* 2B */
1324 field->alg = NIX_LSOALG_ADD_PAYLEN;
1328 field->layer = NIX_TXLAYER_IL3;
1331 /* Incremented linearly per segment */
1332 field->alg = NIX_LSOALG_ADD_SEGNUM;
1336 /* TCP sequence number update */
1337 field->layer = NIX_TXLAYER_IL4;
1339 field->sizem1 = 3; /* 4 bytes */
1340 field->alg = NIX_LSOALG_ADD_OFFSET;
1343 /* TCP flags field */
1344 field->layer = NIX_TXLAYER_IL4;
1347 field->alg = NIX_LSOALG_TCP_FLAGS;
1352 nix_lso_tun_tcp(struct nix_lso_format_cfg *req,
1353 bool outer_v4, bool inner_v4)
1355 volatile struct nix_lso_format *field;
1357 field = (volatile struct nix_lso_format *)&req->fields[0];
1358 req->field_mask = NIX_LSO_FIELD_MASK;
1359 /* Outer IPv4/IPv6 len */
1360 field->layer = NIX_TXLAYER_OL3;
1361 field->offset = outer_v4 ? 2 : 4;
1362 field->sizem1 = 1; /* 2B */
1363 field->alg = NIX_LSOALG_ADD_PAYLEN;
1367 field->layer = NIX_TXLAYER_OL3;
1370 /* Incremented linearly per segment */
1371 field->alg = NIX_LSOALG_ADD_SEGNUM;
1375 /* Inner IPv4/IPv6 */
1376 field->layer = NIX_TXLAYER_IL3;
1377 field->offset = inner_v4 ? 2 : 4;
1378 field->sizem1 = 1; /* 2B */
1379 field->alg = NIX_LSOALG_ADD_PAYLEN;
1383 field->layer = NIX_TXLAYER_IL3;
1386 /* Incremented linearly per segment */
1387 field->alg = NIX_LSOALG_ADD_SEGNUM;
1391 /* TCP sequence number update */
1392 field->layer = NIX_TXLAYER_IL4;
1394 field->sizem1 = 3; /* 4 bytes */
1395 field->alg = NIX_LSOALG_ADD_OFFSET;
1398 /* TCP flags field */
1399 field->layer = NIX_TXLAYER_IL4;
1402 field->alg = NIX_LSOALG_TCP_FLAGS;
1407 nix_setup_lso_formats(struct otx2_eth_dev *dev)
1409 struct otx2_mbox *mbox = dev->mbox;
1410 struct nix_lso_format_cfg_rsp *rsp;
1411 struct nix_lso_format_cfg *req;
1415 /* Skip if TSO was not requested */
1416 if (!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F))
1421 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1422 nix_lso_tcp(req, true);
1423 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1427 base = rsp->lso_format_idx;
1428 if (base != NIX_LSO_FORMAT_IDX_TSOV4)
1430 dev->lso_base_idx = base;
1431 otx2_nix_dbg("tcpv4 lso fmt=%u", base);
1437 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1438 nix_lso_tcp(req, false);
1439 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1443 if (rsp->lso_format_idx != base + 1)
1445 otx2_nix_dbg("tcpv6 lso fmt=%u\n", base + 1);
1448 * IPv4/UDP/TUN HDR/IPv4/TCP LSO
1450 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1451 nix_lso_udp_tun_tcp(req, true, true);
1452 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1456 if (rsp->lso_format_idx != base + 2)
1458 otx2_nix_dbg("udp tun v4v4 fmt=%u\n", base + 2);
1461 * IPv4/UDP/TUN HDR/IPv6/TCP LSO
1463 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1464 nix_lso_udp_tun_tcp(req, true, false);
1465 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1469 if (rsp->lso_format_idx != base + 3)
1471 otx2_nix_dbg("udp tun v4v6 fmt=%u\n", base + 3);
1474 * IPv6/UDP/TUN HDR/IPv4/TCP LSO
1476 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1477 nix_lso_udp_tun_tcp(req, false, true);
1478 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1482 if (rsp->lso_format_idx != base + 4)
1484 otx2_nix_dbg("udp tun v6v4 fmt=%u\n", base + 4);
1487 * IPv6/UDP/TUN HDR/IPv6/TCP LSO
1489 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1490 nix_lso_udp_tun_tcp(req, false, false);
1491 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1494 if (rsp->lso_format_idx != base + 5)
1496 otx2_nix_dbg("udp tun v6v6 fmt=%u\n", base + 5);
1499 * IPv4/TUN HDR/IPv4/TCP LSO
1501 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1502 nix_lso_tun_tcp(req, true, true);
1503 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1507 if (rsp->lso_format_idx != base + 6)
1509 otx2_nix_dbg("tun v4v4 fmt=%u\n", base + 6);
1512 * IPv4/TUN HDR/IPv6/TCP LSO
1514 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1515 nix_lso_tun_tcp(req, true, false);
1516 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1520 if (rsp->lso_format_idx != base + 7)
1522 otx2_nix_dbg("tun v4v6 fmt=%u\n", base + 7);
1525 * IPv6/TUN HDR/IPv4/TCP LSO
1527 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1528 nix_lso_tun_tcp(req, false, true);
1529 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1533 if (rsp->lso_format_idx != base + 8)
1535 otx2_nix_dbg("tun v6v4 fmt=%u\n", base + 8);
1538 * IPv6/TUN HDR/IPv6/TCP LSO
1540 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1541 nix_lso_tun_tcp(req, false, false);
1542 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1545 if (rsp->lso_format_idx != base + 9)
1547 otx2_nix_dbg("tun v6v6 fmt=%u\n", base + 9);
1552 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1554 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1555 struct rte_eth_dev_data *data = eth_dev->data;
1556 struct rte_eth_conf *conf = &data->dev_conf;
1557 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1558 struct rte_eth_txmode *txmode = &conf->txmode;
1559 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1560 struct rte_ether_addr *ea;
1561 uint8_t nb_rxq, nb_txq;
1567 if (rte_eal_has_hugepages() == 0) {
1568 otx2_err("Huge page is not configured");
1569 goto fail_configure;
1572 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1573 otx2_err("Setting link speed/duplex not supported");
1574 goto fail_configure;
1577 if (conf->dcb_capability_en == 1) {
1578 otx2_err("dcb enable is not supported");
1579 goto fail_configure;
1582 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1583 otx2_err("Flow director is not supported");
1584 goto fail_configure;
1587 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1588 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1589 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1590 goto fail_configure;
1593 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1594 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1595 goto fail_configure;
1598 if (otx2_dev_is_Ax(dev) &&
1599 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1600 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1601 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1602 otx2_err("Outer IP and SCTP checksum unsupported");
1603 goto fail_configure;
1606 /* Free the resources allocated from the previous configure */
1607 if (dev->configured == 1) {
1608 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1609 otx2_nix_vlan_fini(eth_dev);
1610 otx2_nix_mc_addr_list_uninstall(eth_dev);
1611 otx2_flow_free_all_resources(dev);
1612 oxt2_nix_unregister_queue_irqs(eth_dev);
1613 if (eth_dev->data->dev_conf.intr_conf.rxq)
1614 oxt2_nix_unregister_cq_irqs(eth_dev);
1615 nix_set_nop_rxtx_function(eth_dev);
1616 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1618 goto fail_configure;
1619 otx2_nix_tm_fini(eth_dev);
1623 dev->rx_offloads = rxmode->offloads;
1624 dev->tx_offloads = txmode->offloads;
1625 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1626 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1627 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1629 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1630 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1632 /* Alloc a nix lf */
1633 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1635 otx2_err("Failed to init nix_lf rc=%d", rc);
1639 rc = nix_lf_switch_header_type_enable(dev);
1641 otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
1645 rc = nix_setup_lso_formats(dev);
1647 otx2_err("failed to setup nix lso format fields, rc=%d", rc);
1652 rc = otx2_nix_rss_config(eth_dev);
1654 otx2_err("Failed to configure rss rc=%d", rc);
1658 /* Init the default TM scheduler hierarchy */
1659 rc = otx2_nix_tm_init_default(eth_dev);
1661 otx2_err("Failed to init traffic manager rc=%d", rc);
1665 rc = otx2_nix_vlan_offload_init(eth_dev);
1667 otx2_err("Failed to init vlan offload rc=%d", rc);
1671 /* Register queue IRQs */
1672 rc = oxt2_nix_register_queue_irqs(eth_dev);
1674 otx2_err("Failed to register queue interrupts rc=%d", rc);
1678 /* Register cq IRQs */
1679 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1680 if (eth_dev->data->nb_rx_queues > dev->cints) {
1681 otx2_err("Rx interrupt cannot be enabled, rxq > %d",
1685 /* Rx interrupt feature cannot work with vector mode because,
1686 * vector mode doesn't process packets unless min 4 pkts are
1687 * received, while cq interrupts are generated even for 1 pkt
1690 dev->scalar_ena = true;
1692 rc = oxt2_nix_register_cq_irqs(eth_dev);
1694 otx2_err("Failed to register CQ interrupts rc=%d", rc);
1699 /* Configure loop back mode */
1700 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1702 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1706 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1708 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1712 rc = otx2_nix_mc_addr_list_install(eth_dev);
1714 otx2_err("Failed to install mc address list rc=%d", rc);
1719 * Restore queue config when reconfigure followed by
1720 * reconfigure and no queue configure invoked from application case.
1722 if (dev->configured == 1) {
1723 rc = nix_restore_queue_cfg(eth_dev);
1725 goto uninstall_mc_list;
1728 /* Update the mac address */
1729 ea = eth_dev->data->mac_addrs;
1730 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1731 if (rte_is_zero_ether_addr(ea))
1732 rte_eth_random_addr((uint8_t *)ea);
1734 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1736 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1737 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1738 " rx_flags=0x%x tx_flags=0x%x",
1739 eth_dev->data->port_id, ea_fmt, nb_rxq,
1740 nb_txq, dev->rx_offloads, dev->tx_offloads,
1741 dev->rx_offload_flags, dev->tx_offload_flags);
1744 dev->configured = 1;
1745 dev->configured_nb_rx_qs = data->nb_rx_queues;
1746 dev->configured_nb_tx_qs = data->nb_tx_queues;
1750 otx2_nix_mc_addr_list_uninstall(eth_dev);
1752 oxt2_nix_unregister_cq_irqs(eth_dev);
1754 oxt2_nix_unregister_queue_irqs(eth_dev);
1756 otx2_nix_vlan_fini(eth_dev);
1758 otx2_nix_tm_fini(eth_dev);
1762 dev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);
1763 dev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);
1765 dev->configured = 0;
1770 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1772 struct rte_eth_dev_data *data = eth_dev->data;
1773 struct otx2_eth_txq *txq;
1776 txq = eth_dev->data->tx_queues[qidx];
1778 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1781 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1783 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1788 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1795 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1797 struct rte_eth_dev_data *data = eth_dev->data;
1798 struct otx2_eth_txq *txq;
1801 txq = eth_dev->data->tx_queues[qidx];
1803 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1806 txq->fc_cache_pkts = 0;
1808 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1810 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1815 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1822 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1824 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1825 struct rte_eth_dev_data *data = eth_dev->data;
1828 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1831 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1833 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1837 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1844 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1846 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1847 struct rte_eth_dev_data *data = eth_dev->data;
1850 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1853 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1855 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1859 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1866 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
1868 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1869 struct rte_mbuf *rx_pkts[32];
1870 struct otx2_eth_rxq *rxq;
1871 int count, i, j, rc;
1873 nix_cgx_stop_link_event(dev);
1874 npc_rx_disable(dev);
1876 /* Stop rx queues and free up pkts pending */
1877 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1878 rc = otx2_nix_rx_queue_stop(eth_dev, i);
1882 rxq = eth_dev->data->rx_queues[i];
1883 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1885 for (j = 0; j < count; j++)
1886 rte_pktmbuf_free(rx_pkts[j]);
1887 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1891 /* Stop tx queues */
1892 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1893 otx2_nix_tx_queue_stop(eth_dev, i);
1897 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
1899 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1902 if (eth_dev->data->nb_rx_queues != 0) {
1903 rc = otx2_nix_recalc_mtu(eth_dev);
1908 /* Start rx queues */
1909 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1910 rc = otx2_nix_rx_queue_start(eth_dev, i);
1915 /* Start tx queues */
1916 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1917 rc = otx2_nix_tx_queue_start(eth_dev, i);
1922 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
1924 otx2_err("Failed to update flow ctrl mode %d", rc);
1928 /* Enable PTP if it was requested by the app or if it is already
1929 * enabled in PF owning this VF
1931 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
1932 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
1933 otx2_ethdev_is_ptp_en(dev))
1934 otx2_nix_timesync_enable(eth_dev);
1936 otx2_nix_timesync_disable(eth_dev);
1938 rc = npc_rx_enable(dev);
1940 otx2_err("Failed to enable NPC rx %d", rc);
1944 otx2_nix_toggle_flag_link_cfg(dev, true);
1946 rc = nix_cgx_start_link_event(dev);
1948 otx2_err("Failed to start cgx link event %d", rc);
1952 otx2_nix_toggle_flag_link_cfg(dev, false);
1953 otx2_eth_set_tx_function(eth_dev);
1954 otx2_eth_set_rx_function(eth_dev);
1959 npc_rx_disable(dev);
1960 otx2_nix_toggle_flag_link_cfg(dev, false);
1964 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
1965 static void otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
1967 /* Initialize and register driver with DPDK Application */
1968 static const struct eth_dev_ops otx2_eth_dev_ops = {
1969 .dev_infos_get = otx2_nix_info_get,
1970 .dev_configure = otx2_nix_configure,
1971 .link_update = otx2_nix_link_update,
1972 .tx_queue_setup = otx2_nix_tx_queue_setup,
1973 .tx_queue_release = otx2_nix_tx_queue_release,
1974 .rx_queue_setup = otx2_nix_rx_queue_setup,
1975 .rx_queue_release = otx2_nix_rx_queue_release,
1976 .dev_start = otx2_nix_dev_start,
1977 .dev_stop = otx2_nix_dev_stop,
1978 .dev_close = otx2_nix_dev_close,
1979 .tx_queue_start = otx2_nix_tx_queue_start,
1980 .tx_queue_stop = otx2_nix_tx_queue_stop,
1981 .rx_queue_start = otx2_nix_rx_queue_start,
1982 .rx_queue_stop = otx2_nix_rx_queue_stop,
1983 .dev_set_link_up = otx2_nix_dev_set_link_up,
1984 .dev_set_link_down = otx2_nix_dev_set_link_down,
1985 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
1986 .dev_reset = otx2_nix_dev_reset,
1987 .stats_get = otx2_nix_dev_stats_get,
1988 .stats_reset = otx2_nix_dev_stats_reset,
1989 .get_reg = otx2_nix_dev_get_reg,
1990 .mtu_set = otx2_nix_mtu_set,
1991 .mac_addr_add = otx2_nix_mac_addr_add,
1992 .mac_addr_remove = otx2_nix_mac_addr_del,
1993 .mac_addr_set = otx2_nix_mac_addr_set,
1994 .set_mc_addr_list = otx2_nix_set_mc_addr_list,
1995 .promiscuous_enable = otx2_nix_promisc_enable,
1996 .promiscuous_disable = otx2_nix_promisc_disable,
1997 .allmulticast_enable = otx2_nix_allmulticast_enable,
1998 .allmulticast_disable = otx2_nix_allmulticast_disable,
1999 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
2000 .reta_update = otx2_nix_dev_reta_update,
2001 .reta_query = otx2_nix_dev_reta_query,
2002 .rss_hash_update = otx2_nix_rss_hash_update,
2003 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
2004 .xstats_get = otx2_nix_xstats_get,
2005 .xstats_get_names = otx2_nix_xstats_get_names,
2006 .xstats_reset = otx2_nix_xstats_reset,
2007 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
2008 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
2009 .rxq_info_get = otx2_nix_rxq_info_get,
2010 .txq_info_get = otx2_nix_txq_info_get,
2011 .rx_queue_count = otx2_nix_rx_queue_count,
2012 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
2013 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
2014 .tx_descriptor_status = otx2_nix_tx_descriptor_status,
2015 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
2016 .pool_ops_supported = otx2_nix_pool_ops_supported,
2017 .filter_ctrl = otx2_nix_dev_filter_ctrl,
2018 .get_module_info = otx2_nix_get_module_info,
2019 .get_module_eeprom = otx2_nix_get_module_eeprom,
2020 .fw_version_get = otx2_nix_fw_version_get,
2021 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
2022 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
2023 .timesync_enable = otx2_nix_timesync_enable,
2024 .timesync_disable = otx2_nix_timesync_disable,
2025 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
2026 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
2027 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
2028 .timesync_read_time = otx2_nix_timesync_read_time,
2029 .timesync_write_time = otx2_nix_timesync_write_time,
2030 .vlan_offload_set = otx2_nix_vlan_offload_set,
2031 .vlan_filter_set = otx2_nix_vlan_filter_set,
2032 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
2033 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
2034 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
2035 .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
2036 .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
2037 .read_clock = otx2_nix_read_clock,
2041 nix_lf_attach(struct otx2_eth_dev *dev)
2043 struct otx2_mbox *mbox = dev->mbox;
2044 struct rsrc_attach_req *req;
2046 /* Attach NIX(lf) */
2047 req = otx2_mbox_alloc_msg_attach_resources(mbox);
2051 return otx2_mbox_process(mbox);
2055 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
2057 struct otx2_mbox *mbox = dev->mbox;
2058 struct msix_offset_rsp *msix_rsp;
2061 /* Get NPA and NIX MSIX vector offsets */
2062 otx2_mbox_alloc_msg_msix_offset(mbox);
2064 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
2066 dev->nix_msixoff = msix_rsp->nix_msixoff;
2072 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
2074 struct rsrc_detach_req *req;
2076 req = otx2_mbox_alloc_msg_detach_resources(mbox);
2078 /* Detach all except npa lf */
2079 req->partial = true;
2086 return otx2_mbox_process(mbox);
2090 otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
2092 if (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||
2093 pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2099 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
2101 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2102 struct rte_pci_device *pci_dev;
2103 int rc, max_entries;
2105 eth_dev->dev_ops = &otx2_eth_dev_ops;
2107 /* For secondary processes, the primary has done all the work */
2108 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2109 /* Setup callbacks for secondary process */
2110 otx2_eth_set_tx_function(eth_dev);
2111 otx2_eth_set_rx_function(eth_dev);
2115 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2117 rte_eth_copy_pci_info(eth_dev, pci_dev);
2118 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2120 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
2121 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
2122 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
2124 /* Parse devargs string */
2125 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
2127 otx2_err("Failed to parse devargs rc=%d", rc);
2131 if (!dev->mbox_active) {
2132 /* Initialize the base otx2_dev object
2133 * only if already present
2135 rc = otx2_dev_init(pci_dev, dev);
2137 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
2141 if (otx2_eth_dev_is_sdp(pci_dev))
2142 dev->sdp_link = true;
2144 dev->sdp_link = false;
2145 /* Device generic callbacks */
2146 dev->ops = &otx2_dev_ops;
2147 dev->eth_dev = eth_dev;
2149 /* Grab the NPA LF if required */
2150 rc = otx2_npa_lf_init(pci_dev, dev);
2152 goto otx2_dev_uninit;
2154 dev->configured = 0;
2155 dev->drv_inited = true;
2156 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
2157 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
2160 rc = nix_lf_attach(dev);
2162 goto otx2_npa_uninit;
2164 /* Get NIX MSIX offset */
2165 rc = nix_lf_get_msix_offset(dev);
2167 goto otx2_npa_uninit;
2169 /* Register LF irq handlers */
2170 rc = otx2_nix_register_irqs(eth_dev);
2174 /* Get maximum number of supported MAC entries */
2175 max_entries = otx2_cgx_mac_max_entries_get(dev);
2176 if (max_entries < 0) {
2177 otx2_err("Failed to get max entries for mac addr");
2179 goto unregister_irq;
2182 /* For VFs, returned max_entries will be 0. But to keep default MAC
2183 * address, one entry must be allocated. So setting up to 1.
2185 if (max_entries == 0)
2188 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
2189 RTE_ETHER_ADDR_LEN, 0);
2190 if (eth_dev->data->mac_addrs == NULL) {
2191 otx2_err("Failed to allocate memory for mac addr");
2193 goto unregister_irq;
2196 dev->max_mac_entries = max_entries;
2198 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
2200 goto free_mac_addrs;
2202 /* Update the mac address */
2203 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
2205 /* Also sync same MAC address to CGX table */
2206 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
2208 /* Initialize the tm data structures */
2209 otx2_nix_tm_conf_init(eth_dev);
2211 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
2212 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
2214 if (otx2_dev_is_96xx_A0(dev) ||
2215 otx2_dev_is_95xx_Ax(dev)) {
2216 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
2217 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
2220 /* Initialize rte-flow */
2221 rc = otx2_flow_init(dev);
2223 goto free_mac_addrs;
2225 otx2_nix_mc_filter_init(dev);
2227 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
2228 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
2229 eth_dev->data->port_id, dev->pf, dev->vf,
2230 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
2231 dev->rx_offload_capa, dev->tx_offload_capa);
2235 rte_free(eth_dev->data->mac_addrs);
2237 otx2_nix_unregister_irqs(eth_dev);
2239 otx2_eth_dev_lf_detach(dev->mbox);
2243 otx2_dev_fini(pci_dev, dev);
2245 otx2_err("Failed to init nix eth_dev rc=%d", rc);
2250 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
2252 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2253 struct rte_pci_device *pci_dev;
2256 /* Nothing to be done for secondary processes */
2257 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2260 /* Clear the flag since we are closing down */
2261 dev->configured = 0;
2263 /* Disable nix bpid config */
2264 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
2266 npc_rx_disable(dev);
2268 /* Disable vlan offloads */
2269 otx2_nix_vlan_fini(eth_dev);
2271 /* Disable other rte_flow entries */
2272 otx2_flow_fini(dev);
2274 /* Free multicast filter list */
2275 otx2_nix_mc_filter_fini(dev);
2277 /* Disable PTP if already enabled */
2278 if (otx2_ethdev_is_ptp_en(dev))
2279 otx2_nix_timesync_disable(eth_dev);
2281 nix_cgx_stop_link_event(dev);
2284 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
2285 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
2286 eth_dev->data->tx_queues[i] = NULL;
2288 eth_dev->data->nb_tx_queues = 0;
2290 /* Free up RQ's and CQ's */
2291 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2292 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
2293 eth_dev->data->rx_queues[i] = NULL;
2295 eth_dev->data->nb_rx_queues = 0;
2297 /* Free tm resources */
2298 rc = otx2_nix_tm_fini(eth_dev);
2300 otx2_err("Failed to cleanup tm, rc=%d", rc);
2302 /* Unregister queue irqs */
2303 oxt2_nix_unregister_queue_irqs(eth_dev);
2305 /* Unregister cq irqs */
2306 if (eth_dev->data->dev_conf.intr_conf.rxq)
2307 oxt2_nix_unregister_cq_irqs(eth_dev);
2309 rc = nix_lf_free(dev);
2311 otx2_err("Failed to free nix lf, rc=%d", rc);
2313 rc = otx2_npa_lf_fini();
2315 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
2317 rte_free(eth_dev->data->mac_addrs);
2318 eth_dev->data->mac_addrs = NULL;
2319 dev->drv_inited = false;
2321 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2322 otx2_nix_unregister_irqs(eth_dev);
2324 rc = otx2_eth_dev_lf_detach(dev->mbox);
2326 otx2_err("Failed to detach resources, rc=%d", rc);
2328 /* Check if mbox close is needed */
2332 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
2333 /* Will be freed later by PMD */
2334 eth_dev->data->dev_private = NULL;
2338 otx2_dev_fini(pci_dev, dev);
2343 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
2345 otx2_eth_dev_uninit(eth_dev, true);
2349 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
2353 rc = otx2_eth_dev_uninit(eth_dev, false);
2357 return otx2_eth_dev_init(eth_dev);
2361 nix_remove(struct rte_pci_device *pci_dev)
2363 struct rte_eth_dev *eth_dev;
2364 struct otx2_idev_cfg *idev;
2365 struct otx2_dev *otx2_dev;
2368 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
2370 /* Cleanup eth dev */
2371 rc = otx2_eth_dev_uninit(eth_dev, true);
2375 rte_eth_dev_pci_release(eth_dev);
2378 /* Nothing to be done for secondary processes */
2379 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2382 /* Check for common resources */
2383 idev = otx2_intra_dev_get_cfg();
2384 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
2387 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
2389 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
2392 /* Safe to cleanup mbox as no more users */
2393 otx2_dev_fini(pci_dev, otx2_dev);
2398 otx2_info("%s: common resource in use by other devices", pci_dev->name);
2403 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
2407 RTE_SET_USED(pci_drv);
2409 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
2412 /* On error on secondary, recheck if port exists in primary or
2413 * in mid of detach state.
2415 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
2416 if (!rte_eth_dev_allocated(pci_dev->device.name))
2421 static const struct rte_pci_id pci_nix_map[] = {
2423 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
2426 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
2429 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2430 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
2433 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2434 PCI_DEVID_OCTEONTX2_RVU_SDP_PF)
2437 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2438 PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2445 static struct rte_pci_driver pci_nix = {
2446 .id_table = pci_nix_map,
2447 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
2448 RTE_PCI_DRV_INTR_LSC,
2450 .remove = nix_remove,
2453 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
2454 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
2455 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");