1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_ethdev_pci.h>
9 #include <rte_malloc.h>
11 #include <rte_mbuf_pool_ops.h>
12 #include <rte_mempool.h>
14 #include "otx2_ethdev.h"
16 static inline uint64_t
17 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
19 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
21 if (otx2_dev_is_vf(dev))
22 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
27 static inline uint64_t
28 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
30 uint64_t capa = NIX_TX_OFFLOAD_CAPA;
32 /* TSO not supported for earlier chip revisions */
33 if (otx2_dev_is_96xx_A0(dev) || otx2_dev_is_95xx_Ax(dev))
34 capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
35 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
36 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
37 DEV_TX_OFFLOAD_GRE_TNL_TSO);
41 static const struct otx2_dev_ops otx2_dev_ops = {
42 .link_status_update = otx2_eth_dev_link_status_update,
43 .ptp_info_update = otx2_eth_dev_ptp_info_update
47 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
49 struct otx2_mbox *mbox = dev->mbox;
50 struct nix_lf_alloc_req *req;
51 struct nix_lf_alloc_rsp *rsp;
54 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
58 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
59 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
60 req->xqe_sz = NIX_XQESZ_W16;
61 req->rss_sz = dev->rss_info.rss_size;
62 req->rss_grps = NIX_RSS_GRPS;
63 req->npa_func = otx2_npa_pf_func_get();
64 req->sso_func = otx2_sso_pf_func_get();
65 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
66 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
67 DEV_RX_OFFLOAD_UDP_CKSUM)) {
68 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
69 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
71 req->rx_cfg |= BIT_ULL(32 /* DROP_RE */);
73 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
77 dev->sqb_size = rsp->sqb_size;
78 dev->tx_chan_base = rsp->tx_chan_base;
79 dev->rx_chan_base = rsp->rx_chan_base;
80 dev->rx_chan_cnt = rsp->rx_chan_cnt;
81 dev->tx_chan_cnt = rsp->tx_chan_cnt;
82 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
83 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
84 dev->lf_tx_stats = rsp->lf_tx_stats;
85 dev->lf_rx_stats = rsp->lf_rx_stats;
86 dev->cints = rsp->cints;
87 dev->qints = rsp->qints;
88 dev->npc_flow.channel = dev->rx_chan_base;
94 nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev)
96 struct otx2_mbox *mbox = dev->mbox;
97 struct npc_set_pkind *req;
101 if (dev->npc_flow.switch_header_type == 0)
104 /* Notify AF about higig2 config */
105 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
106 req->mode = dev->npc_flow.switch_header_type;
108 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
111 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
112 req->mode = dev->npc_flow.switch_header_type;
114 return otx2_mbox_process_msg(mbox, (void *)&rsp);
118 nix_lf_free(struct otx2_eth_dev *dev)
120 struct otx2_mbox *mbox = dev->mbox;
121 struct nix_lf_free_req *req;
122 struct ndc_sync_op *ndc_req;
125 /* Sync NDC-NIX for LF */
126 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
127 ndc_req->nix_lf_tx_sync = 1;
128 ndc_req->nix_lf_rx_sync = 1;
129 rc = otx2_mbox_process(mbox);
131 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
133 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
134 /* Let AF driver free all this nix lf's
135 * NPC entries allocated using NPC MBOX.
139 return otx2_mbox_process(mbox);
143 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
145 struct otx2_mbox *mbox = dev->mbox;
147 if (otx2_dev_is_vf_or_sdp(dev))
150 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
152 return otx2_mbox_process(mbox);
156 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
158 struct otx2_mbox *mbox = dev->mbox;
160 if (otx2_dev_is_vf_or_sdp(dev))
163 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
165 return otx2_mbox_process(mbox);
169 npc_rx_enable(struct otx2_eth_dev *dev)
171 struct otx2_mbox *mbox = dev->mbox;
173 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
175 return otx2_mbox_process(mbox);
179 npc_rx_disable(struct otx2_eth_dev *dev)
181 struct otx2_mbox *mbox = dev->mbox;
183 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
185 return otx2_mbox_process(mbox);
189 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
191 struct otx2_mbox *mbox = dev->mbox;
193 if (otx2_dev_is_vf_or_sdp(dev))
196 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
198 return otx2_mbox_process(mbox);
202 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
204 struct otx2_mbox *mbox = dev->mbox;
206 if (otx2_dev_is_vf_or_sdp(dev))
210 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
212 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
214 return otx2_mbox_process(mbox);
218 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
220 struct otx2_mbox *mbox = dev->mbox;
222 if (otx2_dev_is_vf_or_sdp(dev))
225 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
227 return otx2_mbox_process(mbox);
231 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
237 static inline uint32_t
238 nix_qsize_to_val(enum nix_q_size_e qsize)
240 return (16UL << (qsize * 2));
243 static inline enum nix_q_size_e
244 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
248 if (otx2_ethdev_fixup_is_min_4k_q(dev))
253 for (; i < nix_q_size_max; i++)
254 if (val <= nix_qsize_to_val(i))
257 if (i >= nix_q_size_max)
258 i = nix_q_size_max - 1;
264 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
265 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
267 struct otx2_mbox *mbox = dev->mbox;
268 const struct rte_memzone *rz;
269 uint32_t ring_size, cq_size;
270 struct nix_aq_enq_req *aq;
275 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
276 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
277 NIX_CQ_ALIGN, dev->node);
279 otx2_err("Failed to allocate mem for cq hw ring");
283 memset(rz->addr, 0, rz->len);
284 rxq->desc = (uintptr_t)rz->addr;
285 rxq->qmask = cq_size - 1;
287 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
289 aq->ctype = NIX_AQ_CTYPE_CQ;
290 aq->op = NIX_AQ_INSTOP_INIT;
294 aq->cq.qsize = rxq->qsize;
295 aq->cq.base = rz->iova;
296 aq->cq.avg_level = 0xff;
297 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
298 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
300 /* Many to one reduction */
301 aq->cq.qint_idx = qid % dev->qints;
302 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
303 aq->cq.cint_idx = qid;
305 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
306 const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
307 uint16_t min_rx_drop;
309 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
310 aq->cq.drop = min_rx_drop;
312 rxq->cq_drop = min_rx_drop;
314 rxq->cq_drop = NIX_CQ_THRESH_LEVEL;
315 aq->cq.drop = rxq->cq_drop;
319 /* TX pause frames enable flowctrl on RX side */
320 if (dev->fc_info.tx_pause) {
321 /* Single bpid is allocated for all rx channels for now */
322 aq->cq.bpid = dev->fc_info.bpid[0];
323 aq->cq.bp = rxq->cq_drop;
327 rc = otx2_mbox_process(mbox);
329 otx2_err("Failed to init cq context");
333 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
335 aq->ctype = NIX_AQ_CTYPE_RQ;
336 aq->op = NIX_AQ_INSTOP_INIT;
339 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
341 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
342 first_skip = (sizeof(struct rte_mbuf));
343 first_skip += RTE_PKTMBUF_HEADROOM;
344 first_skip += rte_pktmbuf_priv_size(mp);
345 rxq->data_off = first_skip;
347 first_skip /= 8; /* Expressed in number of dwords */
348 aq->rq.first_skip = first_skip;
349 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
350 aq->rq.flow_tagw = 32; /* 32-bits */
351 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
352 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
353 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
354 aq->rq.lpb_sizem1 /= 8;
355 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
357 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
358 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
359 aq->rq.rq_int_ena = 0;
360 /* Many to one reduction */
361 aq->rq.qint_idx = qid % dev->qints;
363 aq->rq.xqe_drop_ena = 1;
365 rc = otx2_mbox_process(mbox);
367 otx2_err("Failed to init rq context");
377 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
378 struct otx2_eth_rxq *rxq, const bool enb)
380 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
381 struct otx2_mbox *mbox = dev->mbox;
382 struct nix_aq_enq_req *aq;
384 /* Pkts will be dropped silently if RQ is disabled */
385 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
387 aq->ctype = NIX_AQ_CTYPE_RQ;
388 aq->op = NIX_AQ_INSTOP_WRITE;
391 aq->rq_mask.ena = ~(aq->rq_mask.ena);
393 return otx2_mbox_process(mbox);
397 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
399 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
400 struct otx2_mbox *mbox = dev->mbox;
401 struct nix_aq_enq_req *aq;
404 /* RQ is already disabled */
406 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
408 aq->ctype = NIX_AQ_CTYPE_CQ;
409 aq->op = NIX_AQ_INSTOP_WRITE;
412 aq->cq_mask.ena = ~(aq->cq_mask.ena);
414 rc = otx2_mbox_process(mbox);
416 otx2_err("Failed to disable cq context");
424 nix_get_data_off(struct otx2_eth_dev *dev)
426 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
430 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
432 struct rte_mbuf mb_def;
435 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
436 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
437 offsetof(struct rte_mbuf, data_off) != 2);
438 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
439 offsetof(struct rte_mbuf, data_off) != 4);
440 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
441 offsetof(struct rte_mbuf, data_off) != 6);
443 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
444 mb_def.port = port_id;
445 rte_mbuf_refcnt_set(&mb_def, 1);
447 /* Prevent compiler reordering: rearm_data covers previous fields */
448 rte_compiler_barrier();
449 tmp = (uint64_t *)&mb_def.rearm_data;
455 otx2_nix_rx_queue_release(void *rx_queue)
457 struct otx2_eth_rxq *rxq = rx_queue;
462 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
463 nix_cq_rq_uninit(rxq->eth_dev, rxq);
468 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
469 uint16_t nb_desc, unsigned int socket,
470 const struct rte_eth_rxconf *rx_conf,
471 struct rte_mempool *mp)
473 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
474 struct rte_mempool_ops *ops;
475 struct otx2_eth_rxq *rxq;
476 const char *platform_ops;
477 enum nix_q_size_e qsize;
483 /* Compile time check to make sure all fast path elements in a CL */
484 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
487 if (rx_conf->rx_deferred_start == 1) {
488 otx2_err("Deferred Rx start is not supported");
492 platform_ops = rte_mbuf_platform_mempool_ops();
493 /* This driver needs octeontx2_npa mempool ops to work */
494 ops = rte_mempool_get_ops(mp->ops_index);
495 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
496 otx2_err("mempool ops should be of octeontx2_npa type");
500 if (mp->pool_id == 0) {
501 otx2_err("Invalid pool_id");
505 /* Free memory prior to re-allocation if needed */
506 if (eth_dev->data->rx_queues[rq] != NULL) {
507 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
508 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
509 eth_dev->data->rx_queues[rq] = NULL;
512 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
513 dev->rx_offloads |= offloads;
515 /* Find the CQ queue size */
516 qsize = nix_qsize_clampup_get(dev, nb_desc);
517 /* Allocate rxq memory */
518 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
520 otx2_err("Failed to allocate rq=%d", rq);
525 rxq->eth_dev = eth_dev;
527 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
528 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
529 rxq->wdata = (uint64_t)rq << 32;
530 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
531 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
532 eth_dev->data->port_id);
533 rxq->offloads = offloads;
535 rxq->qlen = nix_qsize_to_val(qsize);
537 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
538 rxq->tstamp = &dev->tstamp;
540 /* Alloc completion queue */
541 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
543 otx2_err("Failed to allocate rxq=%u", rq);
547 rxq->qconf.socket_id = socket;
548 rxq->qconf.nb_desc = nb_desc;
549 rxq->qconf.mempool = mp;
550 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
552 nix_rx_queue_reset(rxq);
553 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
554 rq, mp->name, qsize, nb_desc, rxq->qlen);
556 eth_dev->data->rx_queues[rq] = rxq;
557 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
559 /* Calculating delta and freq mult between PTP HI clock and tsc.
560 * These are needed in deriving raw clock value from tsc counter.
561 * read_clock eth op returns raw clock value.
563 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
564 otx2_ethdev_is_ptp_en(dev)) {
565 rc = otx2_nix_raw_clock_tsc_conv(dev);
567 otx2_err("Failed to calculate delta and freq mult");
575 otx2_nix_rx_queue_release(rxq);
580 static inline uint8_t
581 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
584 * Maximum three segments can be supported with W8, Choose
585 * NIX_MAXSQESZ_W16 for multi segment offload.
587 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
588 return NIX_MAXSQESZ_W16;
590 return NIX_MAXSQESZ_W8;
594 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
596 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
597 struct rte_eth_dev_data *data = eth_dev->data;
598 struct rte_eth_conf *conf = &data->dev_conf;
599 struct rte_eth_rxmode *rxmode = &conf->rxmode;
602 if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
603 (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
604 flags |= NIX_RX_OFFLOAD_RSS_F;
606 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
607 DEV_RX_OFFLOAD_UDP_CKSUM))
608 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
610 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
611 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
612 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
614 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
615 flags |= NIX_RX_MULTI_SEG_F;
617 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
618 DEV_RX_OFFLOAD_QINQ_STRIP))
619 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
621 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
622 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
628 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
630 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
631 uint64_t conf = dev->tx_offloads;
634 /* Fastpath is dependent on these enums */
635 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
636 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
637 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
638 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
639 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
640 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
641 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
642 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
643 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
644 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
645 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
646 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
647 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
648 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
649 offsetof(struct rte_mbuf, buf_iova) + 8);
650 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
651 offsetof(struct rte_mbuf, buf_iova) + 16);
652 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
653 offsetof(struct rte_mbuf, ol_flags) + 12);
654 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
655 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
657 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
658 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
659 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
661 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
662 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
663 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
665 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
666 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
667 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
668 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
669 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
671 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
672 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
674 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
675 flags |= NIX_TX_MULTI_SEG_F;
677 /* Enable Inner checksum for TSO */
678 if (conf & DEV_TX_OFFLOAD_TCP_TSO)
679 flags |= (NIX_TX_OFFLOAD_TSO_F |
680 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
682 /* Enable Inner and Outer checksum for Tunnel TSO */
683 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
684 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
685 DEV_TX_OFFLOAD_GRE_TNL_TSO))
686 flags |= (NIX_TX_OFFLOAD_TSO_F |
687 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
688 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
690 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
691 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
697 nix_sq_init(struct otx2_eth_txq *txq)
699 struct otx2_eth_dev *dev = txq->dev;
700 struct otx2_mbox *mbox = dev->mbox;
701 struct nix_aq_enq_req *sq;
706 if (txq->sqb_pool->pool_id == 0)
709 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
711 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
715 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
717 sq->ctype = NIX_AQ_CTYPE_SQ;
718 sq->op = NIX_AQ_INSTOP_INIT;
719 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
722 sq->sq.smq_rr_quantum = rr_quantum;
723 sq->sq.default_chan = dev->tx_chan_base;
724 sq->sq.sqe_stype = NIX_STYPE_STF;
726 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
727 sq->sq.sqe_stype = NIX_STYPE_STP;
729 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
730 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
731 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
732 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
733 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
735 /* Many to one reduction */
736 sq->sq.qint_idx = txq->sq % dev->qints;
738 return otx2_mbox_process(mbox);
742 nix_sq_uninit(struct otx2_eth_txq *txq)
744 struct otx2_eth_dev *dev = txq->dev;
745 struct otx2_mbox *mbox = dev->mbox;
746 struct ndc_sync_op *ndc_req;
747 struct nix_aq_enq_rsp *rsp;
748 struct nix_aq_enq_req *aq;
749 uint16_t sqes_per_sqb;
753 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
755 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
757 aq->ctype = NIX_AQ_CTYPE_SQ;
758 aq->op = NIX_AQ_INSTOP_READ;
760 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
764 /* Check if sq is already cleaned up */
769 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
771 aq->ctype = NIX_AQ_CTYPE_SQ;
772 aq->op = NIX_AQ_INSTOP_WRITE;
774 aq->sq_mask.ena = ~aq->sq_mask.ena;
777 rc = otx2_mbox_process(mbox);
781 /* Read SQ and free sqb's */
782 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
784 aq->ctype = NIX_AQ_CTYPE_SQ;
785 aq->op = NIX_AQ_INSTOP_READ;
787 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
792 otx2_err("SQ has pending sqe's");
794 count = aq->sq.sqb_count;
795 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
796 /* Free SQB's that are used */
797 sqb_buf = (void *)rsp->sq.head_sqb;
801 next_sqb = *(void **)((uintptr_t)sqb_buf + (uint32_t)
802 ((sqes_per_sqb - 1) *
803 nix_sq_max_sqe_sz(txq)));
804 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
810 /* Free next to use sqb */
811 if (rsp->sq.next_sqb)
812 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
815 /* Sync NDC-NIX-TX for LF */
816 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
817 ndc_req->nix_lf_tx_sync = 1;
818 rc = otx2_mbox_process(mbox);
820 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
826 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
828 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
829 struct npa_aq_enq_req *aura_req;
831 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
832 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
833 aura_req->ctype = NPA_AQ_CTYPE_AURA;
834 aura_req->op = NPA_AQ_INSTOP_WRITE;
836 aura_req->aura.limit = nb_sqb_bufs;
837 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
839 return otx2_mbox_process(npa_lf->mbox);
843 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
845 struct otx2_eth_dev *dev = txq->dev;
846 uint16_t sqes_per_sqb, nb_sqb_bufs;
847 char name[RTE_MEMPOOL_NAMESIZE];
848 struct rte_mempool_objsz sz;
849 struct npa_aura_s *aura;
850 uint32_t tmp, blk_sz;
852 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
853 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
854 blk_sz = dev->sqb_size;
856 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
857 sqes_per_sqb = (dev->sqb_size / 8) / 16;
859 sqes_per_sqb = (dev->sqb_size / 8) / 8;
861 nb_sqb_bufs = nb_desc / sqes_per_sqb;
862 /* Clamp up to devarg passed SQB count */
863 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_DEF_SQB,
864 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
866 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
868 MEMPOOL_F_NO_SPREAD);
869 txq->nb_sqb_bufs = nb_sqb_bufs;
870 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
871 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
872 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
873 txq->nb_sqb_bufs_adj =
874 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
876 if (txq->sqb_pool == NULL) {
877 otx2_err("Failed to allocate sqe mempool");
881 memset(aura, 0, sizeof(*aura));
883 aura->fc_addr = txq->fc_iova;
884 aura->fc_hyst_bits = 0; /* Store count on all updates */
885 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
886 otx2_err("Failed to set ops for sqe mempool");
889 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
890 otx2_err("Failed to populate sqe mempool");
894 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
895 if (dev->sqb_size != sz.elt_size) {
896 otx2_err("sqe pool block size is not expected %d != %d",
901 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
909 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
911 struct nix_send_ext_s *send_hdr_ext;
912 struct nix_send_hdr_s *send_hdr;
913 struct nix_send_mem_s *send_mem;
914 union nix_send_sg_s *sg;
916 /* Initialize the fields based on basic single segment packet */
917 memset(&txq->cmd, 0, sizeof(txq->cmd));
919 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
920 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
921 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
922 send_hdr->w0.sizem1 = 2;
924 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
925 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
926 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
927 /* Default: one seg packet would have:
928 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
931 send_hdr->w0.sizem1 = 3;
932 send_hdr_ext->w0.tstmp = 1;
934 /* To calculate the offset for send_mem,
935 * send_hdr->w0.sizem1 * 2
937 send_mem = (struct nix_send_mem_s *)(txq->cmd +
938 (send_hdr->w0.sizem1 << 1));
939 send_mem->subdc = NIX_SUBDC_MEM;
940 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
941 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
943 sg = (union nix_send_sg_s *)&txq->cmd[4];
945 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
946 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
947 send_hdr->w0.sizem1 = 1;
948 sg = (union nix_send_sg_s *)&txq->cmd[2];
951 send_hdr->w0.sq = txq->sq;
952 sg->subdc = NIX_SUBDC_SG;
954 sg->ld_type = NIX_SENDLDTYPE_LDD;
960 otx2_nix_tx_queue_release(void *_txq)
962 struct otx2_eth_txq *txq = _txq;
963 struct rte_eth_dev *eth_dev;
968 eth_dev = txq->dev->eth_dev;
970 otx2_nix_dbg("Releasing txq %u", txq->sq);
972 /* Flush and disable tm */
973 otx2_nix_tm_sw_xoff(txq, eth_dev->data->dev_started);
975 /* Free sqb's and disable sq */
979 rte_mempool_free(txq->sqb_pool);
980 txq->sqb_pool = NULL;
987 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
988 uint16_t nb_desc, unsigned int socket_id,
989 const struct rte_eth_txconf *tx_conf)
991 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
992 const struct rte_memzone *fc;
993 struct otx2_eth_txq *txq;
999 /* Compile time check to make sure all fast path elements in a CL */
1000 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
1002 if (tx_conf->tx_deferred_start) {
1003 otx2_err("Tx deferred start is not supported");
1007 /* Free memory prior to re-allocation if needed. */
1008 if (eth_dev->data->tx_queues[sq] != NULL) {
1009 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
1010 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
1011 eth_dev->data->tx_queues[sq] = NULL;
1014 /* Find the expected offloads for this queue */
1015 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
1017 /* Allocating tx queue data structure */
1018 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
1019 OTX2_ALIGN, socket_id);
1021 otx2_err("Failed to alloc txq=%d", sq);
1027 txq->sqb_pool = NULL;
1028 txq->offloads = offloads;
1029 dev->tx_offloads |= offloads;
1032 * Allocate memory for flow control updates from HW.
1033 * Alloc one cache line, so that fits all FC_STYPE modes.
1035 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
1036 OTX2_ALIGN + sizeof(struct npa_aura_s),
1037 OTX2_ALIGN, dev->node);
1039 otx2_err("Failed to allocate mem for fcmem");
1043 txq->fc_iova = fc->iova;
1044 txq->fc_mem = fc->addr;
1046 /* Initialize the aura sqb pool */
1047 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
1049 otx2_err("Failed to alloc sqe pool rc=%d", rc);
1053 /* Initialize the SQ */
1054 rc = nix_sq_init(txq);
1056 otx2_err("Failed to init sq=%d context", sq);
1060 txq->fc_cache_pkts = 0;
1061 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
1062 /* Evenly distribute LMT slot for each sq */
1063 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
1065 txq->qconf.socket_id = socket_id;
1066 txq->qconf.nb_desc = nb_desc;
1067 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
1069 otx2_nix_form_default_desc(txq);
1071 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
1072 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
1073 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
1074 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
1075 eth_dev->data->tx_queues[sq] = txq;
1076 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
1080 otx2_nix_tx_queue_release(txq);
1086 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1088 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1089 struct otx2_eth_qconf *tx_qconf = NULL;
1090 struct otx2_eth_qconf *rx_qconf = NULL;
1091 struct otx2_eth_txq **txq;
1092 struct otx2_eth_rxq **rxq;
1093 int i, nb_rxq, nb_txq;
1095 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1096 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1098 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1099 if (tx_qconf == NULL) {
1100 otx2_err("Failed to allocate memory for tx_qconf");
1104 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1105 if (rx_qconf == NULL) {
1106 otx2_err("Failed to allocate memory for rx_qconf");
1110 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1111 for (i = 0; i < nb_txq; i++) {
1112 if (txq[i] == NULL) {
1113 otx2_err("txq[%d] is already released", i);
1116 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1117 otx2_nix_tx_queue_release(txq[i]);
1118 eth_dev->data->tx_queues[i] = NULL;
1121 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1122 for (i = 0; i < nb_rxq; i++) {
1123 if (rxq[i] == NULL) {
1124 otx2_err("rxq[%d] is already released", i);
1127 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1128 otx2_nix_rx_queue_release(rxq[i]);
1129 eth_dev->data->rx_queues[i] = NULL;
1132 dev->tx_qconf = tx_qconf;
1133 dev->rx_qconf = rx_qconf;
1146 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1148 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1149 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1150 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1151 struct otx2_eth_txq **txq;
1152 struct otx2_eth_rxq **rxq;
1153 int rc, i, nb_rxq, nb_txq;
1155 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1156 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1159 /* Setup tx & rx queues with previous configuration so
1160 * that the queues can be functional in cases like ports
1161 * are started without re configuring queues.
1163 * Usual re config sequence is like below:
1164 * port_configure() {
1169 * queue_configure() {
1176 * In some application's control path, queue_configure() would
1177 * NOT be invoked for TXQs/RXQs in port_configure().
1178 * In such cases, queues can be functional after start as the
1179 * queues are already setup in port_configure().
1181 for (i = 0; i < nb_txq; i++) {
1182 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1183 tx_qconf[i].socket_id,
1184 &tx_qconf[i].conf.tx);
1186 otx2_err("Failed to setup tx queue rc=%d", rc);
1187 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1188 for (i -= 1; i >= 0; i--)
1189 otx2_nix_tx_queue_release(txq[i]);
1194 free(tx_qconf); tx_qconf = NULL;
1196 for (i = 0; i < nb_rxq; i++) {
1197 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1198 rx_qconf[i].socket_id,
1199 &rx_qconf[i].conf.rx,
1200 rx_qconf[i].mempool);
1202 otx2_err("Failed to setup rx queue rc=%d", rc);
1203 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1204 for (i -= 1; i >= 0; i--)
1205 otx2_nix_rx_queue_release(rxq[i]);
1206 goto release_tx_queues;
1210 free(rx_qconf); rx_qconf = NULL;
1215 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1216 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1217 otx2_nix_tx_queue_release(txq[i]);
1228 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1230 RTE_SET_USED(queue);
1231 RTE_SET_USED(mbufs);
1238 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1240 /* These dummy functions are required for supporting
1241 * some applications which reconfigure queues without
1242 * stopping tx burst and rx burst threads(eg kni app)
1243 * When the queues context is saved, txq/rxqs are released
1244 * which caused app crash since rx/tx burst is still
1245 * on different lcores
1247 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1248 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1253 nix_lso_tcp(struct nix_lso_format_cfg *req, bool v4)
1255 volatile struct nix_lso_format *field;
1257 /* Format works only with TCP packet marked by OL3/OL4 */
1258 field = (volatile struct nix_lso_format *)&req->fields[0];
1259 req->field_mask = NIX_LSO_FIELD_MASK;
1260 /* Outer IPv4/IPv6 */
1261 field->layer = NIX_TXLAYER_OL3;
1262 field->offset = v4 ? 2 : 4;
1263 field->sizem1 = 1; /* 2B */
1264 field->alg = NIX_LSOALG_ADD_PAYLEN;
1268 field->layer = NIX_TXLAYER_OL3;
1271 /* Incremented linearly per segment */
1272 field->alg = NIX_LSOALG_ADD_SEGNUM;
1276 /* TCP sequence number update */
1277 field->layer = NIX_TXLAYER_OL4;
1279 field->sizem1 = 3; /* 4 bytes */
1280 field->alg = NIX_LSOALG_ADD_OFFSET;
1282 /* TCP flags field */
1283 field->layer = NIX_TXLAYER_OL4;
1286 field->alg = NIX_LSOALG_TCP_FLAGS;
1291 nix_lso_udp_tun_tcp(struct nix_lso_format_cfg *req,
1292 bool outer_v4, bool inner_v4)
1294 volatile struct nix_lso_format *field;
1296 field = (volatile struct nix_lso_format *)&req->fields[0];
1297 req->field_mask = NIX_LSO_FIELD_MASK;
1298 /* Outer IPv4/IPv6 len */
1299 field->layer = NIX_TXLAYER_OL3;
1300 field->offset = outer_v4 ? 2 : 4;
1301 field->sizem1 = 1; /* 2B */
1302 field->alg = NIX_LSOALG_ADD_PAYLEN;
1306 field->layer = NIX_TXLAYER_OL3;
1309 /* Incremented linearly per segment */
1310 field->alg = NIX_LSOALG_ADD_SEGNUM;
1314 /* Outer UDP length */
1315 field->layer = NIX_TXLAYER_OL4;
1318 field->alg = NIX_LSOALG_ADD_PAYLEN;
1321 /* Inner IPv4/IPv6 */
1322 field->layer = NIX_TXLAYER_IL3;
1323 field->offset = inner_v4 ? 2 : 4;
1324 field->sizem1 = 1; /* 2B */
1325 field->alg = NIX_LSOALG_ADD_PAYLEN;
1329 field->layer = NIX_TXLAYER_IL3;
1332 /* Incremented linearly per segment */
1333 field->alg = NIX_LSOALG_ADD_SEGNUM;
1337 /* TCP sequence number update */
1338 field->layer = NIX_TXLAYER_IL4;
1340 field->sizem1 = 3; /* 4 bytes */
1341 field->alg = NIX_LSOALG_ADD_OFFSET;
1344 /* TCP flags field */
1345 field->layer = NIX_TXLAYER_IL4;
1348 field->alg = NIX_LSOALG_TCP_FLAGS;
1353 nix_lso_tun_tcp(struct nix_lso_format_cfg *req,
1354 bool outer_v4, bool inner_v4)
1356 volatile struct nix_lso_format *field;
1358 field = (volatile struct nix_lso_format *)&req->fields[0];
1359 req->field_mask = NIX_LSO_FIELD_MASK;
1360 /* Outer IPv4/IPv6 len */
1361 field->layer = NIX_TXLAYER_OL3;
1362 field->offset = outer_v4 ? 2 : 4;
1363 field->sizem1 = 1; /* 2B */
1364 field->alg = NIX_LSOALG_ADD_PAYLEN;
1368 field->layer = NIX_TXLAYER_OL3;
1371 /* Incremented linearly per segment */
1372 field->alg = NIX_LSOALG_ADD_SEGNUM;
1376 /* Inner IPv4/IPv6 */
1377 field->layer = NIX_TXLAYER_IL3;
1378 field->offset = inner_v4 ? 2 : 4;
1379 field->sizem1 = 1; /* 2B */
1380 field->alg = NIX_LSOALG_ADD_PAYLEN;
1384 field->layer = NIX_TXLAYER_IL3;
1387 /* Incremented linearly per segment */
1388 field->alg = NIX_LSOALG_ADD_SEGNUM;
1392 /* TCP sequence number update */
1393 field->layer = NIX_TXLAYER_IL4;
1395 field->sizem1 = 3; /* 4 bytes */
1396 field->alg = NIX_LSOALG_ADD_OFFSET;
1399 /* TCP flags field */
1400 field->layer = NIX_TXLAYER_IL4;
1403 field->alg = NIX_LSOALG_TCP_FLAGS;
1408 nix_setup_lso_formats(struct otx2_eth_dev *dev)
1410 struct otx2_mbox *mbox = dev->mbox;
1411 struct nix_lso_format_cfg_rsp *rsp;
1412 struct nix_lso_format_cfg *req;
1416 /* Skip if TSO was not requested */
1417 if (!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F))
1422 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1423 nix_lso_tcp(req, true);
1424 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1428 base = rsp->lso_format_idx;
1429 if (base != NIX_LSO_FORMAT_IDX_TSOV4)
1431 dev->lso_base_idx = base;
1432 otx2_nix_dbg("tcpv4 lso fmt=%u", base);
1438 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1439 nix_lso_tcp(req, false);
1440 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1444 if (rsp->lso_format_idx != base + 1)
1446 otx2_nix_dbg("tcpv6 lso fmt=%u\n", base + 1);
1449 * IPv4/UDP/TUN HDR/IPv4/TCP LSO
1451 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1452 nix_lso_udp_tun_tcp(req, true, true);
1453 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1457 if (rsp->lso_format_idx != base + 2)
1459 otx2_nix_dbg("udp tun v4v4 fmt=%u\n", base + 2);
1462 * IPv4/UDP/TUN HDR/IPv6/TCP LSO
1464 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1465 nix_lso_udp_tun_tcp(req, true, false);
1466 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1470 if (rsp->lso_format_idx != base + 3)
1472 otx2_nix_dbg("udp tun v4v6 fmt=%u\n", base + 3);
1475 * IPv6/UDP/TUN HDR/IPv4/TCP LSO
1477 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1478 nix_lso_udp_tun_tcp(req, false, true);
1479 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1483 if (rsp->lso_format_idx != base + 4)
1485 otx2_nix_dbg("udp tun v6v4 fmt=%u\n", base + 4);
1488 * IPv6/UDP/TUN HDR/IPv6/TCP LSO
1490 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1491 nix_lso_udp_tun_tcp(req, false, false);
1492 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1495 if (rsp->lso_format_idx != base + 5)
1497 otx2_nix_dbg("udp tun v6v6 fmt=%u\n", base + 5);
1500 * IPv4/TUN HDR/IPv4/TCP LSO
1502 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1503 nix_lso_tun_tcp(req, true, true);
1504 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1508 if (rsp->lso_format_idx != base + 6)
1510 otx2_nix_dbg("tun v4v4 fmt=%u\n", base + 6);
1513 * IPv4/TUN HDR/IPv6/TCP LSO
1515 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1516 nix_lso_tun_tcp(req, true, false);
1517 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1521 if (rsp->lso_format_idx != base + 7)
1523 otx2_nix_dbg("tun v4v6 fmt=%u\n", base + 7);
1526 * IPv6/TUN HDR/IPv4/TCP LSO
1528 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1529 nix_lso_tun_tcp(req, false, true);
1530 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1534 if (rsp->lso_format_idx != base + 8)
1536 otx2_nix_dbg("tun v6v4 fmt=%u\n", base + 8);
1539 * IPv6/TUN HDR/IPv6/TCP LSO
1541 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1542 nix_lso_tun_tcp(req, false, false);
1543 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1546 if (rsp->lso_format_idx != base + 9)
1548 otx2_nix_dbg("tun v6v6 fmt=%u\n", base + 9);
1553 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1555 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1556 struct rte_eth_dev_data *data = eth_dev->data;
1557 struct rte_eth_conf *conf = &data->dev_conf;
1558 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1559 struct rte_eth_txmode *txmode = &conf->txmode;
1560 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1561 struct rte_ether_addr *ea;
1562 uint8_t nb_rxq, nb_txq;
1568 if (rte_eal_has_hugepages() == 0) {
1569 otx2_err("Huge page is not configured");
1570 goto fail_configure;
1573 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1574 otx2_err("Setting link speed/duplex not supported");
1575 goto fail_configure;
1578 if (conf->dcb_capability_en == 1) {
1579 otx2_err("dcb enable is not supported");
1580 goto fail_configure;
1583 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1584 otx2_err("Flow director is not supported");
1585 goto fail_configure;
1588 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1589 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1590 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1591 goto fail_configure;
1594 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1595 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1596 goto fail_configure;
1599 if (otx2_dev_is_Ax(dev) &&
1600 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1601 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1602 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1603 otx2_err("Outer IP and SCTP checksum unsupported");
1604 goto fail_configure;
1607 /* Free the resources allocated from the previous configure */
1608 if (dev->configured == 1) {
1609 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1610 otx2_nix_vlan_fini(eth_dev);
1611 otx2_nix_mc_addr_list_uninstall(eth_dev);
1612 otx2_flow_free_all_resources(dev);
1613 oxt2_nix_unregister_queue_irqs(eth_dev);
1614 if (eth_dev->data->dev_conf.intr_conf.rxq)
1615 oxt2_nix_unregister_cq_irqs(eth_dev);
1616 nix_set_nop_rxtx_function(eth_dev);
1617 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1619 goto fail_configure;
1620 otx2_nix_tm_fini(eth_dev);
1624 dev->rx_offloads = rxmode->offloads;
1625 dev->tx_offloads = txmode->offloads;
1626 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1627 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1628 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1630 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1631 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1633 /* Alloc a nix lf */
1634 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1636 otx2_err("Failed to init nix_lf rc=%d", rc);
1640 rc = nix_lf_switch_header_type_enable(dev);
1642 otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
1646 rc = nix_setup_lso_formats(dev);
1648 otx2_err("failed to setup nix lso format fields, rc=%d", rc);
1653 rc = otx2_nix_rss_config(eth_dev);
1655 otx2_err("Failed to configure rss rc=%d", rc);
1659 /* Init the default TM scheduler hierarchy */
1660 rc = otx2_nix_tm_init_default(eth_dev);
1662 otx2_err("Failed to init traffic manager rc=%d", rc);
1666 rc = otx2_nix_vlan_offload_init(eth_dev);
1668 otx2_err("Failed to init vlan offload rc=%d", rc);
1672 /* Register queue IRQs */
1673 rc = oxt2_nix_register_queue_irqs(eth_dev);
1675 otx2_err("Failed to register queue interrupts rc=%d", rc);
1679 /* Register cq IRQs */
1680 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1681 if (eth_dev->data->nb_rx_queues > dev->cints) {
1682 otx2_err("Rx interrupt cannot be enabled, rxq > %d",
1686 /* Rx interrupt feature cannot work with vector mode because,
1687 * vector mode doesn't process packets unless min 4 pkts are
1688 * received, while cq interrupts are generated even for 1 pkt
1691 dev->scalar_ena = true;
1693 rc = oxt2_nix_register_cq_irqs(eth_dev);
1695 otx2_err("Failed to register CQ interrupts rc=%d", rc);
1700 /* Configure loop back mode */
1701 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1703 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1707 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1709 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1713 rc = otx2_nix_mc_addr_list_install(eth_dev);
1715 otx2_err("Failed to install mc address list rc=%d", rc);
1720 * Restore queue config when reconfigure followed by
1721 * reconfigure and no queue configure invoked from application case.
1723 if (dev->configured == 1) {
1724 rc = nix_restore_queue_cfg(eth_dev);
1726 goto uninstall_mc_list;
1729 /* Update the mac address */
1730 ea = eth_dev->data->mac_addrs;
1731 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1732 if (rte_is_zero_ether_addr(ea))
1733 rte_eth_random_addr((uint8_t *)ea);
1735 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1737 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1738 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1739 " rx_flags=0x%x tx_flags=0x%x",
1740 eth_dev->data->port_id, ea_fmt, nb_rxq,
1741 nb_txq, dev->rx_offloads, dev->tx_offloads,
1742 dev->rx_offload_flags, dev->tx_offload_flags);
1745 dev->configured = 1;
1746 dev->configured_nb_rx_qs = data->nb_rx_queues;
1747 dev->configured_nb_tx_qs = data->nb_tx_queues;
1751 otx2_nix_mc_addr_list_uninstall(eth_dev);
1753 oxt2_nix_unregister_cq_irqs(eth_dev);
1755 oxt2_nix_unregister_queue_irqs(eth_dev);
1757 otx2_nix_vlan_fini(eth_dev);
1759 otx2_nix_tm_fini(eth_dev);
1763 dev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);
1764 dev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);
1766 dev->configured = 0;
1771 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1773 struct rte_eth_dev_data *data = eth_dev->data;
1774 struct otx2_eth_txq *txq;
1777 txq = eth_dev->data->tx_queues[qidx];
1779 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1782 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1784 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1789 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1796 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1798 struct rte_eth_dev_data *data = eth_dev->data;
1799 struct otx2_eth_txq *txq;
1802 txq = eth_dev->data->tx_queues[qidx];
1804 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1807 txq->fc_cache_pkts = 0;
1809 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1811 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1816 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1823 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1825 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1826 struct rte_eth_dev_data *data = eth_dev->data;
1829 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1832 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1834 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1838 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1845 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1847 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1848 struct rte_eth_dev_data *data = eth_dev->data;
1851 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1854 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1856 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1860 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1867 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
1869 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1870 struct rte_mbuf *rx_pkts[32];
1871 struct otx2_eth_rxq *rxq;
1872 int count, i, j, rc;
1874 nix_cgx_stop_link_event(dev);
1875 npc_rx_disable(dev);
1877 /* Stop rx queues and free up pkts pending */
1878 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1879 rc = otx2_nix_rx_queue_stop(eth_dev, i);
1883 rxq = eth_dev->data->rx_queues[i];
1884 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1886 for (j = 0; j < count; j++)
1887 rte_pktmbuf_free(rx_pkts[j]);
1888 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1892 /* Stop tx queues */
1893 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1894 otx2_nix_tx_queue_stop(eth_dev, i);
1898 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
1900 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1903 if (eth_dev->data->nb_rx_queues != 0) {
1904 rc = otx2_nix_recalc_mtu(eth_dev);
1909 /* Start rx queues */
1910 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1911 rc = otx2_nix_rx_queue_start(eth_dev, i);
1916 /* Start tx queues */
1917 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1918 rc = otx2_nix_tx_queue_start(eth_dev, i);
1923 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
1925 otx2_err("Failed to update flow ctrl mode %d", rc);
1929 /* Enable PTP if it was requested by the app or if it is already
1930 * enabled in PF owning this VF
1932 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
1933 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
1934 otx2_ethdev_is_ptp_en(dev))
1935 otx2_nix_timesync_enable(eth_dev);
1937 otx2_nix_timesync_disable(eth_dev);
1939 rc = npc_rx_enable(dev);
1941 otx2_err("Failed to enable NPC rx %d", rc);
1945 otx2_nix_toggle_flag_link_cfg(dev, true);
1947 rc = nix_cgx_start_link_event(dev);
1949 otx2_err("Failed to start cgx link event %d", rc);
1953 otx2_nix_toggle_flag_link_cfg(dev, false);
1954 otx2_eth_set_tx_function(eth_dev);
1955 otx2_eth_set_rx_function(eth_dev);
1960 npc_rx_disable(dev);
1961 otx2_nix_toggle_flag_link_cfg(dev, false);
1965 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
1966 static void otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
1968 /* Initialize and register driver with DPDK Application */
1969 static const struct eth_dev_ops otx2_eth_dev_ops = {
1970 .dev_infos_get = otx2_nix_info_get,
1971 .dev_configure = otx2_nix_configure,
1972 .link_update = otx2_nix_link_update,
1973 .tx_queue_setup = otx2_nix_tx_queue_setup,
1974 .tx_queue_release = otx2_nix_tx_queue_release,
1975 .rx_queue_setup = otx2_nix_rx_queue_setup,
1976 .rx_queue_release = otx2_nix_rx_queue_release,
1977 .dev_start = otx2_nix_dev_start,
1978 .dev_stop = otx2_nix_dev_stop,
1979 .dev_close = otx2_nix_dev_close,
1980 .tx_queue_start = otx2_nix_tx_queue_start,
1981 .tx_queue_stop = otx2_nix_tx_queue_stop,
1982 .rx_queue_start = otx2_nix_rx_queue_start,
1983 .rx_queue_stop = otx2_nix_rx_queue_stop,
1984 .dev_set_link_up = otx2_nix_dev_set_link_up,
1985 .dev_set_link_down = otx2_nix_dev_set_link_down,
1986 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
1987 .dev_reset = otx2_nix_dev_reset,
1988 .stats_get = otx2_nix_dev_stats_get,
1989 .stats_reset = otx2_nix_dev_stats_reset,
1990 .get_reg = otx2_nix_dev_get_reg,
1991 .mtu_set = otx2_nix_mtu_set,
1992 .mac_addr_add = otx2_nix_mac_addr_add,
1993 .mac_addr_remove = otx2_nix_mac_addr_del,
1994 .mac_addr_set = otx2_nix_mac_addr_set,
1995 .set_mc_addr_list = otx2_nix_set_mc_addr_list,
1996 .promiscuous_enable = otx2_nix_promisc_enable,
1997 .promiscuous_disable = otx2_nix_promisc_disable,
1998 .allmulticast_enable = otx2_nix_allmulticast_enable,
1999 .allmulticast_disable = otx2_nix_allmulticast_disable,
2000 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
2001 .reta_update = otx2_nix_dev_reta_update,
2002 .reta_query = otx2_nix_dev_reta_query,
2003 .rss_hash_update = otx2_nix_rss_hash_update,
2004 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
2005 .xstats_get = otx2_nix_xstats_get,
2006 .xstats_get_names = otx2_nix_xstats_get_names,
2007 .xstats_reset = otx2_nix_xstats_reset,
2008 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
2009 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
2010 .rxq_info_get = otx2_nix_rxq_info_get,
2011 .txq_info_get = otx2_nix_txq_info_get,
2012 .rx_burst_mode_get = otx2_rx_burst_mode_get,
2013 .tx_burst_mode_get = otx2_tx_burst_mode_get,
2014 .rx_queue_count = otx2_nix_rx_queue_count,
2015 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
2016 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
2017 .tx_descriptor_status = otx2_nix_tx_descriptor_status,
2018 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
2019 .pool_ops_supported = otx2_nix_pool_ops_supported,
2020 .filter_ctrl = otx2_nix_dev_filter_ctrl,
2021 .get_module_info = otx2_nix_get_module_info,
2022 .get_module_eeprom = otx2_nix_get_module_eeprom,
2023 .fw_version_get = otx2_nix_fw_version_get,
2024 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
2025 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
2026 .timesync_enable = otx2_nix_timesync_enable,
2027 .timesync_disable = otx2_nix_timesync_disable,
2028 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
2029 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
2030 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
2031 .timesync_read_time = otx2_nix_timesync_read_time,
2032 .timesync_write_time = otx2_nix_timesync_write_time,
2033 .vlan_offload_set = otx2_nix_vlan_offload_set,
2034 .vlan_filter_set = otx2_nix_vlan_filter_set,
2035 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
2036 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
2037 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
2038 .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
2039 .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
2040 .read_clock = otx2_nix_read_clock,
2044 nix_lf_attach(struct otx2_eth_dev *dev)
2046 struct otx2_mbox *mbox = dev->mbox;
2047 struct rsrc_attach_req *req;
2049 /* Attach NIX(lf) */
2050 req = otx2_mbox_alloc_msg_attach_resources(mbox);
2054 return otx2_mbox_process(mbox);
2058 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
2060 struct otx2_mbox *mbox = dev->mbox;
2061 struct msix_offset_rsp *msix_rsp;
2064 /* Get NPA and NIX MSIX vector offsets */
2065 otx2_mbox_alloc_msg_msix_offset(mbox);
2067 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
2069 dev->nix_msixoff = msix_rsp->nix_msixoff;
2075 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
2077 struct rsrc_detach_req *req;
2079 req = otx2_mbox_alloc_msg_detach_resources(mbox);
2081 /* Detach all except npa lf */
2082 req->partial = true;
2089 return otx2_mbox_process(mbox);
2093 otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
2095 if (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||
2096 pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2102 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
2104 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2105 struct rte_pci_device *pci_dev;
2106 int rc, max_entries;
2108 eth_dev->dev_ops = &otx2_eth_dev_ops;
2110 /* For secondary processes, the primary has done all the work */
2111 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2112 /* Setup callbacks for secondary process */
2113 otx2_eth_set_tx_function(eth_dev);
2114 otx2_eth_set_rx_function(eth_dev);
2118 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2120 rte_eth_copy_pci_info(eth_dev, pci_dev);
2121 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2123 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
2124 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
2125 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
2127 /* Parse devargs string */
2128 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
2130 otx2_err("Failed to parse devargs rc=%d", rc);
2134 if (!dev->mbox_active) {
2135 /* Initialize the base otx2_dev object
2136 * only if already present
2138 rc = otx2_dev_init(pci_dev, dev);
2140 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
2144 if (otx2_eth_dev_is_sdp(pci_dev))
2145 dev->sdp_link = true;
2147 dev->sdp_link = false;
2148 /* Device generic callbacks */
2149 dev->ops = &otx2_dev_ops;
2150 dev->eth_dev = eth_dev;
2152 /* Grab the NPA LF if required */
2153 rc = otx2_npa_lf_init(pci_dev, dev);
2155 goto otx2_dev_uninit;
2157 dev->configured = 0;
2158 dev->drv_inited = true;
2159 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
2160 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
2163 rc = nix_lf_attach(dev);
2165 goto otx2_npa_uninit;
2167 /* Get NIX MSIX offset */
2168 rc = nix_lf_get_msix_offset(dev);
2170 goto otx2_npa_uninit;
2172 /* Register LF irq handlers */
2173 rc = otx2_nix_register_irqs(eth_dev);
2177 /* Get maximum number of supported MAC entries */
2178 max_entries = otx2_cgx_mac_max_entries_get(dev);
2179 if (max_entries < 0) {
2180 otx2_err("Failed to get max entries for mac addr");
2182 goto unregister_irq;
2185 /* For VFs, returned max_entries will be 0. But to keep default MAC
2186 * address, one entry must be allocated. So setting up to 1.
2188 if (max_entries == 0)
2191 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
2192 RTE_ETHER_ADDR_LEN, 0);
2193 if (eth_dev->data->mac_addrs == NULL) {
2194 otx2_err("Failed to allocate memory for mac addr");
2196 goto unregister_irq;
2199 dev->max_mac_entries = max_entries;
2201 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
2203 goto free_mac_addrs;
2205 /* Update the mac address */
2206 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
2208 /* Also sync same MAC address to CGX table */
2209 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
2211 /* Initialize the tm data structures */
2212 otx2_nix_tm_conf_init(eth_dev);
2214 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
2215 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
2217 if (otx2_dev_is_96xx_A0(dev) ||
2218 otx2_dev_is_95xx_Ax(dev)) {
2219 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
2220 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
2223 /* Initialize rte-flow */
2224 rc = otx2_flow_init(dev);
2226 goto free_mac_addrs;
2228 otx2_nix_mc_filter_init(dev);
2230 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
2231 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
2232 eth_dev->data->port_id, dev->pf, dev->vf,
2233 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
2234 dev->rx_offload_capa, dev->tx_offload_capa);
2238 rte_free(eth_dev->data->mac_addrs);
2240 otx2_nix_unregister_irqs(eth_dev);
2242 otx2_eth_dev_lf_detach(dev->mbox);
2246 otx2_dev_fini(pci_dev, dev);
2248 otx2_err("Failed to init nix eth_dev rc=%d", rc);
2253 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
2255 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2256 struct rte_pci_device *pci_dev;
2259 /* Nothing to be done for secondary processes */
2260 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2263 /* Clear the flag since we are closing down */
2264 dev->configured = 0;
2266 /* Disable nix bpid config */
2267 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
2269 npc_rx_disable(dev);
2271 /* Disable vlan offloads */
2272 otx2_nix_vlan_fini(eth_dev);
2274 /* Disable other rte_flow entries */
2275 otx2_flow_fini(dev);
2277 /* Free multicast filter list */
2278 otx2_nix_mc_filter_fini(dev);
2280 /* Disable PTP if already enabled */
2281 if (otx2_ethdev_is_ptp_en(dev))
2282 otx2_nix_timesync_disable(eth_dev);
2284 nix_cgx_stop_link_event(dev);
2287 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
2288 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
2289 eth_dev->data->tx_queues[i] = NULL;
2291 eth_dev->data->nb_tx_queues = 0;
2293 /* Free up RQ's and CQ's */
2294 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2295 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
2296 eth_dev->data->rx_queues[i] = NULL;
2298 eth_dev->data->nb_rx_queues = 0;
2300 /* Free tm resources */
2301 rc = otx2_nix_tm_fini(eth_dev);
2303 otx2_err("Failed to cleanup tm, rc=%d", rc);
2305 /* Unregister queue irqs */
2306 oxt2_nix_unregister_queue_irqs(eth_dev);
2308 /* Unregister cq irqs */
2309 if (eth_dev->data->dev_conf.intr_conf.rxq)
2310 oxt2_nix_unregister_cq_irqs(eth_dev);
2312 rc = nix_lf_free(dev);
2314 otx2_err("Failed to free nix lf, rc=%d", rc);
2316 rc = otx2_npa_lf_fini();
2318 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
2320 rte_free(eth_dev->data->mac_addrs);
2321 eth_dev->data->mac_addrs = NULL;
2322 dev->drv_inited = false;
2324 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2325 otx2_nix_unregister_irqs(eth_dev);
2327 rc = otx2_eth_dev_lf_detach(dev->mbox);
2329 otx2_err("Failed to detach resources, rc=%d", rc);
2331 /* Check if mbox close is needed */
2335 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
2336 /* Will be freed later by PMD */
2337 eth_dev->data->dev_private = NULL;
2341 otx2_dev_fini(pci_dev, dev);
2346 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
2348 otx2_eth_dev_uninit(eth_dev, true);
2352 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
2356 rc = otx2_eth_dev_uninit(eth_dev, false);
2360 return otx2_eth_dev_init(eth_dev);
2364 nix_remove(struct rte_pci_device *pci_dev)
2366 struct rte_eth_dev *eth_dev;
2367 struct otx2_idev_cfg *idev;
2368 struct otx2_dev *otx2_dev;
2371 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
2373 /* Cleanup eth dev */
2374 rc = otx2_eth_dev_uninit(eth_dev, true);
2378 rte_eth_dev_pci_release(eth_dev);
2381 /* Nothing to be done for secondary processes */
2382 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2385 /* Check for common resources */
2386 idev = otx2_intra_dev_get_cfg();
2387 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
2390 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
2392 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
2395 /* Safe to cleanup mbox as no more users */
2396 otx2_dev_fini(pci_dev, otx2_dev);
2401 otx2_info("%s: common resource in use by other devices", pci_dev->name);
2406 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
2410 RTE_SET_USED(pci_drv);
2412 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
2415 /* On error on secondary, recheck if port exists in primary or
2416 * in mid of detach state.
2418 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
2419 if (!rte_eth_dev_allocated(pci_dev->device.name))
2424 static const struct rte_pci_id pci_nix_map[] = {
2426 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
2429 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
2432 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2433 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
2436 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2437 PCI_DEVID_OCTEONTX2_RVU_SDP_PF)
2440 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2441 PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2448 static struct rte_pci_driver pci_nix = {
2449 .id_table = pci_nix_map,
2450 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
2451 RTE_PCI_DRV_INTR_LSC,
2453 .remove = nix_remove,
2456 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
2457 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
2458 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");