1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_ethdev_pci.h>
9 #include <rte_malloc.h>
11 #include <rte_mbuf_pool_ops.h>
12 #include <rte_mempool.h>
14 #include "otx2_ethdev.h"
16 static inline uint64_t
17 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
19 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
21 if (otx2_dev_is_vf(dev))
22 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
27 static inline uint64_t
28 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
30 uint64_t capa = NIX_TX_OFFLOAD_CAPA;
32 /* TSO not supported for earlier chip revisions */
33 if (otx2_dev_is_96xx_A0(dev) || otx2_dev_is_95xx_Ax(dev))
34 capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
35 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
36 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
37 DEV_TX_OFFLOAD_GRE_TNL_TSO);
41 static const struct otx2_dev_ops otx2_dev_ops = {
42 .link_status_update = otx2_eth_dev_link_status_update,
43 .ptp_info_update = otx2_eth_dev_ptp_info_update
47 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
49 struct otx2_mbox *mbox = dev->mbox;
50 struct nix_lf_alloc_req *req;
51 struct nix_lf_alloc_rsp *rsp;
54 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
58 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
59 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
60 req->xqe_sz = NIX_XQESZ_W16;
61 req->rss_sz = dev->rss_info.rss_size;
62 req->rss_grps = NIX_RSS_GRPS;
63 req->npa_func = otx2_npa_pf_func_get();
64 req->sso_func = otx2_sso_pf_func_get();
65 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
66 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
67 DEV_RX_OFFLOAD_UDP_CKSUM)) {
68 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
69 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
71 req->rx_cfg |= BIT_ULL(32 /* DROP_RE */);
73 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
77 dev->sqb_size = rsp->sqb_size;
78 dev->tx_chan_base = rsp->tx_chan_base;
79 dev->rx_chan_base = rsp->rx_chan_base;
80 dev->rx_chan_cnt = rsp->rx_chan_cnt;
81 dev->tx_chan_cnt = rsp->tx_chan_cnt;
82 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
83 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
84 dev->lf_tx_stats = rsp->lf_tx_stats;
85 dev->lf_rx_stats = rsp->lf_rx_stats;
86 dev->cints = rsp->cints;
87 dev->qints = rsp->qints;
88 dev->npc_flow.channel = dev->rx_chan_base;
89 dev->ptp_en = rsp->hw_rx_tstamp_en;
95 nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev)
97 struct otx2_mbox *mbox = dev->mbox;
98 struct npc_set_pkind *req;
102 if (dev->npc_flow.switch_header_type == 0)
105 /* Notify AF about higig2 config */
106 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
107 req->mode = dev->npc_flow.switch_header_type;
109 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
112 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
113 req->mode = dev->npc_flow.switch_header_type;
115 return otx2_mbox_process_msg(mbox, (void *)&rsp);
119 nix_lf_free(struct otx2_eth_dev *dev)
121 struct otx2_mbox *mbox = dev->mbox;
122 struct nix_lf_free_req *req;
123 struct ndc_sync_op *ndc_req;
126 /* Sync NDC-NIX for LF */
127 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
128 ndc_req->nix_lf_tx_sync = 1;
129 ndc_req->nix_lf_rx_sync = 1;
130 rc = otx2_mbox_process(mbox);
132 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
134 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
135 /* Let AF driver free all this nix lf's
136 * NPC entries allocated using NPC MBOX.
140 return otx2_mbox_process(mbox);
144 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
146 struct otx2_mbox *mbox = dev->mbox;
148 if (otx2_dev_is_vf_or_sdp(dev))
151 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
153 return otx2_mbox_process(mbox);
157 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
159 struct otx2_mbox *mbox = dev->mbox;
161 if (otx2_dev_is_vf_or_sdp(dev))
164 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
166 return otx2_mbox_process(mbox);
170 npc_rx_enable(struct otx2_eth_dev *dev)
172 struct otx2_mbox *mbox = dev->mbox;
174 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
176 return otx2_mbox_process(mbox);
180 npc_rx_disable(struct otx2_eth_dev *dev)
182 struct otx2_mbox *mbox = dev->mbox;
184 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
186 return otx2_mbox_process(mbox);
190 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
192 struct otx2_mbox *mbox = dev->mbox;
194 if (otx2_dev_is_vf_or_sdp(dev))
197 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
199 return otx2_mbox_process(mbox);
203 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
205 struct otx2_mbox *mbox = dev->mbox;
207 if (otx2_dev_is_vf_or_sdp(dev))
211 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
213 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
215 return otx2_mbox_process(mbox);
219 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
221 struct otx2_mbox *mbox = dev->mbox;
223 if (otx2_dev_is_vf_or_sdp(dev))
226 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
228 return otx2_mbox_process(mbox);
232 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
238 static inline uint32_t
239 nix_qsize_to_val(enum nix_q_size_e qsize)
241 return (16UL << (qsize * 2));
244 static inline enum nix_q_size_e
245 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
249 if (otx2_ethdev_fixup_is_min_4k_q(dev))
254 for (; i < nix_q_size_max; i++)
255 if (val <= nix_qsize_to_val(i))
258 if (i >= nix_q_size_max)
259 i = nix_q_size_max - 1;
265 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
266 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
268 struct otx2_mbox *mbox = dev->mbox;
269 const struct rte_memzone *rz;
270 uint32_t ring_size, cq_size;
271 struct nix_aq_enq_req *aq;
276 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
277 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
278 NIX_CQ_ALIGN, dev->node);
280 otx2_err("Failed to allocate mem for cq hw ring");
284 memset(rz->addr, 0, rz->len);
285 rxq->desc = (uintptr_t)rz->addr;
286 rxq->qmask = cq_size - 1;
288 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
290 aq->ctype = NIX_AQ_CTYPE_CQ;
291 aq->op = NIX_AQ_INSTOP_INIT;
295 aq->cq.qsize = rxq->qsize;
296 aq->cq.base = rz->iova;
297 aq->cq.avg_level = 0xff;
298 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
299 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
301 /* Many to one reduction */
302 aq->cq.qint_idx = qid % dev->qints;
303 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
304 aq->cq.cint_idx = qid;
306 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
307 const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
308 uint16_t min_rx_drop;
310 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
311 aq->cq.drop = min_rx_drop;
313 rxq->cq_drop = min_rx_drop;
315 rxq->cq_drop = NIX_CQ_THRESH_LEVEL;
316 aq->cq.drop = rxq->cq_drop;
320 /* TX pause frames enable flowctrl on RX side */
321 if (dev->fc_info.tx_pause) {
322 /* Single bpid is allocated for all rx channels for now */
323 aq->cq.bpid = dev->fc_info.bpid[0];
324 aq->cq.bp = rxq->cq_drop;
328 rc = otx2_mbox_process(mbox);
330 otx2_err("Failed to init cq context");
334 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
336 aq->ctype = NIX_AQ_CTYPE_RQ;
337 aq->op = NIX_AQ_INSTOP_INIT;
340 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
342 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
343 first_skip = (sizeof(struct rte_mbuf));
344 first_skip += RTE_PKTMBUF_HEADROOM;
345 first_skip += rte_pktmbuf_priv_size(mp);
346 rxq->data_off = first_skip;
348 first_skip /= 8; /* Expressed in number of dwords */
349 aq->rq.first_skip = first_skip;
350 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
351 aq->rq.flow_tagw = 32; /* 32-bits */
352 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
353 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
354 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
355 aq->rq.lpb_sizem1 /= 8;
356 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
358 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
359 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
360 aq->rq.rq_int_ena = 0;
361 /* Many to one reduction */
362 aq->rq.qint_idx = qid % dev->qints;
364 aq->rq.xqe_drop_ena = 1;
366 rc = otx2_mbox_process(mbox);
368 otx2_err("Failed to init rq context");
378 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
379 struct otx2_eth_rxq *rxq, const bool enb)
381 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
382 struct otx2_mbox *mbox = dev->mbox;
383 struct nix_aq_enq_req *aq;
385 /* Pkts will be dropped silently if RQ is disabled */
386 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
388 aq->ctype = NIX_AQ_CTYPE_RQ;
389 aq->op = NIX_AQ_INSTOP_WRITE;
392 aq->rq_mask.ena = ~(aq->rq_mask.ena);
394 return otx2_mbox_process(mbox);
398 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
400 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
401 struct otx2_mbox *mbox = dev->mbox;
402 struct nix_aq_enq_req *aq;
405 /* RQ is already disabled */
407 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
409 aq->ctype = NIX_AQ_CTYPE_CQ;
410 aq->op = NIX_AQ_INSTOP_WRITE;
413 aq->cq_mask.ena = ~(aq->cq_mask.ena);
415 rc = otx2_mbox_process(mbox);
417 otx2_err("Failed to disable cq context");
425 nix_get_data_off(struct otx2_eth_dev *dev)
427 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
431 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
433 struct rte_mbuf mb_def;
436 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
437 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
438 offsetof(struct rte_mbuf, data_off) != 2);
439 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
440 offsetof(struct rte_mbuf, data_off) != 4);
441 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
442 offsetof(struct rte_mbuf, data_off) != 6);
444 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
445 mb_def.port = port_id;
446 rte_mbuf_refcnt_set(&mb_def, 1);
448 /* Prevent compiler reordering: rearm_data covers previous fields */
449 rte_compiler_barrier();
450 tmp = (uint64_t *)&mb_def.rearm_data;
456 otx2_nix_rx_queue_release(void *rx_queue)
458 struct otx2_eth_rxq *rxq = rx_queue;
463 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
464 nix_cq_rq_uninit(rxq->eth_dev, rxq);
469 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
470 uint16_t nb_desc, unsigned int socket,
471 const struct rte_eth_rxconf *rx_conf,
472 struct rte_mempool *mp)
474 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
475 struct rte_mempool_ops *ops;
476 struct otx2_eth_rxq *rxq;
477 const char *platform_ops;
478 enum nix_q_size_e qsize;
484 /* Compile time check to make sure all fast path elements in a CL */
485 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
488 if (rx_conf->rx_deferred_start == 1) {
489 otx2_err("Deferred Rx start is not supported");
493 platform_ops = rte_mbuf_platform_mempool_ops();
494 /* This driver needs octeontx2_npa mempool ops to work */
495 ops = rte_mempool_get_ops(mp->ops_index);
496 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
497 otx2_err("mempool ops should be of octeontx2_npa type");
501 if (mp->pool_id == 0) {
502 otx2_err("Invalid pool_id");
506 /* Free memory prior to re-allocation if needed */
507 if (eth_dev->data->rx_queues[rq] != NULL) {
508 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
509 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
510 eth_dev->data->rx_queues[rq] = NULL;
513 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
514 dev->rx_offloads |= offloads;
516 /* Find the CQ queue size */
517 qsize = nix_qsize_clampup_get(dev, nb_desc);
518 /* Allocate rxq memory */
519 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
521 otx2_err("Failed to allocate rq=%d", rq);
526 rxq->eth_dev = eth_dev;
528 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
529 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
530 rxq->wdata = (uint64_t)rq << 32;
531 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
532 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
533 eth_dev->data->port_id);
534 rxq->offloads = offloads;
536 rxq->qlen = nix_qsize_to_val(qsize);
538 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
539 rxq->tstamp = &dev->tstamp;
541 /* Alloc completion queue */
542 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
544 otx2_err("Failed to allocate rxq=%u", rq);
548 rxq->qconf.socket_id = socket;
549 rxq->qconf.nb_desc = nb_desc;
550 rxq->qconf.mempool = mp;
551 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
553 nix_rx_queue_reset(rxq);
554 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
555 rq, mp->name, qsize, nb_desc, rxq->qlen);
557 eth_dev->data->rx_queues[rq] = rxq;
558 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
560 /* Calculating delta and freq mult between PTP HI clock and tsc.
561 * These are needed in deriving raw clock value from tsc counter.
562 * read_clock eth op returns raw clock value.
564 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
565 otx2_ethdev_is_ptp_en(dev)) {
566 rc = otx2_nix_raw_clock_tsc_conv(dev);
568 otx2_err("Failed to calculate delta and freq mult");
576 otx2_nix_rx_queue_release(rxq);
581 static inline uint8_t
582 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
585 * Maximum three segments can be supported with W8, Choose
586 * NIX_MAXSQESZ_W16 for multi segment offload.
588 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
589 return NIX_MAXSQESZ_W16;
591 return NIX_MAXSQESZ_W8;
595 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
597 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
598 struct rte_eth_dev_data *data = eth_dev->data;
599 struct rte_eth_conf *conf = &data->dev_conf;
600 struct rte_eth_rxmode *rxmode = &conf->rxmode;
603 if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
604 (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
605 flags |= NIX_RX_OFFLOAD_RSS_F;
607 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
608 DEV_RX_OFFLOAD_UDP_CKSUM))
609 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
611 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
612 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
613 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
615 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
616 flags |= NIX_RX_MULTI_SEG_F;
618 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
619 DEV_RX_OFFLOAD_QINQ_STRIP))
620 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
622 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
623 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
629 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
631 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
632 uint64_t conf = dev->tx_offloads;
635 /* Fastpath is dependent on these enums */
636 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
637 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
638 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
639 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
640 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
641 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
642 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
643 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
644 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
645 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
646 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
647 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
648 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
649 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
650 offsetof(struct rte_mbuf, buf_iova) + 8);
651 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
652 offsetof(struct rte_mbuf, buf_iova) + 16);
653 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
654 offsetof(struct rte_mbuf, ol_flags) + 12);
655 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
656 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
658 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
659 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
660 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
662 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
663 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
664 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
666 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
667 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
668 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
669 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
670 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
672 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
673 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
675 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
676 flags |= NIX_TX_MULTI_SEG_F;
678 /* Enable Inner checksum for TSO */
679 if (conf & DEV_TX_OFFLOAD_TCP_TSO)
680 flags |= (NIX_TX_OFFLOAD_TSO_F |
681 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
683 /* Enable Inner and Outer checksum for Tunnel TSO */
684 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
685 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
686 DEV_TX_OFFLOAD_GRE_TNL_TSO))
687 flags |= (NIX_TX_OFFLOAD_TSO_F |
688 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
689 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
691 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
692 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
698 nix_sq_init(struct otx2_eth_txq *txq)
700 struct otx2_eth_dev *dev = txq->dev;
701 struct otx2_mbox *mbox = dev->mbox;
702 struct nix_aq_enq_req *sq;
707 if (txq->sqb_pool->pool_id == 0)
710 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
712 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
716 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
718 sq->ctype = NIX_AQ_CTYPE_SQ;
719 sq->op = NIX_AQ_INSTOP_INIT;
720 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
723 sq->sq.smq_rr_quantum = rr_quantum;
724 sq->sq.default_chan = dev->tx_chan_base;
725 sq->sq.sqe_stype = NIX_STYPE_STF;
727 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
728 sq->sq.sqe_stype = NIX_STYPE_STP;
730 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
731 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
732 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
733 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
734 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
736 /* Many to one reduction */
737 sq->sq.qint_idx = txq->sq % dev->qints;
739 return otx2_mbox_process(mbox);
743 nix_sq_uninit(struct otx2_eth_txq *txq)
745 struct otx2_eth_dev *dev = txq->dev;
746 struct otx2_mbox *mbox = dev->mbox;
747 struct ndc_sync_op *ndc_req;
748 struct nix_aq_enq_rsp *rsp;
749 struct nix_aq_enq_req *aq;
750 uint16_t sqes_per_sqb;
754 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
756 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
758 aq->ctype = NIX_AQ_CTYPE_SQ;
759 aq->op = NIX_AQ_INSTOP_READ;
761 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
765 /* Check if sq is already cleaned up */
770 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
772 aq->ctype = NIX_AQ_CTYPE_SQ;
773 aq->op = NIX_AQ_INSTOP_WRITE;
775 aq->sq_mask.ena = ~aq->sq_mask.ena;
778 rc = otx2_mbox_process(mbox);
782 /* Read SQ and free sqb's */
783 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
785 aq->ctype = NIX_AQ_CTYPE_SQ;
786 aq->op = NIX_AQ_INSTOP_READ;
788 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
793 otx2_err("SQ has pending sqe's");
795 count = aq->sq.sqb_count;
796 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
797 /* Free SQB's that are used */
798 sqb_buf = (void *)rsp->sq.head_sqb;
802 next_sqb = *(void **)((uintptr_t)sqb_buf + (uint32_t)
803 ((sqes_per_sqb - 1) *
804 nix_sq_max_sqe_sz(txq)));
805 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
811 /* Free next to use sqb */
812 if (rsp->sq.next_sqb)
813 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
816 /* Sync NDC-NIX-TX for LF */
817 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
818 ndc_req->nix_lf_tx_sync = 1;
819 rc = otx2_mbox_process(mbox);
821 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
827 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
829 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
830 struct npa_aq_enq_req *aura_req;
832 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
833 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
834 aura_req->ctype = NPA_AQ_CTYPE_AURA;
835 aura_req->op = NPA_AQ_INSTOP_WRITE;
837 aura_req->aura.limit = nb_sqb_bufs;
838 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
840 return otx2_mbox_process(npa_lf->mbox);
844 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
846 struct otx2_eth_dev *dev = txq->dev;
847 uint16_t sqes_per_sqb, nb_sqb_bufs;
848 char name[RTE_MEMPOOL_NAMESIZE];
849 struct rte_mempool_objsz sz;
850 struct npa_aura_s *aura;
851 uint32_t tmp, blk_sz;
853 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
854 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
855 blk_sz = dev->sqb_size;
857 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
858 sqes_per_sqb = (dev->sqb_size / 8) / 16;
860 sqes_per_sqb = (dev->sqb_size / 8) / 8;
862 nb_sqb_bufs = nb_desc / sqes_per_sqb;
863 /* Clamp up to devarg passed SQB count */
864 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_DEF_SQB,
865 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
867 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
869 MEMPOOL_F_NO_SPREAD);
870 txq->nb_sqb_bufs = nb_sqb_bufs;
871 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
872 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
873 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
874 txq->nb_sqb_bufs_adj =
875 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
877 if (txq->sqb_pool == NULL) {
878 otx2_err("Failed to allocate sqe mempool");
882 memset(aura, 0, sizeof(*aura));
884 aura->fc_addr = txq->fc_iova;
885 aura->fc_hyst_bits = 0; /* Store count on all updates */
886 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
887 otx2_err("Failed to set ops for sqe mempool");
890 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
891 otx2_err("Failed to populate sqe mempool");
895 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
896 if (dev->sqb_size != sz.elt_size) {
897 otx2_err("sqe pool block size is not expected %d != %d",
902 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
910 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
912 struct nix_send_ext_s *send_hdr_ext;
913 struct nix_send_hdr_s *send_hdr;
914 struct nix_send_mem_s *send_mem;
915 union nix_send_sg_s *sg;
917 /* Initialize the fields based on basic single segment packet */
918 memset(&txq->cmd, 0, sizeof(txq->cmd));
920 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
921 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
922 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
923 send_hdr->w0.sizem1 = 2;
925 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
926 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
927 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
928 /* Default: one seg packet would have:
929 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
932 send_hdr->w0.sizem1 = 3;
933 send_hdr_ext->w0.tstmp = 1;
935 /* To calculate the offset for send_mem,
936 * send_hdr->w0.sizem1 * 2
938 send_mem = (struct nix_send_mem_s *)(txq->cmd +
939 (send_hdr->w0.sizem1 << 1));
940 send_mem->subdc = NIX_SUBDC_MEM;
941 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
942 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
944 sg = (union nix_send_sg_s *)&txq->cmd[4];
946 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
947 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
948 send_hdr->w0.sizem1 = 1;
949 sg = (union nix_send_sg_s *)&txq->cmd[2];
952 send_hdr->w0.sq = txq->sq;
953 sg->subdc = NIX_SUBDC_SG;
955 sg->ld_type = NIX_SENDLDTYPE_LDD;
961 otx2_nix_tx_queue_release(void *_txq)
963 struct otx2_eth_txq *txq = _txq;
964 struct rte_eth_dev *eth_dev;
969 eth_dev = txq->dev->eth_dev;
971 otx2_nix_dbg("Releasing txq %u", txq->sq);
973 /* Flush and disable tm */
974 otx2_nix_tm_sw_xoff(txq, eth_dev->data->dev_started);
976 /* Free sqb's and disable sq */
980 rte_mempool_free(txq->sqb_pool);
981 txq->sqb_pool = NULL;
988 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
989 uint16_t nb_desc, unsigned int socket_id,
990 const struct rte_eth_txconf *tx_conf)
992 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
993 const struct rte_memzone *fc;
994 struct otx2_eth_txq *txq;
1000 /* Compile time check to make sure all fast path elements in a CL */
1001 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
1003 if (tx_conf->tx_deferred_start) {
1004 otx2_err("Tx deferred start is not supported");
1008 /* Free memory prior to re-allocation if needed. */
1009 if (eth_dev->data->tx_queues[sq] != NULL) {
1010 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
1011 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
1012 eth_dev->data->tx_queues[sq] = NULL;
1015 /* Find the expected offloads for this queue */
1016 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
1018 /* Allocating tx queue data structure */
1019 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
1020 OTX2_ALIGN, socket_id);
1022 otx2_err("Failed to alloc txq=%d", sq);
1028 txq->sqb_pool = NULL;
1029 txq->offloads = offloads;
1030 dev->tx_offloads |= offloads;
1033 * Allocate memory for flow control updates from HW.
1034 * Alloc one cache line, so that fits all FC_STYPE modes.
1036 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
1037 OTX2_ALIGN + sizeof(struct npa_aura_s),
1038 OTX2_ALIGN, dev->node);
1040 otx2_err("Failed to allocate mem for fcmem");
1044 txq->fc_iova = fc->iova;
1045 txq->fc_mem = fc->addr;
1047 /* Initialize the aura sqb pool */
1048 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
1050 otx2_err("Failed to alloc sqe pool rc=%d", rc);
1054 /* Initialize the SQ */
1055 rc = nix_sq_init(txq);
1057 otx2_err("Failed to init sq=%d context", sq);
1061 txq->fc_cache_pkts = 0;
1062 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
1063 /* Evenly distribute LMT slot for each sq */
1064 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
1066 txq->qconf.socket_id = socket_id;
1067 txq->qconf.nb_desc = nb_desc;
1068 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
1070 otx2_nix_form_default_desc(txq);
1072 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
1073 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
1074 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
1075 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
1076 eth_dev->data->tx_queues[sq] = txq;
1077 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
1081 otx2_nix_tx_queue_release(txq);
1087 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1089 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1090 struct otx2_eth_qconf *tx_qconf = NULL;
1091 struct otx2_eth_qconf *rx_qconf = NULL;
1092 struct otx2_eth_txq **txq;
1093 struct otx2_eth_rxq **rxq;
1094 int i, nb_rxq, nb_txq;
1096 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1097 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1099 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1100 if (tx_qconf == NULL) {
1101 otx2_err("Failed to allocate memory for tx_qconf");
1105 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1106 if (rx_qconf == NULL) {
1107 otx2_err("Failed to allocate memory for rx_qconf");
1111 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1112 for (i = 0; i < nb_txq; i++) {
1113 if (txq[i] == NULL) {
1114 otx2_err("txq[%d] is already released", i);
1117 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1118 otx2_nix_tx_queue_release(txq[i]);
1119 eth_dev->data->tx_queues[i] = NULL;
1122 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1123 for (i = 0; i < nb_rxq; i++) {
1124 if (rxq[i] == NULL) {
1125 otx2_err("rxq[%d] is already released", i);
1128 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1129 otx2_nix_rx_queue_release(rxq[i]);
1130 eth_dev->data->rx_queues[i] = NULL;
1133 dev->tx_qconf = tx_qconf;
1134 dev->rx_qconf = rx_qconf;
1147 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1149 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1150 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1151 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1152 struct otx2_eth_txq **txq;
1153 struct otx2_eth_rxq **rxq;
1154 int rc, i, nb_rxq, nb_txq;
1156 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1157 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1160 /* Setup tx & rx queues with previous configuration so
1161 * that the queues can be functional in cases like ports
1162 * are started without re configuring queues.
1164 * Usual re config sequence is like below:
1165 * port_configure() {
1170 * queue_configure() {
1177 * In some application's control path, queue_configure() would
1178 * NOT be invoked for TXQs/RXQs in port_configure().
1179 * In such cases, queues can be functional after start as the
1180 * queues are already setup in port_configure().
1182 for (i = 0; i < nb_txq; i++) {
1183 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1184 tx_qconf[i].socket_id,
1185 &tx_qconf[i].conf.tx);
1187 otx2_err("Failed to setup tx queue rc=%d", rc);
1188 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1189 for (i -= 1; i >= 0; i--)
1190 otx2_nix_tx_queue_release(txq[i]);
1195 free(tx_qconf); tx_qconf = NULL;
1197 for (i = 0; i < nb_rxq; i++) {
1198 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1199 rx_qconf[i].socket_id,
1200 &rx_qconf[i].conf.rx,
1201 rx_qconf[i].mempool);
1203 otx2_err("Failed to setup rx queue rc=%d", rc);
1204 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1205 for (i -= 1; i >= 0; i--)
1206 otx2_nix_rx_queue_release(rxq[i]);
1207 goto release_tx_queues;
1211 free(rx_qconf); rx_qconf = NULL;
1216 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1217 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1218 otx2_nix_tx_queue_release(txq[i]);
1229 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1231 RTE_SET_USED(queue);
1232 RTE_SET_USED(mbufs);
1239 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1241 /* These dummy functions are required for supporting
1242 * some applications which reconfigure queues without
1243 * stopping tx burst and rx burst threads(eg kni app)
1244 * When the queues context is saved, txq/rxqs are released
1245 * which caused app crash since rx/tx burst is still
1246 * on different lcores
1248 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1249 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1254 nix_lso_tcp(struct nix_lso_format_cfg *req, bool v4)
1256 volatile struct nix_lso_format *field;
1258 /* Format works only with TCP packet marked by OL3/OL4 */
1259 field = (volatile struct nix_lso_format *)&req->fields[0];
1260 req->field_mask = NIX_LSO_FIELD_MASK;
1261 /* Outer IPv4/IPv6 */
1262 field->layer = NIX_TXLAYER_OL3;
1263 field->offset = v4 ? 2 : 4;
1264 field->sizem1 = 1; /* 2B */
1265 field->alg = NIX_LSOALG_ADD_PAYLEN;
1269 field->layer = NIX_TXLAYER_OL3;
1272 /* Incremented linearly per segment */
1273 field->alg = NIX_LSOALG_ADD_SEGNUM;
1277 /* TCP sequence number update */
1278 field->layer = NIX_TXLAYER_OL4;
1280 field->sizem1 = 3; /* 4 bytes */
1281 field->alg = NIX_LSOALG_ADD_OFFSET;
1283 /* TCP flags field */
1284 field->layer = NIX_TXLAYER_OL4;
1287 field->alg = NIX_LSOALG_TCP_FLAGS;
1292 nix_lso_udp_tun_tcp(struct nix_lso_format_cfg *req,
1293 bool outer_v4, bool inner_v4)
1295 volatile struct nix_lso_format *field;
1297 field = (volatile struct nix_lso_format *)&req->fields[0];
1298 req->field_mask = NIX_LSO_FIELD_MASK;
1299 /* Outer IPv4/IPv6 len */
1300 field->layer = NIX_TXLAYER_OL3;
1301 field->offset = outer_v4 ? 2 : 4;
1302 field->sizem1 = 1; /* 2B */
1303 field->alg = NIX_LSOALG_ADD_PAYLEN;
1307 field->layer = NIX_TXLAYER_OL3;
1310 /* Incremented linearly per segment */
1311 field->alg = NIX_LSOALG_ADD_SEGNUM;
1315 /* Outer UDP length */
1316 field->layer = NIX_TXLAYER_OL4;
1319 field->alg = NIX_LSOALG_ADD_PAYLEN;
1322 /* Inner IPv4/IPv6 */
1323 field->layer = NIX_TXLAYER_IL3;
1324 field->offset = inner_v4 ? 2 : 4;
1325 field->sizem1 = 1; /* 2B */
1326 field->alg = NIX_LSOALG_ADD_PAYLEN;
1330 field->layer = NIX_TXLAYER_IL3;
1333 /* Incremented linearly per segment */
1334 field->alg = NIX_LSOALG_ADD_SEGNUM;
1338 /* TCP sequence number update */
1339 field->layer = NIX_TXLAYER_IL4;
1341 field->sizem1 = 3; /* 4 bytes */
1342 field->alg = NIX_LSOALG_ADD_OFFSET;
1345 /* TCP flags field */
1346 field->layer = NIX_TXLAYER_IL4;
1349 field->alg = NIX_LSOALG_TCP_FLAGS;
1354 nix_lso_tun_tcp(struct nix_lso_format_cfg *req,
1355 bool outer_v4, bool inner_v4)
1357 volatile struct nix_lso_format *field;
1359 field = (volatile struct nix_lso_format *)&req->fields[0];
1360 req->field_mask = NIX_LSO_FIELD_MASK;
1361 /* Outer IPv4/IPv6 len */
1362 field->layer = NIX_TXLAYER_OL3;
1363 field->offset = outer_v4 ? 2 : 4;
1364 field->sizem1 = 1; /* 2B */
1365 field->alg = NIX_LSOALG_ADD_PAYLEN;
1369 field->layer = NIX_TXLAYER_OL3;
1372 /* Incremented linearly per segment */
1373 field->alg = NIX_LSOALG_ADD_SEGNUM;
1377 /* Inner IPv4/IPv6 */
1378 field->layer = NIX_TXLAYER_IL3;
1379 field->offset = inner_v4 ? 2 : 4;
1380 field->sizem1 = 1; /* 2B */
1381 field->alg = NIX_LSOALG_ADD_PAYLEN;
1385 field->layer = NIX_TXLAYER_IL3;
1388 /* Incremented linearly per segment */
1389 field->alg = NIX_LSOALG_ADD_SEGNUM;
1393 /* TCP sequence number update */
1394 field->layer = NIX_TXLAYER_IL4;
1396 field->sizem1 = 3; /* 4 bytes */
1397 field->alg = NIX_LSOALG_ADD_OFFSET;
1400 /* TCP flags field */
1401 field->layer = NIX_TXLAYER_IL4;
1404 field->alg = NIX_LSOALG_TCP_FLAGS;
1409 nix_setup_lso_formats(struct otx2_eth_dev *dev)
1411 struct otx2_mbox *mbox = dev->mbox;
1412 struct nix_lso_format_cfg_rsp *rsp;
1413 struct nix_lso_format_cfg *req;
1417 /* Skip if TSO was not requested */
1418 if (!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F))
1423 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1424 nix_lso_tcp(req, true);
1425 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1429 base = rsp->lso_format_idx;
1430 if (base != NIX_LSO_FORMAT_IDX_TSOV4)
1432 dev->lso_base_idx = base;
1433 otx2_nix_dbg("tcpv4 lso fmt=%u", base);
1439 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1440 nix_lso_tcp(req, false);
1441 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1445 if (rsp->lso_format_idx != base + 1)
1447 otx2_nix_dbg("tcpv6 lso fmt=%u\n", base + 1);
1450 * IPv4/UDP/TUN HDR/IPv4/TCP LSO
1452 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1453 nix_lso_udp_tun_tcp(req, true, true);
1454 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1458 if (rsp->lso_format_idx != base + 2)
1460 otx2_nix_dbg("udp tun v4v4 fmt=%u\n", base + 2);
1463 * IPv4/UDP/TUN HDR/IPv6/TCP LSO
1465 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1466 nix_lso_udp_tun_tcp(req, true, false);
1467 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1471 if (rsp->lso_format_idx != base + 3)
1473 otx2_nix_dbg("udp tun v4v6 fmt=%u\n", base + 3);
1476 * IPv6/UDP/TUN HDR/IPv4/TCP LSO
1478 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1479 nix_lso_udp_tun_tcp(req, false, true);
1480 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1484 if (rsp->lso_format_idx != base + 4)
1486 otx2_nix_dbg("udp tun v6v4 fmt=%u\n", base + 4);
1489 * IPv6/UDP/TUN HDR/IPv6/TCP LSO
1491 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1492 nix_lso_udp_tun_tcp(req, false, false);
1493 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1496 if (rsp->lso_format_idx != base + 5)
1498 otx2_nix_dbg("udp tun v6v6 fmt=%u\n", base + 5);
1501 * IPv4/TUN HDR/IPv4/TCP LSO
1503 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1504 nix_lso_tun_tcp(req, true, true);
1505 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1509 if (rsp->lso_format_idx != base + 6)
1511 otx2_nix_dbg("tun v4v4 fmt=%u\n", base + 6);
1514 * IPv4/TUN HDR/IPv6/TCP LSO
1516 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1517 nix_lso_tun_tcp(req, true, false);
1518 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1522 if (rsp->lso_format_idx != base + 7)
1524 otx2_nix_dbg("tun v4v6 fmt=%u\n", base + 7);
1527 * IPv6/TUN HDR/IPv4/TCP LSO
1529 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1530 nix_lso_tun_tcp(req, false, true);
1531 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1535 if (rsp->lso_format_idx != base + 8)
1537 otx2_nix_dbg("tun v6v4 fmt=%u\n", base + 8);
1540 * IPv6/TUN HDR/IPv6/TCP LSO
1542 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1543 nix_lso_tun_tcp(req, false, false);
1544 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1547 if (rsp->lso_format_idx != base + 9)
1549 otx2_nix_dbg("tun v6v6 fmt=%u\n", base + 9);
1554 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1556 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1557 struct rte_eth_dev_data *data = eth_dev->data;
1558 struct rte_eth_conf *conf = &data->dev_conf;
1559 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1560 struct rte_eth_txmode *txmode = &conf->txmode;
1561 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1562 struct rte_ether_addr *ea;
1563 uint8_t nb_rxq, nb_txq;
1569 if (rte_eal_has_hugepages() == 0) {
1570 otx2_err("Huge page is not configured");
1571 goto fail_configure;
1574 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1575 otx2_err("Setting link speed/duplex not supported");
1576 goto fail_configure;
1579 if (conf->dcb_capability_en == 1) {
1580 otx2_err("dcb enable is not supported");
1581 goto fail_configure;
1584 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1585 otx2_err("Flow director is not supported");
1586 goto fail_configure;
1589 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1590 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1591 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1592 goto fail_configure;
1595 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1596 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1597 goto fail_configure;
1600 if (otx2_dev_is_Ax(dev) &&
1601 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1602 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1603 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1604 otx2_err("Outer IP and SCTP checksum unsupported");
1605 goto fail_configure;
1608 /* Free the resources allocated from the previous configure */
1609 if (dev->configured == 1) {
1610 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1611 otx2_nix_vlan_fini(eth_dev);
1612 otx2_nix_mc_addr_list_uninstall(eth_dev);
1613 otx2_flow_free_all_resources(dev);
1614 oxt2_nix_unregister_queue_irqs(eth_dev);
1615 if (eth_dev->data->dev_conf.intr_conf.rxq)
1616 oxt2_nix_unregister_cq_irqs(eth_dev);
1617 nix_set_nop_rxtx_function(eth_dev);
1618 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1620 goto fail_configure;
1621 otx2_nix_tm_fini(eth_dev);
1625 dev->rx_offloads = rxmode->offloads;
1626 dev->tx_offloads = txmode->offloads;
1627 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1628 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1629 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1631 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1632 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1634 /* Alloc a nix lf */
1635 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1637 otx2_err("Failed to init nix_lf rc=%d", rc);
1641 rc = nix_lf_switch_header_type_enable(dev);
1643 otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
1647 rc = nix_setup_lso_formats(dev);
1649 otx2_err("failed to setup nix lso format fields, rc=%d", rc);
1654 rc = otx2_nix_rss_config(eth_dev);
1656 otx2_err("Failed to configure rss rc=%d", rc);
1660 /* Init the default TM scheduler hierarchy */
1661 rc = otx2_nix_tm_init_default(eth_dev);
1663 otx2_err("Failed to init traffic manager rc=%d", rc);
1667 rc = otx2_nix_vlan_offload_init(eth_dev);
1669 otx2_err("Failed to init vlan offload rc=%d", rc);
1673 /* Register queue IRQs */
1674 rc = oxt2_nix_register_queue_irqs(eth_dev);
1676 otx2_err("Failed to register queue interrupts rc=%d", rc);
1680 /* Register cq IRQs */
1681 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1682 if (eth_dev->data->nb_rx_queues > dev->cints) {
1683 otx2_err("Rx interrupt cannot be enabled, rxq > %d",
1687 /* Rx interrupt feature cannot work with vector mode because,
1688 * vector mode doesn't process packets unless min 4 pkts are
1689 * received, while cq interrupts are generated even for 1 pkt
1692 dev->scalar_ena = true;
1694 rc = oxt2_nix_register_cq_irqs(eth_dev);
1696 otx2_err("Failed to register CQ interrupts rc=%d", rc);
1701 /* Configure loop back mode */
1702 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1704 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1708 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1710 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1714 rc = otx2_nix_mc_addr_list_install(eth_dev);
1716 otx2_err("Failed to install mc address list rc=%d", rc);
1721 * Restore queue config when reconfigure followed by
1722 * reconfigure and no queue configure invoked from application case.
1724 if (dev->configured == 1) {
1725 rc = nix_restore_queue_cfg(eth_dev);
1727 goto uninstall_mc_list;
1730 /* Update the mac address */
1731 ea = eth_dev->data->mac_addrs;
1732 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1733 if (rte_is_zero_ether_addr(ea))
1734 rte_eth_random_addr((uint8_t *)ea);
1736 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1738 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1739 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1740 " rx_flags=0x%x tx_flags=0x%x",
1741 eth_dev->data->port_id, ea_fmt, nb_rxq,
1742 nb_txq, dev->rx_offloads, dev->tx_offloads,
1743 dev->rx_offload_flags, dev->tx_offload_flags);
1746 dev->configured = 1;
1747 dev->configured_nb_rx_qs = data->nb_rx_queues;
1748 dev->configured_nb_tx_qs = data->nb_tx_queues;
1752 otx2_nix_mc_addr_list_uninstall(eth_dev);
1754 oxt2_nix_unregister_cq_irqs(eth_dev);
1756 oxt2_nix_unregister_queue_irqs(eth_dev);
1758 otx2_nix_vlan_fini(eth_dev);
1760 otx2_nix_tm_fini(eth_dev);
1764 dev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);
1765 dev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);
1767 dev->configured = 0;
1772 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1774 struct rte_eth_dev_data *data = eth_dev->data;
1775 struct otx2_eth_txq *txq;
1778 txq = eth_dev->data->tx_queues[qidx];
1780 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1783 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1785 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1790 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1797 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1799 struct rte_eth_dev_data *data = eth_dev->data;
1800 struct otx2_eth_txq *txq;
1803 txq = eth_dev->data->tx_queues[qidx];
1805 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1808 txq->fc_cache_pkts = 0;
1810 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1812 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1817 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1824 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1826 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1827 struct rte_eth_dev_data *data = eth_dev->data;
1830 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1833 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1835 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1839 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1846 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1848 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1849 struct rte_eth_dev_data *data = eth_dev->data;
1852 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1855 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1857 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1861 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1868 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
1870 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1871 struct rte_mbuf *rx_pkts[32];
1872 struct otx2_eth_rxq *rxq;
1873 int count, i, j, rc;
1875 nix_cgx_stop_link_event(dev);
1876 npc_rx_disable(dev);
1878 /* Stop rx queues and free up pkts pending */
1879 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1880 rc = otx2_nix_rx_queue_stop(eth_dev, i);
1884 rxq = eth_dev->data->rx_queues[i];
1885 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1887 for (j = 0; j < count; j++)
1888 rte_pktmbuf_free(rx_pkts[j]);
1889 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1893 /* Stop tx queues */
1894 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1895 otx2_nix_tx_queue_stop(eth_dev, i);
1899 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
1901 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1904 /* MTU recalculate should be avoided here if PTP is enabled by PF, as
1905 * otx2_nix_recalc_mtu would be invoked during otx2_nix_ptp_enable_vf
1908 if (eth_dev->data->nb_rx_queues != 0 && !otx2_ethdev_is_ptp_en(dev)) {
1909 rc = otx2_nix_recalc_mtu(eth_dev);
1914 /* Start rx queues */
1915 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1916 rc = otx2_nix_rx_queue_start(eth_dev, i);
1921 /* Start tx queues */
1922 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1923 rc = otx2_nix_tx_queue_start(eth_dev, i);
1928 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
1930 otx2_err("Failed to update flow ctrl mode %d", rc);
1934 /* Enable PTP if it was requested by the app or if it is already
1935 * enabled in PF owning this VF
1937 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
1938 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
1939 otx2_ethdev_is_ptp_en(dev))
1940 otx2_nix_timesync_enable(eth_dev);
1942 otx2_nix_timesync_disable(eth_dev);
1944 /* Update VF about data off shifted by 8 bytes if PTP already
1945 * enabled in PF owning this VF
1947 if (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))
1948 otx2_nix_ptp_enable_vf(eth_dev);
1950 rc = npc_rx_enable(dev);
1952 otx2_err("Failed to enable NPC rx %d", rc);
1956 otx2_nix_toggle_flag_link_cfg(dev, true);
1958 rc = nix_cgx_start_link_event(dev);
1960 otx2_err("Failed to start cgx link event %d", rc);
1964 otx2_nix_toggle_flag_link_cfg(dev, false);
1965 otx2_eth_set_tx_function(eth_dev);
1966 otx2_eth_set_rx_function(eth_dev);
1971 npc_rx_disable(dev);
1972 otx2_nix_toggle_flag_link_cfg(dev, false);
1976 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
1977 static void otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
1979 /* Initialize and register driver with DPDK Application */
1980 static const struct eth_dev_ops otx2_eth_dev_ops = {
1981 .dev_infos_get = otx2_nix_info_get,
1982 .dev_configure = otx2_nix_configure,
1983 .link_update = otx2_nix_link_update,
1984 .tx_queue_setup = otx2_nix_tx_queue_setup,
1985 .tx_queue_release = otx2_nix_tx_queue_release,
1986 .rx_queue_setup = otx2_nix_rx_queue_setup,
1987 .rx_queue_release = otx2_nix_rx_queue_release,
1988 .dev_start = otx2_nix_dev_start,
1989 .dev_stop = otx2_nix_dev_stop,
1990 .dev_close = otx2_nix_dev_close,
1991 .tx_queue_start = otx2_nix_tx_queue_start,
1992 .tx_queue_stop = otx2_nix_tx_queue_stop,
1993 .rx_queue_start = otx2_nix_rx_queue_start,
1994 .rx_queue_stop = otx2_nix_rx_queue_stop,
1995 .dev_set_link_up = otx2_nix_dev_set_link_up,
1996 .dev_set_link_down = otx2_nix_dev_set_link_down,
1997 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
1998 .dev_ptypes_set = otx2_nix_ptypes_set,
1999 .dev_reset = otx2_nix_dev_reset,
2000 .stats_get = otx2_nix_dev_stats_get,
2001 .stats_reset = otx2_nix_dev_stats_reset,
2002 .get_reg = otx2_nix_dev_get_reg,
2003 .mtu_set = otx2_nix_mtu_set,
2004 .mac_addr_add = otx2_nix_mac_addr_add,
2005 .mac_addr_remove = otx2_nix_mac_addr_del,
2006 .mac_addr_set = otx2_nix_mac_addr_set,
2007 .set_mc_addr_list = otx2_nix_set_mc_addr_list,
2008 .promiscuous_enable = otx2_nix_promisc_enable,
2009 .promiscuous_disable = otx2_nix_promisc_disable,
2010 .allmulticast_enable = otx2_nix_allmulticast_enable,
2011 .allmulticast_disable = otx2_nix_allmulticast_disable,
2012 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
2013 .reta_update = otx2_nix_dev_reta_update,
2014 .reta_query = otx2_nix_dev_reta_query,
2015 .rss_hash_update = otx2_nix_rss_hash_update,
2016 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
2017 .xstats_get = otx2_nix_xstats_get,
2018 .xstats_get_names = otx2_nix_xstats_get_names,
2019 .xstats_reset = otx2_nix_xstats_reset,
2020 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
2021 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
2022 .rxq_info_get = otx2_nix_rxq_info_get,
2023 .txq_info_get = otx2_nix_txq_info_get,
2024 .rx_burst_mode_get = otx2_rx_burst_mode_get,
2025 .tx_burst_mode_get = otx2_tx_burst_mode_get,
2026 .rx_queue_count = otx2_nix_rx_queue_count,
2027 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
2028 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
2029 .tx_descriptor_status = otx2_nix_tx_descriptor_status,
2030 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
2031 .pool_ops_supported = otx2_nix_pool_ops_supported,
2032 .filter_ctrl = otx2_nix_dev_filter_ctrl,
2033 .get_module_info = otx2_nix_get_module_info,
2034 .get_module_eeprom = otx2_nix_get_module_eeprom,
2035 .fw_version_get = otx2_nix_fw_version_get,
2036 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
2037 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
2038 .timesync_enable = otx2_nix_timesync_enable,
2039 .timesync_disable = otx2_nix_timesync_disable,
2040 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
2041 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
2042 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
2043 .timesync_read_time = otx2_nix_timesync_read_time,
2044 .timesync_write_time = otx2_nix_timesync_write_time,
2045 .vlan_offload_set = otx2_nix_vlan_offload_set,
2046 .vlan_filter_set = otx2_nix_vlan_filter_set,
2047 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
2048 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
2049 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
2050 .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
2051 .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
2052 .read_clock = otx2_nix_read_clock,
2056 nix_lf_attach(struct otx2_eth_dev *dev)
2058 struct otx2_mbox *mbox = dev->mbox;
2059 struct rsrc_attach_req *req;
2061 /* Attach NIX(lf) */
2062 req = otx2_mbox_alloc_msg_attach_resources(mbox);
2066 return otx2_mbox_process(mbox);
2070 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
2072 struct otx2_mbox *mbox = dev->mbox;
2073 struct msix_offset_rsp *msix_rsp;
2076 /* Get NPA and NIX MSIX vector offsets */
2077 otx2_mbox_alloc_msg_msix_offset(mbox);
2079 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
2081 dev->nix_msixoff = msix_rsp->nix_msixoff;
2087 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
2089 struct rsrc_detach_req *req;
2091 req = otx2_mbox_alloc_msg_detach_resources(mbox);
2093 /* Detach all except npa lf */
2094 req->partial = true;
2101 return otx2_mbox_process(mbox);
2105 otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
2107 if (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||
2108 pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2114 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
2116 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2117 struct rte_pci_device *pci_dev;
2118 int rc, max_entries;
2120 eth_dev->dev_ops = &otx2_eth_dev_ops;
2122 /* For secondary processes, the primary has done all the work */
2123 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2124 /* Setup callbacks for secondary process */
2125 otx2_eth_set_tx_function(eth_dev);
2126 otx2_eth_set_rx_function(eth_dev);
2130 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2132 rte_eth_copy_pci_info(eth_dev, pci_dev);
2133 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2135 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
2136 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
2137 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
2139 /* Parse devargs string */
2140 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
2142 otx2_err("Failed to parse devargs rc=%d", rc);
2146 if (!dev->mbox_active) {
2147 /* Initialize the base otx2_dev object
2148 * only if already present
2150 rc = otx2_dev_init(pci_dev, dev);
2152 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
2156 if (otx2_eth_dev_is_sdp(pci_dev))
2157 dev->sdp_link = true;
2159 dev->sdp_link = false;
2160 /* Device generic callbacks */
2161 dev->ops = &otx2_dev_ops;
2162 dev->eth_dev = eth_dev;
2164 /* Grab the NPA LF if required */
2165 rc = otx2_npa_lf_init(pci_dev, dev);
2167 goto otx2_dev_uninit;
2169 dev->configured = 0;
2170 dev->drv_inited = true;
2171 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
2172 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
2175 rc = nix_lf_attach(dev);
2177 goto otx2_npa_uninit;
2179 /* Get NIX MSIX offset */
2180 rc = nix_lf_get_msix_offset(dev);
2182 goto otx2_npa_uninit;
2184 /* Register LF irq handlers */
2185 rc = otx2_nix_register_irqs(eth_dev);
2189 /* Get maximum number of supported MAC entries */
2190 max_entries = otx2_cgx_mac_max_entries_get(dev);
2191 if (max_entries < 0) {
2192 otx2_err("Failed to get max entries for mac addr");
2194 goto unregister_irq;
2197 /* For VFs, returned max_entries will be 0. But to keep default MAC
2198 * address, one entry must be allocated. So setting up to 1.
2200 if (max_entries == 0)
2203 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
2204 RTE_ETHER_ADDR_LEN, 0);
2205 if (eth_dev->data->mac_addrs == NULL) {
2206 otx2_err("Failed to allocate memory for mac addr");
2208 goto unregister_irq;
2211 dev->max_mac_entries = max_entries;
2213 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
2215 goto free_mac_addrs;
2217 /* Update the mac address */
2218 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
2220 /* Also sync same MAC address to CGX table */
2221 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
2223 /* Initialize the tm data structures */
2224 otx2_nix_tm_conf_init(eth_dev);
2226 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
2227 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
2229 if (otx2_dev_is_96xx_A0(dev) ||
2230 otx2_dev_is_95xx_Ax(dev)) {
2231 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
2232 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
2235 /* Initialize rte-flow */
2236 rc = otx2_flow_init(dev);
2238 goto free_mac_addrs;
2240 otx2_nix_mc_filter_init(dev);
2242 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
2243 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
2244 eth_dev->data->port_id, dev->pf, dev->vf,
2245 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
2246 dev->rx_offload_capa, dev->tx_offload_capa);
2250 rte_free(eth_dev->data->mac_addrs);
2252 otx2_nix_unregister_irqs(eth_dev);
2254 otx2_eth_dev_lf_detach(dev->mbox);
2258 otx2_dev_fini(pci_dev, dev);
2260 otx2_err("Failed to init nix eth_dev rc=%d", rc);
2265 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
2267 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2268 struct rte_pci_device *pci_dev;
2271 /* Nothing to be done for secondary processes */
2272 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2275 /* Clear the flag since we are closing down */
2276 dev->configured = 0;
2278 /* Disable nix bpid config */
2279 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
2281 npc_rx_disable(dev);
2283 /* Disable vlan offloads */
2284 otx2_nix_vlan_fini(eth_dev);
2286 /* Disable other rte_flow entries */
2287 otx2_flow_fini(dev);
2289 /* Free multicast filter list */
2290 otx2_nix_mc_filter_fini(dev);
2292 /* Disable PTP if already enabled */
2293 if (otx2_ethdev_is_ptp_en(dev))
2294 otx2_nix_timesync_disable(eth_dev);
2296 nix_cgx_stop_link_event(dev);
2299 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
2300 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
2301 eth_dev->data->tx_queues[i] = NULL;
2303 eth_dev->data->nb_tx_queues = 0;
2305 /* Free up RQ's and CQ's */
2306 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2307 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
2308 eth_dev->data->rx_queues[i] = NULL;
2310 eth_dev->data->nb_rx_queues = 0;
2312 /* Free tm resources */
2313 rc = otx2_nix_tm_fini(eth_dev);
2315 otx2_err("Failed to cleanup tm, rc=%d", rc);
2317 /* Unregister queue irqs */
2318 oxt2_nix_unregister_queue_irqs(eth_dev);
2320 /* Unregister cq irqs */
2321 if (eth_dev->data->dev_conf.intr_conf.rxq)
2322 oxt2_nix_unregister_cq_irqs(eth_dev);
2324 rc = nix_lf_free(dev);
2326 otx2_err("Failed to free nix lf, rc=%d", rc);
2328 rc = otx2_npa_lf_fini();
2330 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
2332 rte_free(eth_dev->data->mac_addrs);
2333 eth_dev->data->mac_addrs = NULL;
2334 dev->drv_inited = false;
2336 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2337 otx2_nix_unregister_irqs(eth_dev);
2339 rc = otx2_eth_dev_lf_detach(dev->mbox);
2341 otx2_err("Failed to detach resources, rc=%d", rc);
2343 /* Check if mbox close is needed */
2347 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
2348 /* Will be freed later by PMD */
2349 eth_dev->data->dev_private = NULL;
2353 otx2_dev_fini(pci_dev, dev);
2358 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
2360 otx2_eth_dev_uninit(eth_dev, true);
2364 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
2368 rc = otx2_eth_dev_uninit(eth_dev, false);
2372 return otx2_eth_dev_init(eth_dev);
2376 nix_remove(struct rte_pci_device *pci_dev)
2378 struct rte_eth_dev *eth_dev;
2379 struct otx2_idev_cfg *idev;
2380 struct otx2_dev *otx2_dev;
2383 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
2385 /* Cleanup eth dev */
2386 rc = otx2_eth_dev_uninit(eth_dev, true);
2390 rte_eth_dev_pci_release(eth_dev);
2393 /* Nothing to be done for secondary processes */
2394 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2397 /* Check for common resources */
2398 idev = otx2_intra_dev_get_cfg();
2399 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
2402 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
2404 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
2407 /* Safe to cleanup mbox as no more users */
2408 otx2_dev_fini(pci_dev, otx2_dev);
2413 otx2_info("%s: common resource in use by other devices", pci_dev->name);
2418 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
2422 RTE_SET_USED(pci_drv);
2424 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
2427 /* On error on secondary, recheck if port exists in primary or
2428 * in mid of detach state.
2430 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
2431 if (!rte_eth_dev_allocated(pci_dev->device.name))
2436 static const struct rte_pci_id pci_nix_map[] = {
2438 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
2441 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
2444 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2445 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
2448 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2449 PCI_DEVID_OCTEONTX2_RVU_SDP_PF)
2452 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2453 PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2460 static struct rte_pci_driver pci_nix = {
2461 .id_table = pci_nix_map,
2462 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
2463 RTE_PCI_DRV_INTR_LSC,
2465 .remove = nix_remove,
2468 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
2469 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
2470 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");