1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <ethdev_pci.h>
9 #include <rte_malloc.h>
11 #include <rte_mbuf_pool_ops.h>
12 #include <rte_mempool.h>
14 #include "otx2_ethdev.h"
15 #include "otx2_ethdev_sec.h"
17 static inline uint64_t
18 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
20 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
22 if (otx2_dev_is_vf(dev) ||
23 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)
24 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
29 static inline uint64_t
30 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
32 uint64_t capa = NIX_TX_OFFLOAD_CAPA;
34 /* TSO not supported for earlier chip revisions */
35 if (otx2_dev_is_96xx_A0(dev) || otx2_dev_is_95xx_Ax(dev))
36 capa &= ~(DEV_TX_OFFLOAD_TCP_TSO |
37 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
38 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
39 DEV_TX_OFFLOAD_GRE_TNL_TSO);
43 static const struct otx2_dev_ops otx2_dev_ops = {
44 .link_status_update = otx2_eth_dev_link_status_update,
45 .ptp_info_update = otx2_eth_dev_ptp_info_update
49 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
51 struct otx2_mbox *mbox = dev->mbox;
52 struct nix_lf_alloc_req *req;
53 struct nix_lf_alloc_rsp *rsp;
56 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
60 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
61 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
62 req->xqe_sz = NIX_XQESZ_W16;
63 req->rss_sz = dev->rss_info.rss_size;
64 req->rss_grps = NIX_RSS_GRPS;
65 req->npa_func = otx2_npa_pf_func_get();
66 req->sso_func = otx2_sso_pf_func_get();
67 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
68 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
69 DEV_RX_OFFLOAD_UDP_CKSUM)) {
70 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
71 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
73 req->rx_cfg |= (BIT_ULL(32 /* DROP_RE */) |
74 BIT_ULL(33 /* Outer L2 Length */) |
75 BIT_ULL(38 /* Inner L4 UDP Length */) |
76 BIT_ULL(39 /* Inner L3 Length */) |
77 BIT_ULL(40 /* Outer L4 UDP Length */) |
78 BIT_ULL(41 /* Outer L3 Length */));
80 if (dev->rss_tag_as_xor == 0)
81 req->flags = NIX_LF_RSS_TAG_LSB_AS_ADDER;
83 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
87 dev->sqb_size = rsp->sqb_size;
88 dev->tx_chan_base = rsp->tx_chan_base;
89 dev->rx_chan_base = rsp->rx_chan_base;
90 dev->rx_chan_cnt = rsp->rx_chan_cnt;
91 dev->tx_chan_cnt = rsp->tx_chan_cnt;
92 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
93 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
94 dev->lf_tx_stats = rsp->lf_tx_stats;
95 dev->lf_rx_stats = rsp->lf_rx_stats;
96 dev->cints = rsp->cints;
97 dev->qints = rsp->qints;
98 dev->npc_flow.channel = dev->rx_chan_base;
99 dev->ptp_en = rsp->hw_rx_tstamp_en;
105 nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev, bool enable)
107 struct otx2_mbox *mbox = dev->mbox;
108 struct npc_set_pkind *req;
109 struct msg_resp *rsp;
112 if (dev->npc_flow.switch_header_type == 0)
115 /* Notify AF about higig2 config */
116 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
117 req->mode = dev->npc_flow.switch_header_type;
118 if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B) {
119 req->mode = OTX2_PRIV_FLAGS_CUSTOM;
120 req->pkind = NPC_RX_CHLEN90B_PKIND;
121 } else if (dev->npc_flow.switch_header_type ==
122 OTX2_PRIV_FLAGS_CH_LEN_24B) {
123 req->mode = OTX2_PRIV_FLAGS_CUSTOM;
124 req->pkind = NPC_RX_CHLEN24B_PKIND;
128 req->mode = OTX2_PRIV_FLAGS_DEFAULT;
130 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
133 req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
134 req->mode = dev->npc_flow.switch_header_type;
135 if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B ||
136 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_24B)
137 req->mode = OTX2_PRIV_FLAGS_DEFAULT;
140 req->mode = OTX2_PRIV_FLAGS_DEFAULT;
142 return otx2_mbox_process_msg(mbox, (void *)&rsp);
146 nix_lf_free(struct otx2_eth_dev *dev)
148 struct otx2_mbox *mbox = dev->mbox;
149 struct nix_lf_free_req *req;
150 struct ndc_sync_op *ndc_req;
153 /* Sync NDC-NIX for LF */
154 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
155 ndc_req->nix_lf_tx_sync = 1;
156 ndc_req->nix_lf_rx_sync = 1;
157 rc = otx2_mbox_process(mbox);
159 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
161 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
162 /* Let AF driver free all this nix lf's
163 * NPC entries allocated using NPC MBOX.
167 return otx2_mbox_process(mbox);
171 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
173 struct otx2_mbox *mbox = dev->mbox;
175 if (otx2_dev_is_vf_or_sdp(dev))
178 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
180 return otx2_mbox_process(mbox);
184 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
186 struct otx2_mbox *mbox = dev->mbox;
188 if (otx2_dev_is_vf_or_sdp(dev))
191 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
193 return otx2_mbox_process(mbox);
197 npc_rx_enable(struct otx2_eth_dev *dev)
199 struct otx2_mbox *mbox = dev->mbox;
201 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
203 return otx2_mbox_process(mbox);
207 npc_rx_disable(struct otx2_eth_dev *dev)
209 struct otx2_mbox *mbox = dev->mbox;
211 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
213 return otx2_mbox_process(mbox);
217 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
219 struct otx2_mbox *mbox = dev->mbox;
221 if (otx2_dev_is_vf_or_sdp(dev))
224 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
226 return otx2_mbox_process(mbox);
230 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
232 struct otx2_mbox *mbox = dev->mbox;
234 if (en && otx2_dev_is_vf_or_sdp(dev))
238 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
240 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
242 return otx2_mbox_process(mbox);
246 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
248 struct otx2_mbox *mbox = dev->mbox;
250 if (otx2_dev_is_vf_or_sdp(dev))
253 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
255 return otx2_mbox_process(mbox);
259 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
265 static inline uint32_t
266 nix_qsize_to_val(enum nix_q_size_e qsize)
268 return (16UL << (qsize * 2));
271 static inline enum nix_q_size_e
272 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
276 if (otx2_ethdev_fixup_is_min_4k_q(dev))
281 for (; i < nix_q_size_max; i++)
282 if (val <= nix_qsize_to_val(i))
285 if (i >= nix_q_size_max)
286 i = nix_q_size_max - 1;
292 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
293 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
295 struct otx2_mbox *mbox = dev->mbox;
296 const struct rte_memzone *rz;
297 uint32_t ring_size, cq_size;
298 struct nix_aq_enq_req *aq;
303 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
304 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
305 NIX_CQ_ALIGN, dev->node);
307 otx2_err("Failed to allocate mem for cq hw ring");
310 memset(rz->addr, 0, rz->len);
311 rxq->desc = (uintptr_t)rz->addr;
312 rxq->qmask = cq_size - 1;
314 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
316 aq->ctype = NIX_AQ_CTYPE_CQ;
317 aq->op = NIX_AQ_INSTOP_INIT;
321 aq->cq.qsize = rxq->qsize;
322 aq->cq.base = rz->iova;
323 aq->cq.avg_level = 0xff;
324 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
325 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
327 /* Many to one reduction */
328 aq->cq.qint_idx = qid % dev->qints;
329 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
330 aq->cq.cint_idx = qid;
332 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
333 const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
334 uint16_t min_rx_drop;
336 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
337 aq->cq.drop = min_rx_drop;
339 rxq->cq_drop = min_rx_drop;
341 rxq->cq_drop = NIX_CQ_THRESH_LEVEL;
342 aq->cq.drop = rxq->cq_drop;
346 /* TX pause frames enable flowctrl on RX side */
347 if (dev->fc_info.tx_pause) {
348 /* Single bpid is allocated for all rx channels for now */
349 aq->cq.bpid = dev->fc_info.bpid[0];
350 aq->cq.bp = rxq->cq_drop;
354 rc = otx2_mbox_process(mbox);
356 otx2_err("Failed to init cq context");
360 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
362 aq->ctype = NIX_AQ_CTYPE_RQ;
363 aq->op = NIX_AQ_INSTOP_INIT;
367 if (rxq->offloads & DEV_RX_OFFLOAD_SECURITY)
368 aq->rq.ipsech_ena = 1;
370 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
372 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
373 first_skip = (sizeof(struct rte_mbuf));
374 first_skip += RTE_PKTMBUF_HEADROOM;
375 first_skip += rte_pktmbuf_priv_size(mp);
376 rxq->data_off = first_skip;
378 first_skip /= 8; /* Expressed in number of dwords */
379 aq->rq.first_skip = first_skip;
380 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
381 aq->rq.flow_tagw = 32; /* 32-bits */
382 aq->rq.lpb_sizem1 = mp->elt_size / 8;
383 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
385 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
386 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
387 aq->rq.rq_int_ena = 0;
388 /* Many to one reduction */
389 aq->rq.qint_idx = qid % dev->qints;
391 aq->rq.xqe_drop_ena = 1;
393 rc = otx2_mbox_process(mbox);
395 otx2_err("Failed to init rq context");
399 if (dev->lock_rx_ctx) {
400 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
402 aq->ctype = NIX_AQ_CTYPE_CQ;
403 aq->op = NIX_AQ_INSTOP_LOCK;
405 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
407 /* The shared memory buffer can be full.
410 otx2_mbox_msg_send(mbox, 0);
411 rc = otx2_mbox_wait_for_rsp(mbox, 0);
413 otx2_err("Failed to LOCK cq context");
417 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
419 otx2_err("Failed to LOCK rq context");
424 aq->ctype = NIX_AQ_CTYPE_RQ;
425 aq->op = NIX_AQ_INSTOP_LOCK;
426 rc = otx2_mbox_process(mbox);
428 otx2_err("Failed to LOCK rq context");
437 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
438 struct otx2_eth_rxq *rxq, const bool enb)
440 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
441 struct otx2_mbox *mbox = dev->mbox;
442 struct nix_aq_enq_req *aq;
444 /* Pkts will be dropped silently if RQ is disabled */
445 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
447 aq->ctype = NIX_AQ_CTYPE_RQ;
448 aq->op = NIX_AQ_INSTOP_WRITE;
451 aq->rq_mask.ena = ~(aq->rq_mask.ena);
453 return otx2_mbox_process(mbox);
457 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
459 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
460 struct otx2_mbox *mbox = dev->mbox;
461 struct nix_aq_enq_req *aq;
464 /* RQ is already disabled */
466 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
468 aq->ctype = NIX_AQ_CTYPE_CQ;
469 aq->op = NIX_AQ_INSTOP_WRITE;
472 aq->cq_mask.ena = ~(aq->cq_mask.ena);
474 rc = otx2_mbox_process(mbox);
476 otx2_err("Failed to disable cq context");
480 if (dev->lock_rx_ctx) {
481 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
483 aq->ctype = NIX_AQ_CTYPE_CQ;
484 aq->op = NIX_AQ_INSTOP_UNLOCK;
486 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
488 /* The shared memory buffer can be full.
491 otx2_mbox_msg_send(mbox, 0);
492 rc = otx2_mbox_wait_for_rsp(mbox, 0);
494 otx2_err("Failed to UNLOCK cq context");
498 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
500 otx2_err("Failed to UNLOCK rq context");
505 aq->ctype = NIX_AQ_CTYPE_RQ;
506 aq->op = NIX_AQ_INSTOP_UNLOCK;
507 rc = otx2_mbox_process(mbox);
509 otx2_err("Failed to UNLOCK rq context");
518 nix_get_data_off(struct otx2_eth_dev *dev)
520 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
524 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
526 struct rte_mbuf mb_def;
529 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
530 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
531 offsetof(struct rte_mbuf, data_off) != 2);
532 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
533 offsetof(struct rte_mbuf, data_off) != 4);
534 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
535 offsetof(struct rte_mbuf, data_off) != 6);
537 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
538 mb_def.port = port_id;
539 rte_mbuf_refcnt_set(&mb_def, 1);
541 /* Prevent compiler reordering: rearm_data covers previous fields */
542 rte_compiler_barrier();
543 tmp = (uint64_t *)&mb_def.rearm_data;
549 otx2_nix_rx_queue_release(void *rx_queue)
551 struct otx2_eth_rxq *rxq = rx_queue;
556 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
557 nix_cq_rq_uninit(rxq->eth_dev, rxq);
562 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
563 uint16_t nb_desc, unsigned int socket,
564 const struct rte_eth_rxconf *rx_conf,
565 struct rte_mempool *mp)
567 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
568 struct rte_mempool_ops *ops;
569 struct otx2_eth_rxq *rxq;
570 const char *platform_ops;
571 enum nix_q_size_e qsize;
577 /* Compile time check to make sure all fast path elements in a CL */
578 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
581 if (rx_conf->rx_deferred_start == 1) {
582 otx2_err("Deferred Rx start is not supported");
586 platform_ops = rte_mbuf_platform_mempool_ops();
587 /* This driver needs octeontx2_npa mempool ops to work */
588 ops = rte_mempool_get_ops(mp->ops_index);
589 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
590 otx2_err("mempool ops should be of octeontx2_npa type");
594 if (mp->pool_id == 0) {
595 otx2_err("Invalid pool_id");
599 /* Free memory prior to re-allocation if needed */
600 if (eth_dev->data->rx_queues[rq] != NULL) {
601 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
602 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
603 rte_eth_dma_zone_free(eth_dev, "cq", rq);
604 eth_dev->data->rx_queues[rq] = NULL;
607 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
608 dev->rx_offloads |= offloads;
610 /* Find the CQ queue size */
611 qsize = nix_qsize_clampup_get(dev, nb_desc);
612 /* Allocate rxq memory */
613 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
615 otx2_err("Failed to allocate rq=%d", rq);
620 rxq->eth_dev = eth_dev;
622 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
623 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
624 rxq->wdata = (uint64_t)rq << 32;
625 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
626 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
627 eth_dev->data->port_id);
628 rxq->offloads = offloads;
630 rxq->qlen = nix_qsize_to_val(qsize);
632 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
633 rxq->tstamp = &dev->tstamp;
635 /* Alloc completion queue */
636 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
638 otx2_err("Failed to allocate rxq=%u", rq);
642 rxq->qconf.socket_id = socket;
643 rxq->qconf.nb_desc = nb_desc;
644 rxq->qconf.mempool = mp;
645 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
647 nix_rx_queue_reset(rxq);
648 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
649 rq, mp->name, qsize, nb_desc, rxq->qlen);
651 eth_dev->data->rx_queues[rq] = rxq;
652 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
654 /* Calculating delta and freq mult between PTP HI clock and tsc.
655 * These are needed in deriving raw clock value from tsc counter.
656 * read_clock eth op returns raw clock value.
658 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
659 otx2_ethdev_is_ptp_en(dev)) {
660 rc = otx2_nix_raw_clock_tsc_conv(dev);
662 otx2_err("Failed to calculate delta and freq mult");
667 /* Setup scatter mode if needed by jumbo */
668 otx2_nix_enable_mseg_on_jumbo(rxq);
673 otx2_nix_rx_queue_release(rxq);
678 static inline uint8_t
679 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
682 * Maximum three segments can be supported with W8, Choose
683 * NIX_MAXSQESZ_W16 for multi segment offload.
685 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
686 return NIX_MAXSQESZ_W16;
688 return NIX_MAXSQESZ_W8;
692 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
694 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
695 struct rte_eth_dev_data *data = eth_dev->data;
696 struct rte_eth_conf *conf = &data->dev_conf;
697 struct rte_eth_rxmode *rxmode = &conf->rxmode;
700 if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
701 (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
702 flags |= NIX_RX_OFFLOAD_RSS_F;
704 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
705 DEV_RX_OFFLOAD_UDP_CKSUM))
706 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
708 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
709 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
710 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
712 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
713 flags |= NIX_RX_MULTI_SEG_F;
715 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
716 DEV_RX_OFFLOAD_QINQ_STRIP))
717 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
719 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
720 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
722 if (dev->rx_offloads & DEV_RX_OFFLOAD_SECURITY)
723 flags |= NIX_RX_OFFLOAD_SECURITY_F;
725 if (!dev->ptype_disable)
726 flags |= NIX_RX_OFFLOAD_PTYPE_F;
732 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
734 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
735 uint64_t conf = dev->tx_offloads;
738 /* Fastpath is dependent on these enums */
739 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
740 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
741 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
742 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
743 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
744 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
745 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
746 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
747 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
748 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
749 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
750 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
751 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
752 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
753 offsetof(struct rte_mbuf, buf_iova) + 8);
754 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
755 offsetof(struct rte_mbuf, buf_iova) + 16);
756 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
757 offsetof(struct rte_mbuf, ol_flags) + 12);
758 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
759 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
761 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
762 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
763 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
765 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
766 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
767 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
769 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
770 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
771 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
772 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
773 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
775 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
776 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
778 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
779 flags |= NIX_TX_MULTI_SEG_F;
781 /* Enable Inner checksum for TSO */
782 if (conf & DEV_TX_OFFLOAD_TCP_TSO)
783 flags |= (NIX_TX_OFFLOAD_TSO_F |
784 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
786 /* Enable Inner and Outer checksum for Tunnel TSO */
787 if (conf & (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
788 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
789 DEV_TX_OFFLOAD_GRE_TNL_TSO))
790 flags |= (NIX_TX_OFFLOAD_TSO_F |
791 NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
792 NIX_TX_OFFLOAD_L3_L4_CSUM_F);
794 if (conf & DEV_TX_OFFLOAD_SECURITY)
795 flags |= NIX_TX_OFFLOAD_SECURITY_F;
797 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
798 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
804 nix_sqb_lock(struct rte_mempool *mp)
806 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
807 struct npa_aq_enq_req *req;
810 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
811 req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
812 req->ctype = NPA_AQ_CTYPE_AURA;
813 req->op = NPA_AQ_INSTOP_LOCK;
815 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
817 /* The shared memory buffer can be full.
820 otx2_mbox_msg_send(npa_lf->mbox, 0);
821 rc = otx2_mbox_wait_for_rsp(npa_lf->mbox, 0);
823 otx2_err("Failed to LOCK AURA context");
827 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
829 otx2_err("Failed to LOCK POOL context");
834 req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
835 req->ctype = NPA_AQ_CTYPE_POOL;
836 req->op = NPA_AQ_INSTOP_LOCK;
838 rc = otx2_mbox_process(npa_lf->mbox);
840 otx2_err("Unable to lock POOL in NDC");
848 nix_sqb_unlock(struct rte_mempool *mp)
850 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
851 struct npa_aq_enq_req *req;
854 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
855 req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
856 req->ctype = NPA_AQ_CTYPE_AURA;
857 req->op = NPA_AQ_INSTOP_UNLOCK;
859 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
861 /* The shared memory buffer can be full.
864 otx2_mbox_msg_send(npa_lf->mbox, 0);
865 rc = otx2_mbox_wait_for_rsp(npa_lf->mbox, 0);
867 otx2_err("Failed to UNLOCK AURA context");
871 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
873 otx2_err("Failed to UNLOCK POOL context");
877 req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
878 req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
879 req->ctype = NPA_AQ_CTYPE_POOL;
880 req->op = NPA_AQ_INSTOP_UNLOCK;
882 rc = otx2_mbox_process(npa_lf->mbox);
884 otx2_err("Unable to UNLOCK AURA in NDC");
892 otx2_nix_enable_mseg_on_jumbo(struct otx2_eth_rxq *rxq)
894 struct rte_pktmbuf_pool_private *mbp_priv;
895 struct rte_eth_dev *eth_dev;
896 struct otx2_eth_dev *dev;
899 eth_dev = rxq->eth_dev;
900 dev = otx2_eth_pmd_priv(eth_dev);
902 /* Get rx buffer size */
903 mbp_priv = rte_mempool_get_priv(rxq->pool);
904 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
906 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buffsz) {
907 dev->rx_offloads |= DEV_RX_OFFLOAD_SCATTER;
908 dev->tx_offloads |= DEV_TX_OFFLOAD_MULTI_SEGS;
910 /* Setting up the rx[tx]_offload_flags due to change
911 * in rx[tx]_offloads.
913 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
914 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
919 nix_sq_init(struct otx2_eth_txq *txq)
921 struct otx2_eth_dev *dev = txq->dev;
922 struct otx2_mbox *mbox = dev->mbox;
923 struct nix_aq_enq_req *sq;
928 if (txq->sqb_pool->pool_id == 0)
931 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
933 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
937 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
939 sq->ctype = NIX_AQ_CTYPE_SQ;
940 sq->op = NIX_AQ_INSTOP_INIT;
941 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
944 sq->sq.smq_rr_quantum = rr_quantum;
945 sq->sq.default_chan = dev->tx_chan_base;
946 sq->sq.sqe_stype = NIX_STYPE_STF;
948 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
949 sq->sq.sqe_stype = NIX_STYPE_STP;
951 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
952 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
953 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
954 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
955 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
957 /* Many to one reduction */
958 sq->sq.qint_idx = txq->sq % dev->qints;
960 rc = otx2_mbox_process(mbox);
964 if (dev->lock_tx_ctx) {
965 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
967 sq->ctype = NIX_AQ_CTYPE_SQ;
968 sq->op = NIX_AQ_INSTOP_LOCK;
970 rc = otx2_mbox_process(mbox);
977 nix_sq_uninit(struct otx2_eth_txq *txq)
979 struct otx2_eth_dev *dev = txq->dev;
980 struct otx2_mbox *mbox = dev->mbox;
981 struct ndc_sync_op *ndc_req;
982 struct nix_aq_enq_rsp *rsp;
983 struct nix_aq_enq_req *aq;
984 uint16_t sqes_per_sqb;
988 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
990 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
992 aq->ctype = NIX_AQ_CTYPE_SQ;
993 aq->op = NIX_AQ_INSTOP_READ;
995 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
999 /* Check if sq is already cleaned up */
1004 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
1006 aq->ctype = NIX_AQ_CTYPE_SQ;
1007 aq->op = NIX_AQ_INSTOP_WRITE;
1009 aq->sq_mask.ena = ~aq->sq_mask.ena;
1012 rc = otx2_mbox_process(mbox);
1016 if (dev->lock_tx_ctx) {
1018 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
1020 aq->ctype = NIX_AQ_CTYPE_SQ;
1021 aq->op = NIX_AQ_INSTOP_UNLOCK;
1023 rc = otx2_mbox_process(mbox);
1027 nix_sqb_unlock(txq->sqb_pool);
1030 /* Read SQ and free sqb's */
1031 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
1033 aq->ctype = NIX_AQ_CTYPE_SQ;
1034 aq->op = NIX_AQ_INSTOP_READ;
1036 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1040 if (aq->sq.smq_pend)
1041 otx2_err("SQ has pending sqe's");
1043 count = aq->sq.sqb_count;
1044 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
1045 /* Free SQB's that are used */
1046 sqb_buf = (void *)rsp->sq.head_sqb;
1050 next_sqb = *(void **)((uintptr_t)sqb_buf + (uint32_t)
1051 ((sqes_per_sqb - 1) *
1052 nix_sq_max_sqe_sz(txq)));
1053 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
1059 /* Free next to use sqb */
1060 if (rsp->sq.next_sqb)
1061 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
1064 /* Sync NDC-NIX-TX for LF */
1065 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
1066 ndc_req->nix_lf_tx_sync = 1;
1067 rc = otx2_mbox_process(mbox);
1069 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
1075 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
1077 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
1078 struct npa_aq_enq_req *aura_req;
1080 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
1081 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
1082 aura_req->ctype = NPA_AQ_CTYPE_AURA;
1083 aura_req->op = NPA_AQ_INSTOP_WRITE;
1085 aura_req->aura.limit = nb_sqb_bufs;
1086 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
1088 return otx2_mbox_process(npa_lf->mbox);
1092 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
1094 struct otx2_eth_dev *dev = txq->dev;
1095 uint16_t sqes_per_sqb, nb_sqb_bufs;
1096 char name[RTE_MEMPOOL_NAMESIZE];
1097 struct rte_mempool_objsz sz;
1098 struct npa_aura_s *aura;
1099 uint32_t tmp, blk_sz;
1101 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
1102 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
1103 blk_sz = dev->sqb_size;
1105 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
1106 sqes_per_sqb = (dev->sqb_size / 8) / 16;
1108 sqes_per_sqb = (dev->sqb_size / 8) / 8;
1110 nb_sqb_bufs = nb_desc / sqes_per_sqb;
1111 /* Clamp up to devarg passed SQB count */
1112 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_DEF_SQB,
1113 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
1115 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
1117 MEMPOOL_F_NO_SPREAD);
1118 txq->nb_sqb_bufs = nb_sqb_bufs;
1119 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
1120 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
1121 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
1122 txq->nb_sqb_bufs_adj =
1123 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
1125 if (txq->sqb_pool == NULL) {
1126 otx2_err("Failed to allocate sqe mempool");
1130 memset(aura, 0, sizeof(*aura));
1132 aura->fc_addr = txq->fc_iova;
1133 aura->fc_hyst_bits = 0; /* Store count on all updates */
1134 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
1135 otx2_err("Failed to set ops for sqe mempool");
1138 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
1139 otx2_err("Failed to populate sqe mempool");
1143 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
1144 if (dev->sqb_size != sz.elt_size) {
1145 otx2_err("sqe pool block size is not expected %d != %d",
1146 dev->sqb_size, tmp);
1150 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
1151 if (dev->lock_tx_ctx)
1152 nix_sqb_lock(txq->sqb_pool);
1160 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
1162 struct nix_send_ext_s *send_hdr_ext;
1163 struct nix_send_hdr_s *send_hdr;
1164 struct nix_send_mem_s *send_mem;
1165 union nix_send_sg_s *sg;
1167 /* Initialize the fields based on basic single segment packet */
1168 memset(&txq->cmd, 0, sizeof(txq->cmd));
1170 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
1171 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
1172 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
1173 send_hdr->w0.sizem1 = 2;
1175 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
1176 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
1177 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
1178 /* Default: one seg packet would have:
1179 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
1182 send_hdr->w0.sizem1 = 3;
1183 send_hdr_ext->w0.tstmp = 1;
1185 /* To calculate the offset for send_mem,
1186 * send_hdr->w0.sizem1 * 2
1188 send_mem = (struct nix_send_mem_s *)(txq->cmd +
1189 (send_hdr->w0.sizem1 << 1));
1190 send_mem->subdc = NIX_SUBDC_MEM;
1191 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
1192 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
1194 sg = (union nix_send_sg_s *)&txq->cmd[4];
1196 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
1197 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
1198 send_hdr->w0.sizem1 = 1;
1199 sg = (union nix_send_sg_s *)&txq->cmd[2];
1202 send_hdr->w0.sq = txq->sq;
1203 sg->subdc = NIX_SUBDC_SG;
1205 sg->ld_type = NIX_SENDLDTYPE_LDD;
1211 otx2_nix_tx_queue_release(void *_txq)
1213 struct otx2_eth_txq *txq = _txq;
1214 struct rte_eth_dev *eth_dev;
1219 eth_dev = txq->dev->eth_dev;
1221 otx2_nix_dbg("Releasing txq %u", txq->sq);
1223 /* Flush and disable tm */
1224 otx2_nix_sq_flush_pre(txq, eth_dev->data->dev_started);
1226 /* Free sqb's and disable sq */
1229 if (txq->sqb_pool) {
1230 rte_mempool_free(txq->sqb_pool);
1231 txq->sqb_pool = NULL;
1233 otx2_nix_sq_flush_post(txq);
1239 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
1240 uint16_t nb_desc, unsigned int socket_id,
1241 const struct rte_eth_txconf *tx_conf)
1243 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1244 const struct rte_memzone *fc;
1245 struct otx2_eth_txq *txq;
1251 /* Compile time check to make sure all fast path elements in a CL */
1252 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
1254 if (tx_conf->tx_deferred_start) {
1255 otx2_err("Tx deferred start is not supported");
1259 /* Free memory prior to re-allocation if needed. */
1260 if (eth_dev->data->tx_queues[sq] != NULL) {
1261 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
1262 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
1263 eth_dev->data->tx_queues[sq] = NULL;
1266 /* Find the expected offloads for this queue */
1267 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
1269 /* Allocating tx queue data structure */
1270 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
1271 OTX2_ALIGN, socket_id);
1273 otx2_err("Failed to alloc txq=%d", sq);
1279 txq->sqb_pool = NULL;
1280 txq->offloads = offloads;
1281 dev->tx_offloads |= offloads;
1284 * Allocate memory for flow control updates from HW.
1285 * Alloc one cache line, so that fits all FC_STYPE modes.
1287 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
1288 OTX2_ALIGN + sizeof(struct npa_aura_s),
1289 OTX2_ALIGN, dev->node);
1291 otx2_err("Failed to allocate mem for fcmem");
1295 txq->fc_iova = fc->iova;
1296 txq->fc_mem = fc->addr;
1298 /* Initialize the aura sqb pool */
1299 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
1301 otx2_err("Failed to alloc sqe pool rc=%d", rc);
1305 /* Initialize the SQ */
1306 rc = nix_sq_init(txq);
1308 otx2_err("Failed to init sq=%d context", sq);
1312 txq->fc_cache_pkts = 0;
1313 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
1314 /* Evenly distribute LMT slot for each sq */
1315 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
1317 txq->qconf.socket_id = socket_id;
1318 txq->qconf.nb_desc = nb_desc;
1319 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
1321 otx2_nix_form_default_desc(txq);
1323 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
1324 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
1325 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
1326 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
1327 eth_dev->data->tx_queues[sq] = txq;
1328 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
1332 otx2_nix_tx_queue_release(txq);
1338 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1340 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1341 struct otx2_eth_qconf *tx_qconf = NULL;
1342 struct otx2_eth_qconf *rx_qconf = NULL;
1343 struct otx2_eth_txq **txq;
1344 struct otx2_eth_rxq **rxq;
1345 int i, nb_rxq, nb_txq;
1347 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1348 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1350 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1351 if (tx_qconf == NULL) {
1352 otx2_err("Failed to allocate memory for tx_qconf");
1356 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1357 if (rx_qconf == NULL) {
1358 otx2_err("Failed to allocate memory for rx_qconf");
1362 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1363 for (i = 0; i < nb_txq; i++) {
1364 if (txq[i] == NULL) {
1365 tx_qconf[i].valid = false;
1366 otx2_info("txq[%d] is already released", i);
1369 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1370 tx_qconf[i].valid = true;
1371 otx2_nix_tx_queue_release(txq[i]);
1372 eth_dev->data->tx_queues[i] = NULL;
1375 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1376 for (i = 0; i < nb_rxq; i++) {
1377 if (rxq[i] == NULL) {
1378 rx_qconf[i].valid = false;
1379 otx2_info("rxq[%d] is already released", i);
1382 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1383 rx_qconf[i].valid = true;
1384 otx2_nix_rx_queue_release(rxq[i]);
1385 eth_dev->data->rx_queues[i] = NULL;
1388 dev->tx_qconf = tx_qconf;
1389 dev->rx_qconf = rx_qconf;
1400 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1402 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1403 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1404 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1405 struct otx2_eth_txq **txq;
1406 struct otx2_eth_rxq **rxq;
1407 int rc, i, nb_rxq, nb_txq;
1409 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1410 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1413 /* Setup tx & rx queues with previous configuration so
1414 * that the queues can be functional in cases like ports
1415 * are started without re configuring queues.
1417 * Usual re config sequence is like below:
1418 * port_configure() {
1423 * queue_configure() {
1430 * In some application's control path, queue_configure() would
1431 * NOT be invoked for TXQs/RXQs in port_configure().
1432 * In such cases, queues can be functional after start as the
1433 * queues are already setup in port_configure().
1435 for (i = 0; i < nb_txq; i++) {
1436 if (!tx_qconf[i].valid)
1438 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1439 tx_qconf[i].socket_id,
1440 &tx_qconf[i].conf.tx);
1442 otx2_err("Failed to setup tx queue rc=%d", rc);
1443 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1444 for (i -= 1; i >= 0; i--)
1445 otx2_nix_tx_queue_release(txq[i]);
1450 free(tx_qconf); tx_qconf = NULL;
1452 for (i = 0; i < nb_rxq; i++) {
1453 if (!rx_qconf[i].valid)
1455 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1456 rx_qconf[i].socket_id,
1457 &rx_qconf[i].conf.rx,
1458 rx_qconf[i].mempool);
1460 otx2_err("Failed to setup rx queue rc=%d", rc);
1461 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1462 for (i -= 1; i >= 0; i--)
1463 otx2_nix_rx_queue_release(rxq[i]);
1464 goto release_tx_queues;
1468 free(rx_qconf); rx_qconf = NULL;
1473 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1474 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1475 otx2_nix_tx_queue_release(txq[i]);
1486 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1488 RTE_SET_USED(queue);
1489 RTE_SET_USED(mbufs);
1496 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1498 /* These dummy functions are required for supporting
1499 * some applications which reconfigure queues without
1500 * stopping tx burst and rx burst threads(eg kni app)
1501 * When the queues context is saved, txq/rxqs are released
1502 * which caused app crash since rx/tx burst is still
1503 * on different lcores
1505 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1506 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1511 nix_lso_tcp(struct nix_lso_format_cfg *req, bool v4)
1513 volatile struct nix_lso_format *field;
1515 /* Format works only with TCP packet marked by OL3/OL4 */
1516 field = (volatile struct nix_lso_format *)&req->fields[0];
1517 req->field_mask = NIX_LSO_FIELD_MASK;
1518 /* Outer IPv4/IPv6 */
1519 field->layer = NIX_TXLAYER_OL3;
1520 field->offset = v4 ? 2 : 4;
1521 field->sizem1 = 1; /* 2B */
1522 field->alg = NIX_LSOALG_ADD_PAYLEN;
1526 field->layer = NIX_TXLAYER_OL3;
1529 /* Incremented linearly per segment */
1530 field->alg = NIX_LSOALG_ADD_SEGNUM;
1534 /* TCP sequence number update */
1535 field->layer = NIX_TXLAYER_OL4;
1537 field->sizem1 = 3; /* 4 bytes */
1538 field->alg = NIX_LSOALG_ADD_OFFSET;
1540 /* TCP flags field */
1541 field->layer = NIX_TXLAYER_OL4;
1544 field->alg = NIX_LSOALG_TCP_FLAGS;
1549 nix_lso_udp_tun_tcp(struct nix_lso_format_cfg *req,
1550 bool outer_v4, bool inner_v4)
1552 volatile struct nix_lso_format *field;
1554 field = (volatile struct nix_lso_format *)&req->fields[0];
1555 req->field_mask = NIX_LSO_FIELD_MASK;
1556 /* Outer IPv4/IPv6 len */
1557 field->layer = NIX_TXLAYER_OL3;
1558 field->offset = outer_v4 ? 2 : 4;
1559 field->sizem1 = 1; /* 2B */
1560 field->alg = NIX_LSOALG_ADD_PAYLEN;
1564 field->layer = NIX_TXLAYER_OL3;
1567 /* Incremented linearly per segment */
1568 field->alg = NIX_LSOALG_ADD_SEGNUM;
1572 /* Outer UDP length */
1573 field->layer = NIX_TXLAYER_OL4;
1576 field->alg = NIX_LSOALG_ADD_PAYLEN;
1579 /* Inner IPv4/IPv6 */
1580 field->layer = NIX_TXLAYER_IL3;
1581 field->offset = inner_v4 ? 2 : 4;
1582 field->sizem1 = 1; /* 2B */
1583 field->alg = NIX_LSOALG_ADD_PAYLEN;
1587 field->layer = NIX_TXLAYER_IL3;
1590 /* Incremented linearly per segment */
1591 field->alg = NIX_LSOALG_ADD_SEGNUM;
1595 /* TCP sequence number update */
1596 field->layer = NIX_TXLAYER_IL4;
1598 field->sizem1 = 3; /* 4 bytes */
1599 field->alg = NIX_LSOALG_ADD_OFFSET;
1602 /* TCP flags field */
1603 field->layer = NIX_TXLAYER_IL4;
1606 field->alg = NIX_LSOALG_TCP_FLAGS;
1611 nix_lso_tun_tcp(struct nix_lso_format_cfg *req,
1612 bool outer_v4, bool inner_v4)
1614 volatile struct nix_lso_format *field;
1616 field = (volatile struct nix_lso_format *)&req->fields[0];
1617 req->field_mask = NIX_LSO_FIELD_MASK;
1618 /* Outer IPv4/IPv6 len */
1619 field->layer = NIX_TXLAYER_OL3;
1620 field->offset = outer_v4 ? 2 : 4;
1621 field->sizem1 = 1; /* 2B */
1622 field->alg = NIX_LSOALG_ADD_PAYLEN;
1626 field->layer = NIX_TXLAYER_OL3;
1629 /* Incremented linearly per segment */
1630 field->alg = NIX_LSOALG_ADD_SEGNUM;
1634 /* Inner IPv4/IPv6 */
1635 field->layer = NIX_TXLAYER_IL3;
1636 field->offset = inner_v4 ? 2 : 4;
1637 field->sizem1 = 1; /* 2B */
1638 field->alg = NIX_LSOALG_ADD_PAYLEN;
1642 field->layer = NIX_TXLAYER_IL3;
1645 /* Incremented linearly per segment */
1646 field->alg = NIX_LSOALG_ADD_SEGNUM;
1650 /* TCP sequence number update */
1651 field->layer = NIX_TXLAYER_IL4;
1653 field->sizem1 = 3; /* 4 bytes */
1654 field->alg = NIX_LSOALG_ADD_OFFSET;
1657 /* TCP flags field */
1658 field->layer = NIX_TXLAYER_IL4;
1661 field->alg = NIX_LSOALG_TCP_FLAGS;
1666 nix_setup_lso_formats(struct otx2_eth_dev *dev)
1668 struct otx2_mbox *mbox = dev->mbox;
1669 struct nix_lso_format_cfg_rsp *rsp;
1670 struct nix_lso_format_cfg *req;
1674 /* Skip if TSO was not requested */
1675 if (!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F))
1680 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1681 nix_lso_tcp(req, true);
1682 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1686 base = rsp->lso_format_idx;
1687 if (base != NIX_LSO_FORMAT_IDX_TSOV4)
1689 dev->lso_base_idx = base;
1690 otx2_nix_dbg("tcpv4 lso fmt=%u", base);
1696 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1697 nix_lso_tcp(req, false);
1698 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1702 if (rsp->lso_format_idx != base + 1)
1704 otx2_nix_dbg("tcpv6 lso fmt=%u\n", base + 1);
1707 * IPv4/UDP/TUN HDR/IPv4/TCP LSO
1709 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1710 nix_lso_udp_tun_tcp(req, true, true);
1711 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1715 if (rsp->lso_format_idx != base + 2)
1717 otx2_nix_dbg("udp tun v4v4 fmt=%u\n", base + 2);
1720 * IPv4/UDP/TUN HDR/IPv6/TCP LSO
1722 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1723 nix_lso_udp_tun_tcp(req, true, false);
1724 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1728 if (rsp->lso_format_idx != base + 3)
1730 otx2_nix_dbg("udp tun v4v6 fmt=%u\n", base + 3);
1733 * IPv6/UDP/TUN HDR/IPv4/TCP LSO
1735 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1736 nix_lso_udp_tun_tcp(req, false, true);
1737 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1741 if (rsp->lso_format_idx != base + 4)
1743 otx2_nix_dbg("udp tun v6v4 fmt=%u\n", base + 4);
1746 * IPv6/UDP/TUN HDR/IPv6/TCP LSO
1748 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1749 nix_lso_udp_tun_tcp(req, false, false);
1750 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1753 if (rsp->lso_format_idx != base + 5)
1755 otx2_nix_dbg("udp tun v6v6 fmt=%u\n", base + 5);
1758 * IPv4/TUN HDR/IPv4/TCP LSO
1760 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1761 nix_lso_tun_tcp(req, true, true);
1762 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1766 if (rsp->lso_format_idx != base + 6)
1768 otx2_nix_dbg("tun v4v4 fmt=%u\n", base + 6);
1771 * IPv4/TUN HDR/IPv6/TCP LSO
1773 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1774 nix_lso_tun_tcp(req, true, false);
1775 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1779 if (rsp->lso_format_idx != base + 7)
1781 otx2_nix_dbg("tun v4v6 fmt=%u\n", base + 7);
1784 * IPv6/TUN HDR/IPv4/TCP LSO
1786 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1787 nix_lso_tun_tcp(req, false, true);
1788 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1792 if (rsp->lso_format_idx != base + 8)
1794 otx2_nix_dbg("tun v6v4 fmt=%u\n", base + 8);
1797 * IPv6/TUN HDR/IPv6/TCP LSO
1799 req = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);
1800 nix_lso_tun_tcp(req, false, false);
1801 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1804 if (rsp->lso_format_idx != base + 9)
1806 otx2_nix_dbg("tun v6v6 fmt=%u\n", base + 9);
1811 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1813 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1814 struct rte_eth_dev_data *data = eth_dev->data;
1815 struct rte_eth_conf *conf = &data->dev_conf;
1816 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1817 struct rte_eth_txmode *txmode = &conf->txmode;
1818 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1819 struct rte_ether_addr *ea;
1820 uint8_t nb_rxq, nb_txq;
1826 if (rte_eal_has_hugepages() == 0) {
1827 otx2_err("Huge page is not configured");
1828 goto fail_configure;
1831 if (conf->dcb_capability_en == 1) {
1832 otx2_err("dcb enable is not supported");
1833 goto fail_configure;
1836 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1837 otx2_err("Flow director is not supported");
1838 goto fail_configure;
1841 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1842 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1843 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1844 goto fail_configure;
1847 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1848 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1849 goto fail_configure;
1852 if (otx2_dev_is_Ax(dev) &&
1853 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1854 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1855 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1856 otx2_err("Outer IP and SCTP checksum unsupported");
1857 goto fail_configure;
1860 /* Free the resources allocated from the previous configure */
1861 if (dev->configured == 1) {
1862 otx2_eth_sec_fini(eth_dev);
1863 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1864 otx2_nix_vlan_fini(eth_dev);
1865 otx2_nix_mc_addr_list_uninstall(eth_dev);
1866 otx2_flow_free_all_resources(dev);
1867 oxt2_nix_unregister_queue_irqs(eth_dev);
1868 if (eth_dev->data->dev_conf.intr_conf.rxq)
1869 oxt2_nix_unregister_cq_irqs(eth_dev);
1870 nix_set_nop_rxtx_function(eth_dev);
1871 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1873 goto fail_configure;
1874 otx2_nix_tm_fini(eth_dev);
1878 dev->rx_offloads = rxmode->offloads;
1879 dev->tx_offloads = txmode->offloads;
1880 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1881 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1882 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1884 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1885 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1887 /* Alloc a nix lf */
1888 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1890 otx2_err("Failed to init nix_lf rc=%d", rc);
1894 otx2_nix_err_intr_enb_dis(eth_dev, true);
1895 otx2_nix_ras_intr_enb_dis(eth_dev, true);
1898 dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
1899 otx2_err("Both PTP and switch header enabled");
1903 rc = nix_lf_switch_header_type_enable(dev, true);
1905 otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
1909 rc = nix_setup_lso_formats(dev);
1911 otx2_err("failed to setup nix lso format fields, rc=%d", rc);
1916 rc = otx2_nix_rss_config(eth_dev);
1918 otx2_err("Failed to configure rss rc=%d", rc);
1922 /* Init the default TM scheduler hierarchy */
1923 rc = otx2_nix_tm_init_default(eth_dev);
1925 otx2_err("Failed to init traffic manager rc=%d", rc);
1929 rc = otx2_nix_vlan_offload_init(eth_dev);
1931 otx2_err("Failed to init vlan offload rc=%d", rc);
1935 /* Register queue IRQs */
1936 rc = oxt2_nix_register_queue_irqs(eth_dev);
1938 otx2_err("Failed to register queue interrupts rc=%d", rc);
1942 /* Register cq IRQs */
1943 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1944 if (eth_dev->data->nb_rx_queues > dev->cints) {
1945 otx2_err("Rx interrupt cannot be enabled, rxq > %d",
1949 /* Rx interrupt feature cannot work with vector mode because,
1950 * vector mode doesn't process packets unless min 4 pkts are
1951 * received, while cq interrupts are generated even for 1 pkt
1954 dev->scalar_ena = true;
1956 rc = oxt2_nix_register_cq_irqs(eth_dev);
1958 otx2_err("Failed to register CQ interrupts rc=%d", rc);
1963 /* Configure loop back mode */
1964 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1966 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1970 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1972 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1976 /* Enable security */
1977 rc = otx2_eth_sec_init(eth_dev);
1981 rc = otx2_nix_flow_ctrl_init(eth_dev);
1983 otx2_err("Failed to init flow ctrl mode %d", rc);
1987 rc = otx2_nix_mc_addr_list_install(eth_dev);
1989 otx2_err("Failed to install mc address list rc=%d", rc);
1994 * Restore queue config when reconfigure followed by
1995 * reconfigure and no queue configure invoked from application case.
1997 if (dev->configured == 1) {
1998 rc = nix_restore_queue_cfg(eth_dev);
2000 goto uninstall_mc_list;
2003 /* Update the mac address */
2004 ea = eth_dev->data->mac_addrs;
2005 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
2006 if (rte_is_zero_ether_addr(ea))
2007 rte_eth_random_addr((uint8_t *)ea);
2009 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
2011 /* Apply new link configurations if changed */
2012 rc = otx2_apply_link_speed(eth_dev);
2014 otx2_err("Failed to set link configuration");
2015 goto uninstall_mc_list;
2018 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
2019 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
2020 " rx_flags=0x%x tx_flags=0x%x",
2021 eth_dev->data->port_id, ea_fmt, nb_rxq,
2022 nb_txq, dev->rx_offloads, dev->tx_offloads,
2023 dev->rx_offload_flags, dev->tx_offload_flags);
2026 dev->configured = 1;
2027 dev->configured_nb_rx_qs = data->nb_rx_queues;
2028 dev->configured_nb_tx_qs = data->nb_tx_queues;
2032 otx2_nix_mc_addr_list_uninstall(eth_dev);
2034 otx2_eth_sec_fini(eth_dev);
2036 oxt2_nix_unregister_cq_irqs(eth_dev);
2038 oxt2_nix_unregister_queue_irqs(eth_dev);
2040 otx2_nix_vlan_fini(eth_dev);
2042 otx2_nix_tm_fini(eth_dev);
2046 dev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);
2047 dev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);
2049 dev->configured = 0;
2054 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
2056 struct rte_eth_dev_data *data = eth_dev->data;
2057 struct otx2_eth_txq *txq;
2060 txq = eth_dev->data->tx_queues[qidx];
2062 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
2065 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
2067 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
2072 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
2079 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
2081 struct rte_eth_dev_data *data = eth_dev->data;
2082 struct otx2_eth_txq *txq;
2085 txq = eth_dev->data->tx_queues[qidx];
2087 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
2090 txq->fc_cache_pkts = 0;
2092 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
2094 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
2099 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
2106 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
2108 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
2109 struct rte_eth_dev_data *data = eth_dev->data;
2112 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
2115 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
2117 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
2121 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
2128 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
2130 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
2131 struct rte_eth_dev_data *data = eth_dev->data;
2134 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
2137 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
2139 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
2143 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
2150 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
2152 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2153 struct rte_mbuf *rx_pkts[32];
2154 struct otx2_eth_rxq *rxq;
2155 int count, i, j, rc;
2157 nix_lf_switch_header_type_enable(dev, false);
2158 nix_cgx_stop_link_event(dev);
2159 npc_rx_disable(dev);
2161 /* Stop rx queues and free up pkts pending */
2162 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2163 rc = otx2_nix_rx_queue_stop(eth_dev, i);
2167 rxq = eth_dev->data->rx_queues[i];
2168 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
2170 for (j = 0; j < count; j++)
2171 rte_pktmbuf_free(rx_pkts[j]);
2172 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
2176 /* Stop tx queues */
2177 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
2178 otx2_nix_tx_queue_stop(eth_dev, i);
2184 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
2186 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2189 /* MTU recalculate should be avoided here if PTP is enabled by PF, as
2190 * otx2_nix_recalc_mtu would be invoked during otx2_nix_ptp_enable_vf
2193 if (eth_dev->data->nb_rx_queues != 0 && !otx2_ethdev_is_ptp_en(dev)) {
2194 rc = otx2_nix_recalc_mtu(eth_dev);
2199 /* Start rx queues */
2200 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2201 rc = otx2_nix_rx_queue_start(eth_dev, i);
2206 /* Start tx queues */
2207 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
2208 rc = otx2_nix_tx_queue_start(eth_dev, i);
2213 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
2215 otx2_err("Failed to update flow ctrl mode %d", rc);
2219 /* Enable PTP if it was requested by the app or if it is already
2220 * enabled in PF owning this VF
2222 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
2223 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
2224 otx2_ethdev_is_ptp_en(dev))
2225 otx2_nix_timesync_enable(eth_dev);
2227 otx2_nix_timesync_disable(eth_dev);
2229 /* Update VF about data off shifted by 8 bytes if PTP already
2230 * enabled in PF owning this VF
2232 if (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))
2233 otx2_nix_ptp_enable_vf(eth_dev);
2235 if (dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F) {
2236 rc = rte_mbuf_dyn_rx_timestamp_register(
2237 &dev->tstamp.tstamp_dynfield_offset,
2238 &dev->tstamp.rx_tstamp_dynflag);
2240 otx2_err("Failed to register Rx timestamp field/flag");
2245 rc = npc_rx_enable(dev);
2247 otx2_err("Failed to enable NPC rx %d", rc);
2251 otx2_nix_toggle_flag_link_cfg(dev, true);
2253 rc = nix_cgx_start_link_event(dev);
2255 otx2_err("Failed to start cgx link event %d", rc);
2259 otx2_nix_toggle_flag_link_cfg(dev, false);
2260 otx2_eth_set_tx_function(eth_dev);
2261 otx2_eth_set_rx_function(eth_dev);
2266 npc_rx_disable(dev);
2267 otx2_nix_toggle_flag_link_cfg(dev, false);
2271 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
2272 static int otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
2274 /* Initialize and register driver with DPDK Application */
2275 static const struct eth_dev_ops otx2_eth_dev_ops = {
2276 .dev_infos_get = otx2_nix_info_get,
2277 .dev_configure = otx2_nix_configure,
2278 .link_update = otx2_nix_link_update,
2279 .tx_queue_setup = otx2_nix_tx_queue_setup,
2280 .tx_queue_release = otx2_nix_tx_queue_release,
2281 .tm_ops_get = otx2_nix_tm_ops_get,
2282 .rx_queue_setup = otx2_nix_rx_queue_setup,
2283 .rx_queue_release = otx2_nix_rx_queue_release,
2284 .dev_start = otx2_nix_dev_start,
2285 .dev_stop = otx2_nix_dev_stop,
2286 .dev_close = otx2_nix_dev_close,
2287 .tx_queue_start = otx2_nix_tx_queue_start,
2288 .tx_queue_stop = otx2_nix_tx_queue_stop,
2289 .rx_queue_start = otx2_nix_rx_queue_start,
2290 .rx_queue_stop = otx2_nix_rx_queue_stop,
2291 .dev_set_link_up = otx2_nix_dev_set_link_up,
2292 .dev_set_link_down = otx2_nix_dev_set_link_down,
2293 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
2294 .dev_ptypes_set = otx2_nix_ptypes_set,
2295 .dev_reset = otx2_nix_dev_reset,
2296 .stats_get = otx2_nix_dev_stats_get,
2297 .stats_reset = otx2_nix_dev_stats_reset,
2298 .get_reg = otx2_nix_dev_get_reg,
2299 .mtu_set = otx2_nix_mtu_set,
2300 .mac_addr_add = otx2_nix_mac_addr_add,
2301 .mac_addr_remove = otx2_nix_mac_addr_del,
2302 .mac_addr_set = otx2_nix_mac_addr_set,
2303 .set_mc_addr_list = otx2_nix_set_mc_addr_list,
2304 .promiscuous_enable = otx2_nix_promisc_enable,
2305 .promiscuous_disable = otx2_nix_promisc_disable,
2306 .allmulticast_enable = otx2_nix_allmulticast_enable,
2307 .allmulticast_disable = otx2_nix_allmulticast_disable,
2308 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
2309 .reta_update = otx2_nix_dev_reta_update,
2310 .reta_query = otx2_nix_dev_reta_query,
2311 .rss_hash_update = otx2_nix_rss_hash_update,
2312 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
2313 .xstats_get = otx2_nix_xstats_get,
2314 .xstats_get_names = otx2_nix_xstats_get_names,
2315 .xstats_reset = otx2_nix_xstats_reset,
2316 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
2317 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
2318 .rxq_info_get = otx2_nix_rxq_info_get,
2319 .txq_info_get = otx2_nix_txq_info_get,
2320 .rx_burst_mode_get = otx2_rx_burst_mode_get,
2321 .tx_burst_mode_get = otx2_tx_burst_mode_get,
2322 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
2323 .set_queue_rate_limit = otx2_nix_tm_set_queue_rate_limit,
2324 .pool_ops_supported = otx2_nix_pool_ops_supported,
2325 .filter_ctrl = otx2_nix_dev_filter_ctrl,
2326 .get_module_info = otx2_nix_get_module_info,
2327 .get_module_eeprom = otx2_nix_get_module_eeprom,
2328 .fw_version_get = otx2_nix_fw_version_get,
2329 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
2330 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
2331 .timesync_enable = otx2_nix_timesync_enable,
2332 .timesync_disable = otx2_nix_timesync_disable,
2333 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
2334 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
2335 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
2336 .timesync_read_time = otx2_nix_timesync_read_time,
2337 .timesync_write_time = otx2_nix_timesync_write_time,
2338 .vlan_offload_set = otx2_nix_vlan_offload_set,
2339 .vlan_filter_set = otx2_nix_vlan_filter_set,
2340 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
2341 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
2342 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
2343 .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
2344 .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
2345 .read_clock = otx2_nix_read_clock,
2349 nix_lf_attach(struct otx2_eth_dev *dev)
2351 struct otx2_mbox *mbox = dev->mbox;
2352 struct rsrc_attach_req *req;
2354 /* Attach NIX(lf) */
2355 req = otx2_mbox_alloc_msg_attach_resources(mbox);
2359 return otx2_mbox_process(mbox);
2363 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
2365 struct otx2_mbox *mbox = dev->mbox;
2366 struct msix_offset_rsp *msix_rsp;
2369 /* Get NPA and NIX MSIX vector offsets */
2370 otx2_mbox_alloc_msg_msix_offset(mbox);
2372 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
2374 dev->nix_msixoff = msix_rsp->nix_msixoff;
2380 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
2382 struct rsrc_detach_req *req;
2384 req = otx2_mbox_alloc_msg_detach_resources(mbox);
2386 /* Detach all except npa lf */
2387 req->partial = true;
2394 return otx2_mbox_process(mbox);
2398 otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
2400 if (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||
2401 pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2406 static inline uint64_t
2407 nix_get_blkaddr(struct otx2_eth_dev *dev)
2411 /* Reading the discovery register to know which NIX is the LF
2414 reg = otx2_read64(dev->bar2 +
2415 RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_NIX0));
2417 return reg & 0x1FFULL ? RVU_BLOCK_ADDR_NIX0 : RVU_BLOCK_ADDR_NIX1;
2421 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
2423 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2424 struct rte_pci_device *pci_dev;
2425 int rc, max_entries;
2427 eth_dev->dev_ops = &otx2_eth_dev_ops;
2428 eth_dev->rx_descriptor_done = otx2_nix_rx_descriptor_done;
2429 eth_dev->rx_queue_count = otx2_nix_rx_queue_count;
2430 eth_dev->rx_descriptor_status = otx2_nix_rx_descriptor_status;
2431 eth_dev->tx_descriptor_status = otx2_nix_tx_descriptor_status;
2433 /* For secondary processes, the primary has done all the work */
2434 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2435 /* Setup callbacks for secondary process */
2436 otx2_eth_set_tx_function(eth_dev);
2437 otx2_eth_set_rx_function(eth_dev);
2441 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2443 rte_eth_copy_pci_info(eth_dev, pci_dev);
2444 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2446 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
2447 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
2448 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
2450 /* Parse devargs string */
2451 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
2453 otx2_err("Failed to parse devargs rc=%d", rc);
2457 if (!dev->mbox_active) {
2458 /* Initialize the base otx2_dev object
2459 * only if already present
2461 rc = otx2_dev_init(pci_dev, dev);
2463 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
2467 if (otx2_eth_dev_is_sdp(pci_dev))
2468 dev->sdp_link = true;
2470 dev->sdp_link = false;
2471 /* Device generic callbacks */
2472 dev->ops = &otx2_dev_ops;
2473 dev->eth_dev = eth_dev;
2475 /* Grab the NPA LF if required */
2476 rc = otx2_npa_lf_init(pci_dev, dev);
2478 goto otx2_dev_uninit;
2480 dev->configured = 0;
2481 dev->drv_inited = true;
2482 dev->ptype_disable = 0;
2483 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
2486 rc = nix_lf_attach(dev);
2488 goto otx2_npa_uninit;
2490 dev->base = dev->bar2 + (nix_get_blkaddr(dev) << 20);
2492 /* Get NIX MSIX offset */
2493 rc = nix_lf_get_msix_offset(dev);
2495 goto otx2_npa_uninit;
2497 /* Register LF irq handlers */
2498 rc = otx2_nix_register_irqs(eth_dev);
2502 /* Get maximum number of supported MAC entries */
2503 max_entries = otx2_cgx_mac_max_entries_get(dev);
2504 if (max_entries < 0) {
2505 otx2_err("Failed to get max entries for mac addr");
2507 goto unregister_irq;
2510 /* For VFs, returned max_entries will be 0. But to keep default MAC
2511 * address, one entry must be allocated. So setting up to 1.
2513 if (max_entries == 0)
2516 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
2517 RTE_ETHER_ADDR_LEN, 0);
2518 if (eth_dev->data->mac_addrs == NULL) {
2519 otx2_err("Failed to allocate memory for mac addr");
2521 goto unregister_irq;
2524 dev->max_mac_entries = max_entries;
2526 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
2528 goto free_mac_addrs;
2530 /* Update the mac address */
2531 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
2533 /* Also sync same MAC address to CGX table */
2534 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
2536 /* Initialize the tm data structures */
2537 otx2_nix_tm_conf_init(eth_dev);
2539 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
2540 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
2542 if (otx2_dev_is_96xx_A0(dev) ||
2543 otx2_dev_is_95xx_Ax(dev)) {
2544 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
2545 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
2548 /* Create security ctx */
2549 rc = otx2_eth_sec_ctx_create(eth_dev);
2551 goto free_mac_addrs;
2552 dev->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
2553 dev->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
2555 /* Initialize rte-flow */
2556 rc = otx2_flow_init(dev);
2558 goto sec_ctx_destroy;
2560 otx2_nix_mc_filter_init(dev);
2562 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
2563 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
2564 eth_dev->data->port_id, dev->pf, dev->vf,
2565 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
2566 dev->rx_offload_capa, dev->tx_offload_capa);
2570 otx2_eth_sec_ctx_destroy(eth_dev);
2572 rte_free(eth_dev->data->mac_addrs);
2574 otx2_nix_unregister_irqs(eth_dev);
2576 otx2_eth_dev_lf_detach(dev->mbox);
2580 otx2_dev_fini(pci_dev, dev);
2582 otx2_err("Failed to init nix eth_dev rc=%d", rc);
2587 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
2589 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
2590 struct rte_pci_device *pci_dev;
2593 /* Nothing to be done for secondary processes */
2594 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2597 /* Clear the flag since we are closing down */
2598 dev->configured = 0;
2600 /* Disable nix bpid config */
2601 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
2603 npc_rx_disable(dev);
2605 /* Disable vlan offloads */
2606 otx2_nix_vlan_fini(eth_dev);
2608 /* Disable other rte_flow entries */
2609 otx2_flow_fini(dev);
2611 /* Free multicast filter list */
2612 otx2_nix_mc_filter_fini(dev);
2614 /* Disable PTP if already enabled */
2615 if (otx2_ethdev_is_ptp_en(dev))
2616 otx2_nix_timesync_disable(eth_dev);
2618 nix_cgx_stop_link_event(dev);
2621 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
2622 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
2623 eth_dev->data->tx_queues[i] = NULL;
2625 eth_dev->data->nb_tx_queues = 0;
2627 /* Free up RQ's and CQ's */
2628 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
2629 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
2630 eth_dev->data->rx_queues[i] = NULL;
2632 eth_dev->data->nb_rx_queues = 0;
2634 /* Free tm resources */
2635 rc = otx2_nix_tm_fini(eth_dev);
2637 otx2_err("Failed to cleanup tm, rc=%d", rc);
2639 /* Unregister queue irqs */
2640 oxt2_nix_unregister_queue_irqs(eth_dev);
2642 /* Unregister cq irqs */
2643 if (eth_dev->data->dev_conf.intr_conf.rxq)
2644 oxt2_nix_unregister_cq_irqs(eth_dev);
2646 rc = nix_lf_free(dev);
2648 otx2_err("Failed to free nix lf, rc=%d", rc);
2650 rc = otx2_npa_lf_fini();
2652 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
2654 /* Disable security */
2655 otx2_eth_sec_fini(eth_dev);
2657 /* Destroy security ctx */
2658 otx2_eth_sec_ctx_destroy(eth_dev);
2660 rte_free(eth_dev->data->mac_addrs);
2661 eth_dev->data->mac_addrs = NULL;
2662 dev->drv_inited = false;
2664 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2665 otx2_nix_unregister_irqs(eth_dev);
2667 rc = otx2_eth_dev_lf_detach(dev->mbox);
2669 otx2_err("Failed to detach resources, rc=%d", rc);
2671 /* Check if mbox close is needed */
2675 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
2676 /* Will be freed later by PMD */
2677 eth_dev->data->dev_private = NULL;
2681 otx2_dev_fini(pci_dev, dev);
2686 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
2688 otx2_eth_dev_uninit(eth_dev, true);
2693 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
2697 rc = otx2_eth_dev_uninit(eth_dev, false);
2701 return otx2_eth_dev_init(eth_dev);
2705 nix_remove(struct rte_pci_device *pci_dev)
2707 struct rte_eth_dev *eth_dev;
2708 struct otx2_idev_cfg *idev;
2709 struct otx2_dev *otx2_dev;
2712 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
2714 /* Cleanup eth dev */
2715 rc = otx2_eth_dev_uninit(eth_dev, true);
2719 rte_eth_dev_release_port(eth_dev);
2722 /* Nothing to be done for secondary processes */
2723 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2726 /* Check for common resources */
2727 idev = otx2_intra_dev_get_cfg();
2728 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
2731 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
2733 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
2736 /* Safe to cleanup mbox as no more users */
2737 otx2_dev_fini(pci_dev, otx2_dev);
2742 otx2_info("%s: common resource in use by other devices", pci_dev->name);
2747 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
2751 RTE_SET_USED(pci_drv);
2753 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
2756 /* On error on secondary, recheck if port exists in primary or
2757 * in mid of detach state.
2759 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
2760 if (!rte_eth_dev_allocated(pci_dev->device.name))
2765 static const struct rte_pci_id pci_nix_map[] = {
2767 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
2770 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
2773 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2774 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
2777 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2778 PCI_DEVID_OCTEONTX2_RVU_SDP_PF)
2781 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2782 PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
2789 static struct rte_pci_driver pci_nix = {
2790 .id_table = pci_nix_map,
2791 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
2792 RTE_PCI_DRV_INTR_LSC,
2794 .remove = nix_remove,
2797 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
2798 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
2799 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");