1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_ethdev_pci.h>
7 #include <rte_malloc.h>
9 #include "otx2_ethdev.h"
12 otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev)
14 RTE_SET_USED(eth_dev);
18 otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev)
20 RTE_SET_USED(eth_dev);
23 static inline uint64_t
24 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
26 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
28 if (otx2_dev_is_vf(dev))
29 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
34 static inline uint64_t
35 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
39 return NIX_TX_OFFLOAD_CAPA;
43 nix_lf_free(struct otx2_eth_dev *dev)
45 struct otx2_mbox *mbox = dev->mbox;
46 struct nix_lf_free_req *req;
47 struct ndc_sync_op *ndc_req;
50 /* Sync NDC-NIX for LF */
51 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
52 ndc_req->nix_lf_tx_sync = 1;
53 ndc_req->nix_lf_rx_sync = 1;
54 rc = otx2_mbox_process(mbox);
56 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
58 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
59 /* Let AF driver free all this nix lf's
60 * NPC entries allocated using NPC MBOX.
64 return otx2_mbox_process(mbox);
68 nix_lf_attach(struct otx2_eth_dev *dev)
70 struct otx2_mbox *mbox = dev->mbox;
71 struct rsrc_attach_req *req;
74 req = otx2_mbox_alloc_msg_attach_resources(mbox);
78 return otx2_mbox_process(mbox);
82 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
84 struct otx2_mbox *mbox = dev->mbox;
85 struct msix_offset_rsp *msix_rsp;
88 /* Get NPA and NIX MSIX vector offsets */
89 otx2_mbox_alloc_msg_msix_offset(mbox);
91 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
93 dev->nix_msixoff = msix_rsp->nix_msixoff;
99 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
101 struct rsrc_detach_req *req;
103 req = otx2_mbox_alloc_msg_detach_resources(mbox);
105 /* Detach all except npa lf */
113 return otx2_mbox_process(mbox);
117 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
119 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
120 struct rte_pci_device *pci_dev;
123 /* For secondary processes, the primary has done all the work */
124 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
125 /* Setup callbacks for secondary process */
126 otx2_eth_set_tx_function(eth_dev);
127 otx2_eth_set_rx_function(eth_dev);
131 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
133 rte_eth_copy_pci_info(eth_dev, pci_dev);
134 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
136 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
137 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
138 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
140 /* Parse devargs string */
141 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
143 otx2_err("Failed to parse devargs rc=%d", rc);
147 if (!dev->mbox_active) {
148 /* Initialize the base otx2_dev object
149 * only if already present
151 rc = otx2_dev_init(pci_dev, dev);
153 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
158 /* Grab the NPA LF if required */
159 rc = otx2_npa_lf_init(pci_dev, dev);
161 goto otx2_dev_uninit;
164 dev->drv_inited = true;
165 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
166 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
169 rc = nix_lf_attach(dev);
171 goto otx2_npa_uninit;
173 /* Get NIX MSIX offset */
174 rc = nix_lf_get_msix_offset(dev);
176 goto otx2_npa_uninit;
178 /* Get maximum number of supported MAC entries */
179 max_entries = otx2_cgx_mac_max_entries_get(dev);
180 if (max_entries < 0) {
181 otx2_err("Failed to get max entries for mac addr");
186 /* For VFs, returned max_entries will be 0. But to keep default MAC
187 * address, one entry must be allocated. So setting up to 1.
189 if (max_entries == 0)
192 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
193 RTE_ETHER_ADDR_LEN, 0);
194 if (eth_dev->data->mac_addrs == NULL) {
195 otx2_err("Failed to allocate memory for mac addr");
200 dev->max_mac_entries = max_entries;
202 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
206 /* Update the mac address */
207 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
209 /* Also sync same MAC address to CGX table */
210 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
212 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
213 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
215 if (otx2_dev_is_A0(dev)) {
216 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
217 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
220 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
221 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
222 eth_dev->data->port_id, dev->pf, dev->vf,
223 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
224 dev->rx_offload_capa, dev->tx_offload_capa);
228 rte_free(eth_dev->data->mac_addrs);
230 otx2_eth_dev_lf_detach(dev->mbox);
234 otx2_dev_fini(pci_dev, dev);
236 otx2_err("Failed to init nix eth_dev rc=%d", rc);
241 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
243 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
244 struct rte_pci_device *pci_dev;
247 /* Nothing to be done for secondary processes */
248 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
251 rc = nix_lf_free(dev);
253 otx2_err("Failed to free nix lf, rc=%d", rc);
255 rc = otx2_npa_lf_fini();
257 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
259 rte_free(eth_dev->data->mac_addrs);
260 eth_dev->data->mac_addrs = NULL;
261 dev->drv_inited = false;
263 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
265 rc = otx2_eth_dev_lf_detach(dev->mbox);
267 otx2_err("Failed to detach resources, rc=%d", rc);
269 /* Check if mbox close is needed */
273 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
274 /* Will be freed later by PMD */
275 eth_dev->data->dev_private = NULL;
279 otx2_dev_fini(pci_dev, dev);
284 nix_remove(struct rte_pci_device *pci_dev)
286 struct rte_eth_dev *eth_dev;
287 struct otx2_idev_cfg *idev;
288 struct otx2_dev *otx2_dev;
291 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
293 /* Cleanup eth dev */
294 rc = otx2_eth_dev_uninit(eth_dev, true);
298 rte_eth_dev_pci_release(eth_dev);
301 /* Nothing to be done for secondary processes */
302 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
305 /* Check for common resources */
306 idev = otx2_intra_dev_get_cfg();
307 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
310 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
312 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
315 /* Safe to cleanup mbox as no more users */
316 otx2_dev_fini(pci_dev, otx2_dev);
321 otx2_info("%s: common resource in use by other devices", pci_dev->name);
326 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
330 RTE_SET_USED(pci_drv);
332 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
335 /* On error on secondary, recheck if port exists in primary or
336 * in mid of detach state.
338 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
339 if (!rte_eth_dev_allocated(pci_dev->device.name))
344 static const struct rte_pci_id pci_nix_map[] = {
346 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
349 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
352 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
353 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
360 static struct rte_pci_driver pci_nix = {
361 .id_table = pci_nix_map,
362 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA |
363 RTE_PCI_DRV_INTR_LSC,
365 .remove = nix_remove,
368 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
369 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
370 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");