1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
8 #include <rte_ethdev_pci.h>
10 #include <rte_malloc.h>
12 #include <rte_mbuf_pool_ops.h>
13 #include <rte_mempool.h>
15 #include "otx2_ethdev.h"
17 static inline uint64_t
18 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
20 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
22 if (otx2_dev_is_vf(dev))
23 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
28 static inline uint64_t
29 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
33 return NIX_TX_OFFLOAD_CAPA;
36 static const struct otx2_dev_ops otx2_dev_ops = {
37 .link_status_update = otx2_eth_dev_link_status_update,
38 .ptp_info_update = otx2_eth_dev_ptp_info_update
42 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
44 struct otx2_mbox *mbox = dev->mbox;
45 struct nix_lf_alloc_req *req;
46 struct nix_lf_alloc_rsp *rsp;
49 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
53 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
54 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
55 req->xqe_sz = NIX_XQESZ_W16;
56 req->rss_sz = dev->rss_info.rss_size;
57 req->rss_grps = NIX_RSS_GRPS;
58 req->npa_func = otx2_npa_pf_func_get();
59 req->sso_func = otx2_sso_pf_func_get();
60 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
61 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
62 DEV_RX_OFFLOAD_UDP_CKSUM)) {
63 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
64 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
67 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
71 dev->sqb_size = rsp->sqb_size;
72 dev->tx_chan_base = rsp->tx_chan_base;
73 dev->rx_chan_base = rsp->rx_chan_base;
74 dev->rx_chan_cnt = rsp->rx_chan_cnt;
75 dev->tx_chan_cnt = rsp->tx_chan_cnt;
76 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
77 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
78 dev->lf_tx_stats = rsp->lf_tx_stats;
79 dev->lf_rx_stats = rsp->lf_rx_stats;
80 dev->cints = rsp->cints;
81 dev->qints = rsp->qints;
82 dev->npc_flow.channel = dev->rx_chan_base;
88 nix_lf_free(struct otx2_eth_dev *dev)
90 struct otx2_mbox *mbox = dev->mbox;
91 struct nix_lf_free_req *req;
92 struct ndc_sync_op *ndc_req;
95 /* Sync NDC-NIX for LF */
96 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
97 ndc_req->nix_lf_tx_sync = 1;
98 ndc_req->nix_lf_rx_sync = 1;
99 rc = otx2_mbox_process(mbox);
101 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
103 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
104 /* Let AF driver free all this nix lf's
105 * NPC entries allocated using NPC MBOX.
109 return otx2_mbox_process(mbox);
113 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
115 struct otx2_mbox *mbox = dev->mbox;
117 if (otx2_dev_is_vf(dev))
120 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
122 return otx2_mbox_process(mbox);
126 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
128 struct otx2_mbox *mbox = dev->mbox;
130 if (otx2_dev_is_vf(dev))
133 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
135 return otx2_mbox_process(mbox);
139 npc_rx_enable(struct otx2_eth_dev *dev)
141 struct otx2_mbox *mbox = dev->mbox;
143 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
145 return otx2_mbox_process(mbox);
149 npc_rx_disable(struct otx2_eth_dev *dev)
151 struct otx2_mbox *mbox = dev->mbox;
153 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
155 return otx2_mbox_process(mbox);
159 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
161 struct otx2_mbox *mbox = dev->mbox;
163 if (otx2_dev_is_vf(dev))
166 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
168 return otx2_mbox_process(mbox);
172 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
174 struct otx2_mbox *mbox = dev->mbox;
176 if (otx2_dev_is_vf(dev))
180 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
182 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
184 return otx2_mbox_process(mbox);
188 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
190 struct otx2_mbox *mbox = dev->mbox;
192 if (otx2_dev_is_vf(dev))
195 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
197 return otx2_mbox_process(mbox);
201 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
207 static inline uint32_t
208 nix_qsize_to_val(enum nix_q_size_e qsize)
210 return (16UL << (qsize * 2));
213 static inline enum nix_q_size_e
214 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
218 if (otx2_ethdev_fixup_is_min_4k_q(dev))
223 for (; i < nix_q_size_max; i++)
224 if (val <= nix_qsize_to_val(i))
227 if (i >= nix_q_size_max)
228 i = nix_q_size_max - 1;
234 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
235 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
237 struct otx2_mbox *mbox = dev->mbox;
238 const struct rte_memzone *rz;
239 uint32_t ring_size, cq_size;
240 struct nix_aq_enq_req *aq;
245 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
246 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
247 NIX_CQ_ALIGN, dev->node);
249 otx2_err("Failed to allocate mem for cq hw ring");
253 memset(rz->addr, 0, rz->len);
254 rxq->desc = (uintptr_t)rz->addr;
255 rxq->qmask = cq_size - 1;
257 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
259 aq->ctype = NIX_AQ_CTYPE_CQ;
260 aq->op = NIX_AQ_INSTOP_INIT;
264 aq->cq.qsize = rxq->qsize;
265 aq->cq.base = rz->iova;
266 aq->cq.avg_level = 0xff;
267 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
268 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
270 /* TX pause frames enable flowctrl on RX side */
271 if (dev->fc_info.tx_pause) {
272 /* Single bpid is allocated for all rx channels for now */
273 aq->cq.bpid = dev->fc_info.bpid[0];
274 aq->cq.bp = NIX_CQ_BP_LEVEL;
278 /* Many to one reduction */
279 aq->cq.qint_idx = qid % dev->qints;
280 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
281 aq->cq.cint_idx = qid;
283 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
284 uint16_t min_rx_drop;
285 const float rx_cq_skid = 1024 * 256;
287 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
288 aq->cq.drop = min_rx_drop;
292 rc = otx2_mbox_process(mbox);
294 otx2_err("Failed to init cq context");
298 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
300 aq->ctype = NIX_AQ_CTYPE_RQ;
301 aq->op = NIX_AQ_INSTOP_INIT;
304 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
306 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
307 first_skip = (sizeof(struct rte_mbuf));
308 first_skip += RTE_PKTMBUF_HEADROOM;
309 first_skip += rte_pktmbuf_priv_size(mp);
310 rxq->data_off = first_skip;
312 first_skip /= 8; /* Expressed in number of dwords */
313 aq->rq.first_skip = first_skip;
314 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
315 aq->rq.flow_tagw = 32; /* 32-bits */
316 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
317 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
318 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
319 aq->rq.lpb_sizem1 /= 8;
320 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
322 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
323 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
324 aq->rq.rq_int_ena = 0;
325 /* Many to one reduction */
326 aq->rq.qint_idx = qid % dev->qints;
328 if (otx2_ethdev_fixup_is_limit_cq_full(dev))
329 aq->rq.xqe_drop_ena = 1;
331 rc = otx2_mbox_process(mbox);
333 otx2_err("Failed to init rq context");
343 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
344 struct otx2_eth_rxq *rxq, const bool enb)
346 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
347 struct otx2_mbox *mbox = dev->mbox;
348 struct nix_aq_enq_req *aq;
350 /* Pkts will be dropped silently if RQ is disabled */
351 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
353 aq->ctype = NIX_AQ_CTYPE_RQ;
354 aq->op = NIX_AQ_INSTOP_WRITE;
357 aq->rq_mask.ena = ~(aq->rq_mask.ena);
359 return otx2_mbox_process(mbox);
363 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
365 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
366 struct otx2_mbox *mbox = dev->mbox;
367 struct nix_aq_enq_req *aq;
370 /* RQ is already disabled */
372 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
374 aq->ctype = NIX_AQ_CTYPE_CQ;
375 aq->op = NIX_AQ_INSTOP_WRITE;
378 aq->cq_mask.ena = ~(aq->cq_mask.ena);
380 rc = otx2_mbox_process(mbox);
382 otx2_err("Failed to disable cq context");
390 nix_get_data_off(struct otx2_eth_dev *dev)
392 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
396 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
398 struct rte_mbuf mb_def;
401 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
402 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
403 offsetof(struct rte_mbuf, data_off) != 2);
404 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
405 offsetof(struct rte_mbuf, data_off) != 4);
406 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
407 offsetof(struct rte_mbuf, data_off) != 6);
409 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
410 mb_def.port = port_id;
411 rte_mbuf_refcnt_set(&mb_def, 1);
413 /* Prevent compiler reordering: rearm_data covers previous fields */
414 rte_compiler_barrier();
415 tmp = (uint64_t *)&mb_def.rearm_data;
421 otx2_nix_rx_queue_release(void *rx_queue)
423 struct otx2_eth_rxq *rxq = rx_queue;
428 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
429 nix_cq_rq_uninit(rxq->eth_dev, rxq);
434 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
435 uint16_t nb_desc, unsigned int socket,
436 const struct rte_eth_rxconf *rx_conf,
437 struct rte_mempool *mp)
439 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
440 struct rte_mempool_ops *ops;
441 struct otx2_eth_rxq *rxq;
442 const char *platform_ops;
443 enum nix_q_size_e qsize;
449 /* Compile time check to make sure all fast path elements in a CL */
450 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
453 if (rx_conf->rx_deferred_start == 1) {
454 otx2_err("Deferred Rx start is not supported");
458 platform_ops = rte_mbuf_platform_mempool_ops();
459 /* This driver needs octeontx2_npa mempool ops to work */
460 ops = rte_mempool_get_ops(mp->ops_index);
461 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
462 otx2_err("mempool ops should be of octeontx2_npa type");
466 if (mp->pool_id == 0) {
467 otx2_err("Invalid pool_id");
471 /* Free memory prior to re-allocation if needed */
472 if (eth_dev->data->rx_queues[rq] != NULL) {
473 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
474 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
475 eth_dev->data->rx_queues[rq] = NULL;
478 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
479 dev->rx_offloads |= offloads;
481 /* Find the CQ queue size */
482 qsize = nix_qsize_clampup_get(dev, nb_desc);
483 /* Allocate rxq memory */
484 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
486 otx2_err("Failed to allocate rq=%d", rq);
491 rxq->eth_dev = eth_dev;
493 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
494 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
495 rxq->wdata = (uint64_t)rq << 32;
496 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
497 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
498 eth_dev->data->port_id);
499 rxq->offloads = offloads;
501 rxq->qlen = nix_qsize_to_val(qsize);
503 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
504 rxq->tstamp = &dev->tstamp;
506 /* Alloc completion queue */
507 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
509 otx2_err("Failed to allocate rxq=%u", rq);
513 rxq->qconf.socket_id = socket;
514 rxq->qconf.nb_desc = nb_desc;
515 rxq->qconf.mempool = mp;
516 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
518 nix_rx_queue_reset(rxq);
519 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
520 rq, mp->name, qsize, nb_desc, rxq->qlen);
522 eth_dev->data->rx_queues[rq] = rxq;
523 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
527 otx2_nix_rx_queue_release(rxq);
532 static inline uint8_t
533 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
536 * Maximum three segments can be supported with W8, Choose
537 * NIX_MAXSQESZ_W16 for multi segment offload.
539 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
540 return NIX_MAXSQESZ_W16;
542 return NIX_MAXSQESZ_W8;
546 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
548 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
549 struct rte_eth_dev_data *data = eth_dev->data;
550 struct rte_eth_conf *conf = &data->dev_conf;
551 struct rte_eth_rxmode *rxmode = &conf->rxmode;
554 if (rxmode->mq_mode == ETH_MQ_RX_RSS)
555 flags |= NIX_RX_OFFLOAD_RSS_F;
557 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
558 DEV_RX_OFFLOAD_UDP_CKSUM))
559 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
561 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
562 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
563 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
565 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
566 flags |= NIX_RX_MULTI_SEG_F;
568 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
569 DEV_RX_OFFLOAD_QINQ_STRIP))
570 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
572 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
573 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
579 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
581 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
582 uint64_t conf = dev->tx_offloads;
585 /* Fastpath is dependent on these enums */
586 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
587 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
588 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
590 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
591 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
592 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
594 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
595 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
596 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
598 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
599 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
600 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
601 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
602 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
604 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
605 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
607 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
608 flags |= NIX_TX_MULTI_SEG_F;
614 nix_sq_init(struct otx2_eth_txq *txq)
616 struct otx2_eth_dev *dev = txq->dev;
617 struct otx2_mbox *mbox = dev->mbox;
618 struct nix_aq_enq_req *sq;
623 if (txq->sqb_pool->pool_id == 0)
626 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
628 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
632 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
634 sq->ctype = NIX_AQ_CTYPE_SQ;
635 sq->op = NIX_AQ_INSTOP_INIT;
636 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
639 sq->sq.smq_rr_quantum = rr_quantum;
640 sq->sq.default_chan = dev->tx_chan_base;
641 sq->sq.sqe_stype = NIX_STYPE_STF;
643 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
644 sq->sq.sqe_stype = NIX_STYPE_STP;
646 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
647 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
648 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
649 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
650 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
652 /* Many to one reduction */
653 sq->sq.qint_idx = txq->sq % dev->qints;
655 return otx2_mbox_process(mbox);
659 nix_sq_uninit(struct otx2_eth_txq *txq)
661 struct otx2_eth_dev *dev = txq->dev;
662 struct otx2_mbox *mbox = dev->mbox;
663 struct ndc_sync_op *ndc_req;
664 struct nix_aq_enq_rsp *rsp;
665 struct nix_aq_enq_req *aq;
666 uint16_t sqes_per_sqb;
670 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
672 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
674 aq->ctype = NIX_AQ_CTYPE_SQ;
675 aq->op = NIX_AQ_INSTOP_READ;
677 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
681 /* Check if sq is already cleaned up */
686 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
688 aq->ctype = NIX_AQ_CTYPE_SQ;
689 aq->op = NIX_AQ_INSTOP_WRITE;
691 aq->sq_mask.ena = ~aq->sq_mask.ena;
694 rc = otx2_mbox_process(mbox);
698 /* Read SQ and free sqb's */
699 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
701 aq->ctype = NIX_AQ_CTYPE_SQ;
702 aq->op = NIX_AQ_INSTOP_READ;
704 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
709 otx2_err("SQ has pending sqe's");
711 count = aq->sq.sqb_count;
712 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
713 /* Free SQB's that are used */
714 sqb_buf = (void *)rsp->sq.head_sqb;
718 next_sqb = *(void **)((uintptr_t)sqb_buf + ((sqes_per_sqb - 1) *
719 nix_sq_max_sqe_sz(txq)));
720 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
726 /* Free next to use sqb */
727 if (rsp->sq.next_sqb)
728 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
731 /* Sync NDC-NIX-TX for LF */
732 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
733 ndc_req->nix_lf_tx_sync = 1;
734 rc = otx2_mbox_process(mbox);
736 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
742 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
744 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
745 struct npa_aq_enq_req *aura_req;
747 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
748 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
749 aura_req->ctype = NPA_AQ_CTYPE_AURA;
750 aura_req->op = NPA_AQ_INSTOP_WRITE;
752 aura_req->aura.limit = nb_sqb_bufs;
753 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
755 return otx2_mbox_process(npa_lf->mbox);
759 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
761 struct otx2_eth_dev *dev = txq->dev;
762 uint16_t sqes_per_sqb, nb_sqb_bufs;
763 char name[RTE_MEMPOOL_NAMESIZE];
764 struct rte_mempool_objsz sz;
765 struct npa_aura_s *aura;
766 uint32_t tmp, blk_sz;
768 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
769 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
770 blk_sz = dev->sqb_size;
772 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
773 sqes_per_sqb = (dev->sqb_size / 8) / 16;
775 sqes_per_sqb = (dev->sqb_size / 8) / 8;
777 nb_sqb_bufs = nb_desc / sqes_per_sqb;
778 /* Clamp up to devarg passed SQB count */
779 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_MIN_SQB,
780 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
782 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
784 MEMPOOL_F_NO_SPREAD);
785 txq->nb_sqb_bufs = nb_sqb_bufs;
786 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
787 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
788 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
789 txq->nb_sqb_bufs_adj =
790 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
792 if (txq->sqb_pool == NULL) {
793 otx2_err("Failed to allocate sqe mempool");
797 memset(aura, 0, sizeof(*aura));
799 aura->fc_addr = txq->fc_iova;
800 aura->fc_hyst_bits = 0; /* Store count on all updates */
801 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
802 otx2_err("Failed to set ops for sqe mempool");
805 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
806 otx2_err("Failed to populate sqe mempool");
810 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
811 if (dev->sqb_size != sz.elt_size) {
812 otx2_err("sqe pool block size is not expected %d != %d",
817 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
825 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
827 struct nix_send_ext_s *send_hdr_ext;
828 struct nix_send_hdr_s *send_hdr;
829 struct nix_send_mem_s *send_mem;
830 union nix_send_sg_s *sg;
832 /* Initialize the fields based on basic single segment packet */
833 memset(&txq->cmd, 0, sizeof(txq->cmd));
835 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
836 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
837 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
838 send_hdr->w0.sizem1 = 2;
840 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
841 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
842 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
843 /* Default: one seg packet would have:
844 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
847 send_hdr->w0.sizem1 = 3;
848 send_hdr_ext->w0.tstmp = 1;
850 /* To calculate the offset for send_mem,
851 * send_hdr->w0.sizem1 * 2
853 send_mem = (struct nix_send_mem_s *)(txq->cmd +
854 (send_hdr->w0.sizem1 << 1));
855 send_mem->subdc = NIX_SUBDC_MEM;
857 send_mem->wmem = 0x1;
858 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
859 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
861 sg = (union nix_send_sg_s *)&txq->cmd[4];
863 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
864 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
865 send_hdr->w0.sizem1 = 1;
866 sg = (union nix_send_sg_s *)&txq->cmd[2];
869 send_hdr->w0.sq = txq->sq;
870 sg->subdc = NIX_SUBDC_SG;
872 sg->ld_type = NIX_SENDLDTYPE_LDD;
878 otx2_nix_tx_queue_release(void *_txq)
880 struct otx2_eth_txq *txq = _txq;
881 struct rte_eth_dev *eth_dev;
886 eth_dev = txq->dev->eth_dev;
888 otx2_nix_dbg("Releasing txq %u", txq->sq);
890 /* Flush and disable tm */
891 otx2_nix_tm_sw_xoff(txq, eth_dev->data->dev_started);
893 /* Free sqb's and disable sq */
897 rte_mempool_free(txq->sqb_pool);
898 txq->sqb_pool = NULL;
905 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
906 uint16_t nb_desc, unsigned int socket_id,
907 const struct rte_eth_txconf *tx_conf)
909 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
910 const struct rte_memzone *fc;
911 struct otx2_eth_txq *txq;
917 /* Compile time check to make sure all fast path elements in a CL */
918 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
920 if (tx_conf->tx_deferred_start) {
921 otx2_err("Tx deferred start is not supported");
925 /* Free memory prior to re-allocation if needed. */
926 if (eth_dev->data->tx_queues[sq] != NULL) {
927 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
928 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
929 eth_dev->data->tx_queues[sq] = NULL;
932 /* Find the expected offloads for this queue */
933 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
935 /* Allocating tx queue data structure */
936 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
937 OTX2_ALIGN, socket_id);
939 otx2_err("Failed to alloc txq=%d", sq);
945 txq->sqb_pool = NULL;
946 txq->offloads = offloads;
947 dev->tx_offloads |= offloads;
950 * Allocate memory for flow control updates from HW.
951 * Alloc one cache line, so that fits all FC_STYPE modes.
953 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
954 OTX2_ALIGN + sizeof(struct npa_aura_s),
955 OTX2_ALIGN, dev->node);
957 otx2_err("Failed to allocate mem for fcmem");
961 txq->fc_iova = fc->iova;
962 txq->fc_mem = fc->addr;
964 /* Initialize the aura sqb pool */
965 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
967 otx2_err("Failed to alloc sqe pool rc=%d", rc);
971 /* Initialize the SQ */
972 rc = nix_sq_init(txq);
974 otx2_err("Failed to init sq=%d context", sq);
978 txq->fc_cache_pkts = 0;
979 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
980 /* Evenly distribute LMT slot for each sq */
981 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
983 txq->qconf.socket_id = socket_id;
984 txq->qconf.nb_desc = nb_desc;
985 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
987 otx2_nix_form_default_desc(txq);
989 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
990 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
991 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
992 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
993 eth_dev->data->tx_queues[sq] = txq;
994 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
998 otx2_nix_tx_queue_release(txq);
1004 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1006 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1007 struct otx2_eth_qconf *tx_qconf = NULL;
1008 struct otx2_eth_qconf *rx_qconf = NULL;
1009 struct otx2_eth_txq **txq;
1010 struct otx2_eth_rxq **rxq;
1011 int i, nb_rxq, nb_txq;
1013 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1014 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1016 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1017 if (tx_qconf == NULL) {
1018 otx2_err("Failed to allocate memory for tx_qconf");
1022 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1023 if (rx_qconf == NULL) {
1024 otx2_err("Failed to allocate memory for rx_qconf");
1028 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1029 for (i = 0; i < nb_txq; i++) {
1030 if (txq[i] == NULL) {
1031 otx2_err("txq[%d] is already released", i);
1034 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1035 otx2_nix_tx_queue_release(txq[i]);
1036 eth_dev->data->tx_queues[i] = NULL;
1039 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1040 for (i = 0; i < nb_rxq; i++) {
1041 if (rxq[i] == NULL) {
1042 otx2_err("rxq[%d] is already released", i);
1045 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1046 otx2_nix_rx_queue_release(rxq[i]);
1047 eth_dev->data->rx_queues[i] = NULL;
1050 dev->tx_qconf = tx_qconf;
1051 dev->rx_qconf = rx_qconf;
1064 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1066 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1067 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1068 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1069 struct otx2_eth_txq **txq;
1070 struct otx2_eth_rxq **rxq;
1071 int rc, i, nb_rxq, nb_txq;
1073 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1074 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1077 /* Setup tx & rx queues with previous configuration so
1078 * that the queues can be functional in cases like ports
1079 * are started without re configuring queues.
1081 * Usual re config sequence is like below:
1082 * port_configure() {
1087 * queue_configure() {
1094 * In some application's control path, queue_configure() would
1095 * NOT be invoked for TXQs/RXQs in port_configure().
1096 * In such cases, queues can be functional after start as the
1097 * queues are already setup in port_configure().
1099 for (i = 0; i < nb_txq; i++) {
1100 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1101 tx_qconf[i].socket_id,
1102 &tx_qconf[i].conf.tx);
1104 otx2_err("Failed to setup tx queue rc=%d", rc);
1105 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1106 for (i -= 1; i >= 0; i--)
1107 otx2_nix_tx_queue_release(txq[i]);
1112 free(tx_qconf); tx_qconf = NULL;
1114 for (i = 0; i < nb_rxq; i++) {
1115 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1116 rx_qconf[i].socket_id,
1117 &rx_qconf[i].conf.rx,
1118 rx_qconf[i].mempool);
1120 otx2_err("Failed to setup rx queue rc=%d", rc);
1121 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1122 for (i -= 1; i >= 0; i--)
1123 otx2_nix_rx_queue_release(rxq[i]);
1124 goto release_tx_queues;
1128 free(rx_qconf); rx_qconf = NULL;
1133 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1134 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1135 otx2_nix_tx_queue_release(txq[i]);
1146 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1148 RTE_SET_USED(queue);
1149 RTE_SET_USED(mbufs);
1156 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1158 /* These dummy functions are required for supporting
1159 * some applications which reconfigure queues without
1160 * stopping tx burst and rx burst threads(eg kni app)
1161 * When the queues context is saved, txq/rxqs are released
1162 * which caused app crash since rx/tx burst is still
1163 * on different lcores
1165 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1166 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1171 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1173 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1174 struct rte_eth_dev_data *data = eth_dev->data;
1175 struct rte_eth_conf *conf = &data->dev_conf;
1176 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1177 struct rte_eth_txmode *txmode = &conf->txmode;
1178 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1179 struct rte_ether_addr *ea;
1180 uint8_t nb_rxq, nb_txq;
1186 if (rte_eal_has_hugepages() == 0) {
1187 otx2_err("Huge page is not configured");
1191 if (rte_eal_iova_mode() != RTE_IOVA_VA) {
1192 otx2_err("iova mode should be va");
1196 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1197 otx2_err("Setting link speed/duplex not supported");
1201 if (conf->dcb_capability_en == 1) {
1202 otx2_err("dcb enable is not supported");
1206 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1207 otx2_err("Flow director is not supported");
1211 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1212 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1213 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1217 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1218 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1222 /* Free the resources allocated from the previous configure */
1223 if (dev->configured == 1) {
1224 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1225 otx2_nix_vlan_fini(eth_dev);
1226 otx2_flow_free_all_resources(dev);
1227 oxt2_nix_unregister_queue_irqs(eth_dev);
1228 if (eth_dev->data->dev_conf.intr_conf.rxq)
1229 oxt2_nix_unregister_cq_irqs(eth_dev);
1230 nix_set_nop_rxtx_function(eth_dev);
1231 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1234 otx2_nix_tm_fini(eth_dev);
1238 if (otx2_dev_is_Ax(dev) &&
1239 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1240 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1241 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1242 otx2_err("Outer IP and SCTP checksum unsupported");
1247 dev->rx_offloads = rxmode->offloads;
1248 dev->tx_offloads = txmode->offloads;
1249 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1250 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1251 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1253 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1254 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1256 /* Alloc a nix lf */
1257 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1259 otx2_err("Failed to init nix_lf rc=%d", rc);
1264 rc = otx2_nix_rss_config(eth_dev);
1266 otx2_err("Failed to configure rss rc=%d", rc);
1270 /* Init the default TM scheduler hierarchy */
1271 rc = otx2_nix_tm_init_default(eth_dev);
1273 otx2_err("Failed to init traffic manager rc=%d", rc);
1277 rc = otx2_nix_vlan_offload_init(eth_dev);
1279 otx2_err("Failed to init vlan offload rc=%d", rc);
1283 /* Register queue IRQs */
1284 rc = oxt2_nix_register_queue_irqs(eth_dev);
1286 otx2_err("Failed to register queue interrupts rc=%d", rc);
1290 /* Register cq IRQs */
1291 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1292 if (eth_dev->data->nb_rx_queues > dev->cints) {
1293 otx2_err("Rx interrupt cannot be enabled, rxq > %d",
1297 /* Rx interrupt feature cannot work with vector mode because,
1298 * vector mode doesn't process packets unless min 4 pkts are
1299 * received, while cq interrupts are generated even for 1 pkt
1302 dev->scalar_ena = true;
1304 rc = oxt2_nix_register_cq_irqs(eth_dev);
1306 otx2_err("Failed to register CQ interrupts rc=%d", rc);
1311 /* Configure loop back mode */
1312 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1314 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1318 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1320 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1324 /* Enable PTP if it was requested by the app or if it is already
1325 * enabled in PF owning this VF
1327 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
1328 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
1329 otx2_ethdev_is_ptp_en(dev))
1330 otx2_nix_timesync_enable(eth_dev);
1332 otx2_nix_timesync_disable(eth_dev);
1335 * Restore queue config when reconfigure followed by
1336 * reconfigure and no queue configure invoked from application case.
1338 if (dev->configured == 1) {
1339 rc = nix_restore_queue_cfg(eth_dev);
1344 /* Update the mac address */
1345 ea = eth_dev->data->mac_addrs;
1346 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1347 if (rte_is_zero_ether_addr(ea))
1348 rte_eth_random_addr((uint8_t *)ea);
1350 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1352 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1353 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1354 " rx_flags=0x%x tx_flags=0x%x",
1355 eth_dev->data->port_id, ea_fmt, nb_rxq,
1356 nb_txq, dev->rx_offloads, dev->tx_offloads,
1357 dev->rx_offload_flags, dev->tx_offload_flags);
1360 dev->configured = 1;
1361 dev->configured_nb_rx_qs = data->nb_rx_queues;
1362 dev->configured_nb_tx_qs = data->nb_tx_queues;
1366 rc = nix_lf_free(dev);
1372 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1374 struct rte_eth_dev_data *data = eth_dev->data;
1375 struct otx2_eth_txq *txq;
1378 txq = eth_dev->data->tx_queues[qidx];
1380 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1383 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1385 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1390 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1397 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1399 struct rte_eth_dev_data *data = eth_dev->data;
1400 struct otx2_eth_txq *txq;
1403 txq = eth_dev->data->tx_queues[qidx];
1405 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1408 txq->fc_cache_pkts = 0;
1410 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1412 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1417 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1424 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1426 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1427 struct rte_eth_dev_data *data = eth_dev->data;
1430 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1433 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1435 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1439 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1446 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1448 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1449 struct rte_eth_dev_data *data = eth_dev->data;
1452 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1455 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1457 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1461 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1468 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
1470 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1471 struct rte_mbuf *rx_pkts[32];
1472 struct otx2_eth_rxq *rxq;
1473 int count, i, j, rc;
1475 nix_cgx_stop_link_event(dev);
1476 npc_rx_disable(dev);
1478 /* Stop rx queues and free up pkts pending */
1479 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1480 rc = otx2_nix_rx_queue_stop(eth_dev, i);
1484 rxq = eth_dev->data->rx_queues[i];
1485 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1487 for (j = 0; j < count; j++)
1488 rte_pktmbuf_free(rx_pkts[j]);
1489 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1493 /* Stop tx queues */
1494 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1495 otx2_nix_tx_queue_stop(eth_dev, i);
1499 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
1501 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1504 if (eth_dev->data->nb_rx_queues != 0) {
1505 rc = otx2_nix_recalc_mtu(eth_dev);
1510 /* Start rx queues */
1511 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1512 rc = otx2_nix_rx_queue_start(eth_dev, i);
1517 /* Start tx queues */
1518 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1519 rc = otx2_nix_tx_queue_start(eth_dev, i);
1524 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
1526 otx2_err("Failed to update flow ctrl mode %d", rc);
1530 rc = npc_rx_enable(dev);
1532 otx2_err("Failed to enable NPC rx %d", rc);
1536 otx2_nix_toggle_flag_link_cfg(dev, true);
1538 rc = nix_cgx_start_link_event(dev);
1540 otx2_err("Failed to start cgx link event %d", rc);
1544 otx2_nix_toggle_flag_link_cfg(dev, false);
1545 otx2_eth_set_tx_function(eth_dev);
1546 otx2_eth_set_rx_function(eth_dev);
1551 npc_rx_disable(dev);
1552 otx2_nix_toggle_flag_link_cfg(dev, false);
1556 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
1557 static void otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
1559 /* Initialize and register driver with DPDK Application */
1560 static const struct eth_dev_ops otx2_eth_dev_ops = {
1561 .dev_infos_get = otx2_nix_info_get,
1562 .dev_configure = otx2_nix_configure,
1563 .link_update = otx2_nix_link_update,
1564 .tx_queue_setup = otx2_nix_tx_queue_setup,
1565 .tx_queue_release = otx2_nix_tx_queue_release,
1566 .rx_queue_setup = otx2_nix_rx_queue_setup,
1567 .rx_queue_release = otx2_nix_rx_queue_release,
1568 .dev_start = otx2_nix_dev_start,
1569 .dev_stop = otx2_nix_dev_stop,
1570 .dev_close = otx2_nix_dev_close,
1571 .tx_queue_start = otx2_nix_tx_queue_start,
1572 .tx_queue_stop = otx2_nix_tx_queue_stop,
1573 .rx_queue_start = otx2_nix_rx_queue_start,
1574 .rx_queue_stop = otx2_nix_rx_queue_stop,
1575 .dev_set_link_up = otx2_nix_dev_set_link_up,
1576 .dev_set_link_down = otx2_nix_dev_set_link_down,
1577 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
1578 .dev_reset = otx2_nix_dev_reset,
1579 .stats_get = otx2_nix_dev_stats_get,
1580 .stats_reset = otx2_nix_dev_stats_reset,
1581 .get_reg = otx2_nix_dev_get_reg,
1582 .mtu_set = otx2_nix_mtu_set,
1583 .mac_addr_add = otx2_nix_mac_addr_add,
1584 .mac_addr_remove = otx2_nix_mac_addr_del,
1585 .mac_addr_set = otx2_nix_mac_addr_set,
1586 .promiscuous_enable = otx2_nix_promisc_enable,
1587 .promiscuous_disable = otx2_nix_promisc_disable,
1588 .allmulticast_enable = otx2_nix_allmulticast_enable,
1589 .allmulticast_disable = otx2_nix_allmulticast_disable,
1590 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
1591 .reta_update = otx2_nix_dev_reta_update,
1592 .reta_query = otx2_nix_dev_reta_query,
1593 .rss_hash_update = otx2_nix_rss_hash_update,
1594 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
1595 .xstats_get = otx2_nix_xstats_get,
1596 .xstats_get_names = otx2_nix_xstats_get_names,
1597 .xstats_reset = otx2_nix_xstats_reset,
1598 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
1599 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
1600 .rxq_info_get = otx2_nix_rxq_info_get,
1601 .txq_info_get = otx2_nix_txq_info_get,
1602 .rx_queue_count = otx2_nix_rx_queue_count,
1603 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
1604 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
1605 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
1606 .pool_ops_supported = otx2_nix_pool_ops_supported,
1607 .filter_ctrl = otx2_nix_dev_filter_ctrl,
1608 .get_module_info = otx2_nix_get_module_info,
1609 .get_module_eeprom = otx2_nix_get_module_eeprom,
1610 .fw_version_get = otx2_nix_fw_version_get,
1611 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
1612 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
1613 .timesync_enable = otx2_nix_timesync_enable,
1614 .timesync_disable = otx2_nix_timesync_disable,
1615 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
1616 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
1617 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
1618 .timesync_read_time = otx2_nix_timesync_read_time,
1619 .timesync_write_time = otx2_nix_timesync_write_time,
1620 .vlan_offload_set = otx2_nix_vlan_offload_set,
1621 .vlan_filter_set = otx2_nix_vlan_filter_set,
1622 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
1623 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
1624 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
1625 .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
1626 .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
1630 nix_lf_attach(struct otx2_eth_dev *dev)
1632 struct otx2_mbox *mbox = dev->mbox;
1633 struct rsrc_attach_req *req;
1635 /* Attach NIX(lf) */
1636 req = otx2_mbox_alloc_msg_attach_resources(mbox);
1640 return otx2_mbox_process(mbox);
1644 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
1646 struct otx2_mbox *mbox = dev->mbox;
1647 struct msix_offset_rsp *msix_rsp;
1650 /* Get NPA and NIX MSIX vector offsets */
1651 otx2_mbox_alloc_msg_msix_offset(mbox);
1653 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
1655 dev->nix_msixoff = msix_rsp->nix_msixoff;
1661 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
1663 struct rsrc_detach_req *req;
1665 req = otx2_mbox_alloc_msg_detach_resources(mbox);
1667 /* Detach all except npa lf */
1668 req->partial = true;
1675 return otx2_mbox_process(mbox);
1679 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
1681 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1682 struct rte_pci_device *pci_dev;
1683 int rc, max_entries;
1685 eth_dev->dev_ops = &otx2_eth_dev_ops;
1687 /* For secondary processes, the primary has done all the work */
1688 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1689 /* Setup callbacks for secondary process */
1690 otx2_eth_set_tx_function(eth_dev);
1691 otx2_eth_set_rx_function(eth_dev);
1695 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1697 rte_eth_copy_pci_info(eth_dev, pci_dev);
1698 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1700 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
1701 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
1702 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
1704 /* Parse devargs string */
1705 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1707 otx2_err("Failed to parse devargs rc=%d", rc);
1711 if (!dev->mbox_active) {
1712 /* Initialize the base otx2_dev object
1713 * only if already present
1715 rc = otx2_dev_init(pci_dev, dev);
1717 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1721 /* Device generic callbacks */
1722 dev->ops = &otx2_dev_ops;
1723 dev->eth_dev = eth_dev;
1725 /* Grab the NPA LF if required */
1726 rc = otx2_npa_lf_init(pci_dev, dev);
1728 goto otx2_dev_uninit;
1730 dev->configured = 0;
1731 dev->drv_inited = true;
1732 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
1733 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
1736 rc = nix_lf_attach(dev);
1738 goto otx2_npa_uninit;
1740 /* Get NIX MSIX offset */
1741 rc = nix_lf_get_msix_offset(dev);
1743 goto otx2_npa_uninit;
1745 /* Register LF irq handlers */
1746 rc = otx2_nix_register_irqs(eth_dev);
1750 /* Get maximum number of supported MAC entries */
1751 max_entries = otx2_cgx_mac_max_entries_get(dev);
1752 if (max_entries < 0) {
1753 otx2_err("Failed to get max entries for mac addr");
1755 goto unregister_irq;
1758 /* For VFs, returned max_entries will be 0. But to keep default MAC
1759 * address, one entry must be allocated. So setting up to 1.
1761 if (max_entries == 0)
1764 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
1765 RTE_ETHER_ADDR_LEN, 0);
1766 if (eth_dev->data->mac_addrs == NULL) {
1767 otx2_err("Failed to allocate memory for mac addr");
1769 goto unregister_irq;
1772 dev->max_mac_entries = max_entries;
1774 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
1776 goto free_mac_addrs;
1778 /* Update the mac address */
1779 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1781 /* Also sync same MAC address to CGX table */
1782 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
1784 /* Initialize the tm data structures */
1785 otx2_nix_tm_conf_init(eth_dev);
1787 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1788 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1790 if (otx2_dev_is_Ax(dev)) {
1791 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
1792 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
1795 /* Initialize rte-flow */
1796 rc = otx2_flow_init(dev);
1798 goto free_mac_addrs;
1800 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
1801 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1802 eth_dev->data->port_id, dev->pf, dev->vf,
1803 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
1804 dev->rx_offload_capa, dev->tx_offload_capa);
1808 rte_free(eth_dev->data->mac_addrs);
1810 otx2_nix_unregister_irqs(eth_dev);
1812 otx2_eth_dev_lf_detach(dev->mbox);
1816 otx2_dev_fini(pci_dev, dev);
1818 otx2_err("Failed to init nix eth_dev rc=%d", rc);
1823 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
1825 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1826 struct rte_pci_device *pci_dev;
1829 /* Nothing to be done for secondary processes */
1830 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1833 /* Clear the flag since we are closing down */
1834 dev->configured = 0;
1836 /* Disable nix bpid config */
1837 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1839 npc_rx_disable(dev);
1841 /* Disable vlan offloads */
1842 otx2_nix_vlan_fini(eth_dev);
1844 /* Disable other rte_flow entries */
1845 otx2_flow_fini(dev);
1847 /* Disable PTP if already enabled */
1848 if (otx2_ethdev_is_ptp_en(dev))
1849 otx2_nix_timesync_disable(eth_dev);
1851 nix_cgx_stop_link_event(dev);
1854 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1855 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
1856 eth_dev->data->tx_queues[i] = NULL;
1858 eth_dev->data->nb_tx_queues = 0;
1860 /* Free up RQ's and CQ's */
1861 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1862 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
1863 eth_dev->data->rx_queues[i] = NULL;
1865 eth_dev->data->nb_rx_queues = 0;
1867 /* Free tm resources */
1868 rc = otx2_nix_tm_fini(eth_dev);
1870 otx2_err("Failed to cleanup tm, rc=%d", rc);
1872 /* Unregister queue irqs */
1873 oxt2_nix_unregister_queue_irqs(eth_dev);
1875 /* Unregister cq irqs */
1876 if (eth_dev->data->dev_conf.intr_conf.rxq)
1877 oxt2_nix_unregister_cq_irqs(eth_dev);
1879 rc = nix_lf_free(dev);
1881 otx2_err("Failed to free nix lf, rc=%d", rc);
1883 rc = otx2_npa_lf_fini();
1885 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
1887 rte_free(eth_dev->data->mac_addrs);
1888 eth_dev->data->mac_addrs = NULL;
1889 dev->drv_inited = false;
1891 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1892 otx2_nix_unregister_irqs(eth_dev);
1894 rc = otx2_eth_dev_lf_detach(dev->mbox);
1896 otx2_err("Failed to detach resources, rc=%d", rc);
1898 /* Check if mbox close is needed */
1902 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
1903 /* Will be freed later by PMD */
1904 eth_dev->data->dev_private = NULL;
1908 otx2_dev_fini(pci_dev, dev);
1913 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
1915 otx2_eth_dev_uninit(eth_dev, true);
1919 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
1923 rc = otx2_eth_dev_uninit(eth_dev, false);
1927 return otx2_eth_dev_init(eth_dev);
1931 nix_remove(struct rte_pci_device *pci_dev)
1933 struct rte_eth_dev *eth_dev;
1934 struct otx2_idev_cfg *idev;
1935 struct otx2_dev *otx2_dev;
1938 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1940 /* Cleanup eth dev */
1941 rc = otx2_eth_dev_uninit(eth_dev, true);
1945 rte_eth_dev_pci_release(eth_dev);
1948 /* Nothing to be done for secondary processes */
1949 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1952 /* Check for common resources */
1953 idev = otx2_intra_dev_get_cfg();
1954 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
1957 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
1959 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
1962 /* Safe to cleanup mbox as no more users */
1963 otx2_dev_fini(pci_dev, otx2_dev);
1968 otx2_info("%s: common resource in use by other devices", pci_dev->name);
1973 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
1977 RTE_SET_USED(pci_drv);
1979 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
1982 /* On error on secondary, recheck if port exists in primary or
1983 * in mid of detach state.
1985 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
1986 if (!rte_eth_dev_allocated(pci_dev->device.name))
1991 static const struct rte_pci_id pci_nix_map[] = {
1993 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
1996 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
1999 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2000 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
2007 static struct rte_pci_driver pci_nix = {
2008 .id_table = pci_nix_map,
2009 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA |
2010 RTE_PCI_DRV_INTR_LSC,
2012 .remove = nix_remove,
2015 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
2016 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
2017 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");