1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_ethdev_pci.h>
9 #include <rte_malloc.h>
11 #include <rte_mbuf_pool_ops.h>
12 #include <rte_mempool.h>
14 #include "otx2_ethdev.h"
16 static inline uint64_t
17 nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
19 uint64_t capa = NIX_RX_OFFLOAD_CAPA;
21 if (otx2_dev_is_vf(dev))
22 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
27 static inline uint64_t
28 nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
32 return NIX_TX_OFFLOAD_CAPA;
35 static const struct otx2_dev_ops otx2_dev_ops = {
36 .link_status_update = otx2_eth_dev_link_status_update,
37 .ptp_info_update = otx2_eth_dev_ptp_info_update
41 nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
43 struct otx2_mbox *mbox = dev->mbox;
44 struct nix_lf_alloc_req *req;
45 struct nix_lf_alloc_rsp *rsp;
48 req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
52 /* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
53 RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
54 req->xqe_sz = NIX_XQESZ_W16;
55 req->rss_sz = dev->rss_info.rss_size;
56 req->rss_grps = NIX_RSS_GRPS;
57 req->npa_func = otx2_npa_pf_func_get();
58 req->sso_func = otx2_sso_pf_func_get();
59 req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
60 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
61 DEV_RX_OFFLOAD_UDP_CKSUM)) {
62 req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
63 req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
65 req->rx_cfg |= BIT_ULL(32 /* DROP_RE */);
67 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
71 dev->sqb_size = rsp->sqb_size;
72 dev->tx_chan_base = rsp->tx_chan_base;
73 dev->rx_chan_base = rsp->rx_chan_base;
74 dev->rx_chan_cnt = rsp->rx_chan_cnt;
75 dev->tx_chan_cnt = rsp->tx_chan_cnt;
76 dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
77 dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
78 dev->lf_tx_stats = rsp->lf_tx_stats;
79 dev->lf_rx_stats = rsp->lf_rx_stats;
80 dev->cints = rsp->cints;
81 dev->qints = rsp->qints;
82 dev->npc_flow.channel = dev->rx_chan_base;
88 nix_lf_free(struct otx2_eth_dev *dev)
90 struct otx2_mbox *mbox = dev->mbox;
91 struct nix_lf_free_req *req;
92 struct ndc_sync_op *ndc_req;
95 /* Sync NDC-NIX for LF */
96 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
97 ndc_req->nix_lf_tx_sync = 1;
98 ndc_req->nix_lf_rx_sync = 1;
99 rc = otx2_mbox_process(mbox);
101 otx2_err("Error on NDC-NIX-[TX, RX] LF sync, rc %d", rc);
103 req = otx2_mbox_alloc_msg_nix_lf_free(mbox);
104 /* Let AF driver free all this nix lf's
105 * NPC entries allocated using NPC MBOX.
109 return otx2_mbox_process(mbox);
113 otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
115 struct otx2_mbox *mbox = dev->mbox;
117 if (otx2_dev_is_vf(dev))
120 otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
122 return otx2_mbox_process(mbox);
126 otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
128 struct otx2_mbox *mbox = dev->mbox;
130 if (otx2_dev_is_vf(dev))
133 otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
135 return otx2_mbox_process(mbox);
139 npc_rx_enable(struct otx2_eth_dev *dev)
141 struct otx2_mbox *mbox = dev->mbox;
143 otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
145 return otx2_mbox_process(mbox);
149 npc_rx_disable(struct otx2_eth_dev *dev)
151 struct otx2_mbox *mbox = dev->mbox;
153 otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
155 return otx2_mbox_process(mbox);
159 nix_cgx_start_link_event(struct otx2_eth_dev *dev)
161 struct otx2_mbox *mbox = dev->mbox;
163 if (otx2_dev_is_vf(dev))
166 otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
168 return otx2_mbox_process(mbox);
172 cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
174 struct otx2_mbox *mbox = dev->mbox;
176 if (otx2_dev_is_vf(dev))
180 otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
182 otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
184 return otx2_mbox_process(mbox);
188 nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
190 struct otx2_mbox *mbox = dev->mbox;
192 if (otx2_dev_is_vf(dev))
195 otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
197 return otx2_mbox_process(mbox);
201 nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
207 static inline uint32_t
208 nix_qsize_to_val(enum nix_q_size_e qsize)
210 return (16UL << (qsize * 2));
213 static inline enum nix_q_size_e
214 nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)
218 if (otx2_ethdev_fixup_is_min_4k_q(dev))
223 for (; i < nix_q_size_max; i++)
224 if (val <= nix_qsize_to_val(i))
227 if (i >= nix_q_size_max)
228 i = nix_q_size_max - 1;
234 nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,
235 uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)
237 struct otx2_mbox *mbox = dev->mbox;
238 const struct rte_memzone *rz;
239 uint32_t ring_size, cq_size;
240 struct nix_aq_enq_req *aq;
245 ring_size = cq_size * NIX_CQ_ENTRY_SZ;
246 rz = rte_eth_dma_zone_reserve(eth_dev, "cq", qid, ring_size,
247 NIX_CQ_ALIGN, dev->node);
249 otx2_err("Failed to allocate mem for cq hw ring");
253 memset(rz->addr, 0, rz->len);
254 rxq->desc = (uintptr_t)rz->addr;
255 rxq->qmask = cq_size - 1;
257 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
259 aq->ctype = NIX_AQ_CTYPE_CQ;
260 aq->op = NIX_AQ_INSTOP_INIT;
264 aq->cq.qsize = rxq->qsize;
265 aq->cq.base = rz->iova;
266 aq->cq.avg_level = 0xff;
267 aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
268 aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
270 /* TX pause frames enable flowctrl on RX side */
271 if (dev->fc_info.tx_pause) {
272 /* Single bpid is allocated for all rx channels for now */
273 aq->cq.bpid = dev->fc_info.bpid[0];
274 aq->cq.bp = NIX_CQ_BP_LEVEL;
278 /* Many to one reduction */
279 aq->cq.qint_idx = qid % dev->qints;
280 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
281 aq->cq.cint_idx = qid;
283 if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
284 uint16_t min_rx_drop;
285 const float rx_cq_skid = 1024 * 256;
287 min_rx_drop = ceil(rx_cq_skid / (float)cq_size);
288 aq->cq.drop = min_rx_drop;
292 rc = otx2_mbox_process(mbox);
294 otx2_err("Failed to init cq context");
298 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
300 aq->ctype = NIX_AQ_CTYPE_RQ;
301 aq->op = NIX_AQ_INSTOP_INIT;
304 aq->rq.cq = qid; /* RQ to CQ 1:1 mapped */
306 aq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);
307 first_skip = (sizeof(struct rte_mbuf));
308 first_skip += RTE_PKTMBUF_HEADROOM;
309 first_skip += rte_pktmbuf_priv_size(mp);
310 rxq->data_off = first_skip;
312 first_skip /= 8; /* Expressed in number of dwords */
313 aq->rq.first_skip = first_skip;
314 aq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);
315 aq->rq.flow_tagw = 32; /* 32-bits */
316 aq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);
317 aq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);
318 aq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);
319 aq->rq.lpb_sizem1 /= 8;
320 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
322 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
323 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
324 aq->rq.rq_int_ena = 0;
325 /* Many to one reduction */
326 aq->rq.qint_idx = qid % dev->qints;
328 if (otx2_ethdev_fixup_is_limit_cq_full(dev))
329 aq->rq.xqe_drop_ena = 1;
331 rc = otx2_mbox_process(mbox);
333 otx2_err("Failed to init rq context");
343 nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
344 struct otx2_eth_rxq *rxq, const bool enb)
346 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
347 struct otx2_mbox *mbox = dev->mbox;
348 struct nix_aq_enq_req *aq;
350 /* Pkts will be dropped silently if RQ is disabled */
351 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
353 aq->ctype = NIX_AQ_CTYPE_RQ;
354 aq->op = NIX_AQ_INSTOP_WRITE;
357 aq->rq_mask.ena = ~(aq->rq_mask.ena);
359 return otx2_mbox_process(mbox);
363 nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
365 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
366 struct otx2_mbox *mbox = dev->mbox;
367 struct nix_aq_enq_req *aq;
370 /* RQ is already disabled */
372 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
374 aq->ctype = NIX_AQ_CTYPE_CQ;
375 aq->op = NIX_AQ_INSTOP_WRITE;
378 aq->cq_mask.ena = ~(aq->cq_mask.ena);
380 rc = otx2_mbox_process(mbox);
382 otx2_err("Failed to disable cq context");
390 nix_get_data_off(struct otx2_eth_dev *dev)
392 return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
396 otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)
398 struct rte_mbuf mb_def;
401 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
402 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
403 offsetof(struct rte_mbuf, data_off) != 2);
404 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
405 offsetof(struct rte_mbuf, data_off) != 4);
406 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
407 offsetof(struct rte_mbuf, data_off) != 6);
409 mb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);
410 mb_def.port = port_id;
411 rte_mbuf_refcnt_set(&mb_def, 1);
413 /* Prevent compiler reordering: rearm_data covers previous fields */
414 rte_compiler_barrier();
415 tmp = (uint64_t *)&mb_def.rearm_data;
421 otx2_nix_rx_queue_release(void *rx_queue)
423 struct otx2_eth_rxq *rxq = rx_queue;
428 otx2_nix_dbg("Releasing rxq %u", rxq->rq);
429 nix_cq_rq_uninit(rxq->eth_dev, rxq);
434 otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,
435 uint16_t nb_desc, unsigned int socket,
436 const struct rte_eth_rxconf *rx_conf,
437 struct rte_mempool *mp)
439 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
440 struct rte_mempool_ops *ops;
441 struct otx2_eth_rxq *rxq;
442 const char *platform_ops;
443 enum nix_q_size_e qsize;
449 /* Compile time check to make sure all fast path elements in a CL */
450 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);
453 if (rx_conf->rx_deferred_start == 1) {
454 otx2_err("Deferred Rx start is not supported");
458 platform_ops = rte_mbuf_platform_mempool_ops();
459 /* This driver needs octeontx2_npa mempool ops to work */
460 ops = rte_mempool_get_ops(mp->ops_index);
461 if (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {
462 otx2_err("mempool ops should be of octeontx2_npa type");
466 if (mp->pool_id == 0) {
467 otx2_err("Invalid pool_id");
471 /* Free memory prior to re-allocation if needed */
472 if (eth_dev->data->rx_queues[rq] != NULL) {
473 otx2_nix_dbg("Freeing memory prior to re-allocation %d", rq);
474 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);
475 eth_dev->data->rx_queues[rq] = NULL;
478 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
479 dev->rx_offloads |= offloads;
481 /* Find the CQ queue size */
482 qsize = nix_qsize_clampup_get(dev, nb_desc);
483 /* Allocate rxq memory */
484 rxq = rte_zmalloc_socket("otx2 rxq", sizeof(*rxq), OTX2_ALIGN, socket);
486 otx2_err("Failed to allocate rq=%d", rq);
491 rxq->eth_dev = eth_dev;
493 rxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;
494 rxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);
495 rxq->wdata = (uint64_t)rq << 32;
496 rxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);
497 rxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,
498 eth_dev->data->port_id);
499 rxq->offloads = offloads;
501 rxq->qlen = nix_qsize_to_val(qsize);
503 rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
504 rxq->tstamp = &dev->tstamp;
506 /* Alloc completion queue */
507 rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
509 otx2_err("Failed to allocate rxq=%u", rq);
513 rxq->qconf.socket_id = socket;
514 rxq->qconf.nb_desc = nb_desc;
515 rxq->qconf.mempool = mp;
516 memcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));
518 nix_rx_queue_reset(rxq);
519 otx2_nix_dbg("rq=%d pool=%s qsize=%d nb_desc=%d->%d",
520 rq, mp->name, qsize, nb_desc, rxq->qlen);
522 eth_dev->data->rx_queues[rq] = rxq;
523 eth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;
525 /* Calculating delta and freq mult between PTP HI clock and tsc.
526 * These are needed in deriving raw clock value from tsc counter.
527 * read_clock eth op returns raw clock value.
529 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
530 otx2_ethdev_is_ptp_en(dev)) {
531 rc = otx2_nix_raw_clock_tsc_conv(dev);
533 otx2_err("Failed to calculate delta and freq mult");
541 otx2_nix_rx_queue_release(rxq);
546 static inline uint8_t
547 nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
550 * Maximum three segments can be supported with W8, Choose
551 * NIX_MAXSQESZ_W16 for multi segment offload.
553 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
554 return NIX_MAXSQESZ_W16;
556 return NIX_MAXSQESZ_W8;
560 nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
562 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
563 struct rte_eth_dev_data *data = eth_dev->data;
564 struct rte_eth_conf *conf = &data->dev_conf;
565 struct rte_eth_rxmode *rxmode = &conf->rxmode;
568 if (rxmode->mq_mode == ETH_MQ_RX_RSS)
569 flags |= NIX_RX_OFFLOAD_RSS_F;
571 if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
572 DEV_RX_OFFLOAD_UDP_CKSUM))
573 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
575 if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
576 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
577 flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
579 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
580 flags |= NIX_RX_MULTI_SEG_F;
582 if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
583 DEV_RX_OFFLOAD_QINQ_STRIP))
584 flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
586 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
587 flags |= NIX_RX_OFFLOAD_TSTAMP_F;
593 nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
595 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
596 uint64_t conf = dev->tx_offloads;
599 /* Fastpath is dependent on these enums */
600 RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
601 RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
602 RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
603 RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
604 RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
605 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
606 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
607 RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
608 RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
609 RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
610 RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
611 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
612 RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
613 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
614 offsetof(struct rte_mbuf, buf_iova) + 8);
615 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
616 offsetof(struct rte_mbuf, buf_iova) + 16);
617 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
618 offsetof(struct rte_mbuf, ol_flags) + 12);
619 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
620 offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
622 if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
623 conf & DEV_TX_OFFLOAD_QINQ_INSERT)
624 flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
626 if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
627 conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
628 flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
630 if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
631 conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
632 conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
633 conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
634 flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
636 if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
637 flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
639 if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
640 flags |= NIX_TX_MULTI_SEG_F;
642 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
643 flags |= NIX_TX_OFFLOAD_TSTAMP_F;
649 nix_sq_init(struct otx2_eth_txq *txq)
651 struct otx2_eth_dev *dev = txq->dev;
652 struct otx2_mbox *mbox = dev->mbox;
653 struct nix_aq_enq_req *sq;
658 if (txq->sqb_pool->pool_id == 0)
661 rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
663 otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
667 sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
669 sq->ctype = NIX_AQ_CTYPE_SQ;
670 sq->op = NIX_AQ_INSTOP_INIT;
671 sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
674 sq->sq.smq_rr_quantum = rr_quantum;
675 sq->sq.default_chan = dev->tx_chan_base;
676 sq->sq.sqe_stype = NIX_STYPE_STF;
678 if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
679 sq->sq.sqe_stype = NIX_STYPE_STP;
681 npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
682 sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
683 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
684 sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
685 sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
687 /* Many to one reduction */
688 sq->sq.qint_idx = txq->sq % dev->qints;
690 return otx2_mbox_process(mbox);
694 nix_sq_uninit(struct otx2_eth_txq *txq)
696 struct otx2_eth_dev *dev = txq->dev;
697 struct otx2_mbox *mbox = dev->mbox;
698 struct ndc_sync_op *ndc_req;
699 struct nix_aq_enq_rsp *rsp;
700 struct nix_aq_enq_req *aq;
701 uint16_t sqes_per_sqb;
705 otx2_nix_dbg("Cleaning up sq %u", txq->sq);
707 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
709 aq->ctype = NIX_AQ_CTYPE_SQ;
710 aq->op = NIX_AQ_INSTOP_READ;
712 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
716 /* Check if sq is already cleaned up */
721 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
723 aq->ctype = NIX_AQ_CTYPE_SQ;
724 aq->op = NIX_AQ_INSTOP_WRITE;
726 aq->sq_mask.ena = ~aq->sq_mask.ena;
729 rc = otx2_mbox_process(mbox);
733 /* Read SQ and free sqb's */
734 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
736 aq->ctype = NIX_AQ_CTYPE_SQ;
737 aq->op = NIX_AQ_INSTOP_READ;
739 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
744 otx2_err("SQ has pending sqe's");
746 count = aq->sq.sqb_count;
747 sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
748 /* Free SQB's that are used */
749 sqb_buf = (void *)rsp->sq.head_sqb;
753 next_sqb = *(void **)((uintptr_t)sqb_buf + ((sqes_per_sqb - 1) *
754 nix_sq_max_sqe_sz(txq)));
755 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
761 /* Free next to use sqb */
762 if (rsp->sq.next_sqb)
763 npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
766 /* Sync NDC-NIX-TX for LF */
767 ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
768 ndc_req->nix_lf_tx_sync = 1;
769 rc = otx2_mbox_process(mbox);
771 otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
777 nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
779 struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
780 struct npa_aq_enq_req *aura_req;
782 aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
783 aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
784 aura_req->ctype = NPA_AQ_CTYPE_AURA;
785 aura_req->op = NPA_AQ_INSTOP_WRITE;
787 aura_req->aura.limit = nb_sqb_bufs;
788 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
790 return otx2_mbox_process(npa_lf->mbox);
794 nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
796 struct otx2_eth_dev *dev = txq->dev;
797 uint16_t sqes_per_sqb, nb_sqb_bufs;
798 char name[RTE_MEMPOOL_NAMESIZE];
799 struct rte_mempool_objsz sz;
800 struct npa_aura_s *aura;
801 uint32_t tmp, blk_sz;
803 aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
804 snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
805 blk_sz = dev->sqb_size;
807 if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
808 sqes_per_sqb = (dev->sqb_size / 8) / 16;
810 sqes_per_sqb = (dev->sqb_size / 8) / 8;
812 nb_sqb_bufs = nb_desc / sqes_per_sqb;
813 /* Clamp up to devarg passed SQB count */
814 nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_MIN_SQB,
815 nb_sqb_bufs + NIX_SQB_LIST_SPACE));
817 txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
819 MEMPOOL_F_NO_SPREAD);
820 txq->nb_sqb_bufs = nb_sqb_bufs;
821 txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
822 txq->nb_sqb_bufs_adj = nb_sqb_bufs -
823 RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
824 txq->nb_sqb_bufs_adj =
825 (NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
827 if (txq->sqb_pool == NULL) {
828 otx2_err("Failed to allocate sqe mempool");
832 memset(aura, 0, sizeof(*aura));
834 aura->fc_addr = txq->fc_iova;
835 aura->fc_hyst_bits = 0; /* Store count on all updates */
836 if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
837 otx2_err("Failed to set ops for sqe mempool");
840 if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
841 otx2_err("Failed to populate sqe mempool");
845 tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
846 if (dev->sqb_size != sz.elt_size) {
847 otx2_err("sqe pool block size is not expected %d != %d",
852 nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
860 otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
862 struct nix_send_ext_s *send_hdr_ext;
863 struct nix_send_hdr_s *send_hdr;
864 struct nix_send_mem_s *send_mem;
865 union nix_send_sg_s *sg;
867 /* Initialize the fields based on basic single segment packet */
868 memset(&txq->cmd, 0, sizeof(txq->cmd));
870 if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
871 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
872 /* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
873 send_hdr->w0.sizem1 = 2;
875 send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
876 send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
877 if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
878 /* Default: one seg packet would have:
879 * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
882 send_hdr->w0.sizem1 = 3;
883 send_hdr_ext->w0.tstmp = 1;
885 /* To calculate the offset for send_mem,
886 * send_hdr->w0.sizem1 * 2
888 send_mem = (struct nix_send_mem_s *)(txq->cmd +
889 (send_hdr->w0.sizem1 << 1));
890 send_mem->subdc = NIX_SUBDC_MEM;
891 send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
892 send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
894 sg = (union nix_send_sg_s *)&txq->cmd[4];
896 send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
897 /* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
898 send_hdr->w0.sizem1 = 1;
899 sg = (union nix_send_sg_s *)&txq->cmd[2];
902 send_hdr->w0.sq = txq->sq;
903 sg->subdc = NIX_SUBDC_SG;
905 sg->ld_type = NIX_SENDLDTYPE_LDD;
911 otx2_nix_tx_queue_release(void *_txq)
913 struct otx2_eth_txq *txq = _txq;
914 struct rte_eth_dev *eth_dev;
919 eth_dev = txq->dev->eth_dev;
921 otx2_nix_dbg("Releasing txq %u", txq->sq);
923 /* Flush and disable tm */
924 otx2_nix_tm_sw_xoff(txq, eth_dev->data->dev_started);
926 /* Free sqb's and disable sq */
930 rte_mempool_free(txq->sqb_pool);
931 txq->sqb_pool = NULL;
938 otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
939 uint16_t nb_desc, unsigned int socket_id,
940 const struct rte_eth_txconf *tx_conf)
942 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
943 const struct rte_memzone *fc;
944 struct otx2_eth_txq *txq;
950 /* Compile time check to make sure all fast path elements in a CL */
951 RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
953 if (tx_conf->tx_deferred_start) {
954 otx2_err("Tx deferred start is not supported");
958 /* Free memory prior to re-allocation if needed. */
959 if (eth_dev->data->tx_queues[sq] != NULL) {
960 otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
961 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
962 eth_dev->data->tx_queues[sq] = NULL;
965 /* Find the expected offloads for this queue */
966 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
968 /* Allocating tx queue data structure */
969 txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
970 OTX2_ALIGN, socket_id);
972 otx2_err("Failed to alloc txq=%d", sq);
978 txq->sqb_pool = NULL;
979 txq->offloads = offloads;
980 dev->tx_offloads |= offloads;
983 * Allocate memory for flow control updates from HW.
984 * Alloc one cache line, so that fits all FC_STYPE modes.
986 fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
987 OTX2_ALIGN + sizeof(struct npa_aura_s),
988 OTX2_ALIGN, dev->node);
990 otx2_err("Failed to allocate mem for fcmem");
994 txq->fc_iova = fc->iova;
995 txq->fc_mem = fc->addr;
997 /* Initialize the aura sqb pool */
998 rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
1000 otx2_err("Failed to alloc sqe pool rc=%d", rc);
1004 /* Initialize the SQ */
1005 rc = nix_sq_init(txq);
1007 otx2_err("Failed to init sq=%d context", sq);
1011 txq->fc_cache_pkts = 0;
1012 txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
1013 /* Evenly distribute LMT slot for each sq */
1014 txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
1016 txq->qconf.socket_id = socket_id;
1017 txq->qconf.nb_desc = nb_desc;
1018 memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
1020 otx2_nix_form_default_desc(txq);
1022 otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
1023 " lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
1024 fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
1025 txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
1026 eth_dev->data->tx_queues[sq] = txq;
1027 eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
1031 otx2_nix_tx_queue_release(txq);
1037 nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)
1039 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1040 struct otx2_eth_qconf *tx_qconf = NULL;
1041 struct otx2_eth_qconf *rx_qconf = NULL;
1042 struct otx2_eth_txq **txq;
1043 struct otx2_eth_rxq **rxq;
1044 int i, nb_rxq, nb_txq;
1046 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1047 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1049 tx_qconf = malloc(nb_txq * sizeof(*tx_qconf));
1050 if (tx_qconf == NULL) {
1051 otx2_err("Failed to allocate memory for tx_qconf");
1055 rx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));
1056 if (rx_qconf == NULL) {
1057 otx2_err("Failed to allocate memory for rx_qconf");
1061 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1062 for (i = 0; i < nb_txq; i++) {
1063 if (txq[i] == NULL) {
1064 otx2_err("txq[%d] is already released", i);
1067 memcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));
1068 otx2_nix_tx_queue_release(txq[i]);
1069 eth_dev->data->tx_queues[i] = NULL;
1072 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1073 for (i = 0; i < nb_rxq; i++) {
1074 if (rxq[i] == NULL) {
1075 otx2_err("rxq[%d] is already released", i);
1078 memcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));
1079 otx2_nix_rx_queue_release(rxq[i]);
1080 eth_dev->data->rx_queues[i] = NULL;
1083 dev->tx_qconf = tx_qconf;
1084 dev->rx_qconf = rx_qconf;
1097 nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)
1099 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1100 struct otx2_eth_qconf *tx_qconf = dev->tx_qconf;
1101 struct otx2_eth_qconf *rx_qconf = dev->rx_qconf;
1102 struct otx2_eth_txq **txq;
1103 struct otx2_eth_rxq **rxq;
1104 int rc, i, nb_rxq, nb_txq;
1106 nb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);
1107 nb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);
1110 /* Setup tx & rx queues with previous configuration so
1111 * that the queues can be functional in cases like ports
1112 * are started without re configuring queues.
1114 * Usual re config sequence is like below:
1115 * port_configure() {
1120 * queue_configure() {
1127 * In some application's control path, queue_configure() would
1128 * NOT be invoked for TXQs/RXQs in port_configure().
1129 * In such cases, queues can be functional after start as the
1130 * queues are already setup in port_configure().
1132 for (i = 0; i < nb_txq; i++) {
1133 rc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,
1134 tx_qconf[i].socket_id,
1135 &tx_qconf[i].conf.tx);
1137 otx2_err("Failed to setup tx queue rc=%d", rc);
1138 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1139 for (i -= 1; i >= 0; i--)
1140 otx2_nix_tx_queue_release(txq[i]);
1145 free(tx_qconf); tx_qconf = NULL;
1147 for (i = 0; i < nb_rxq; i++) {
1148 rc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,
1149 rx_qconf[i].socket_id,
1150 &rx_qconf[i].conf.rx,
1151 rx_qconf[i].mempool);
1153 otx2_err("Failed to setup rx queue rc=%d", rc);
1154 rxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;
1155 for (i -= 1; i >= 0; i--)
1156 otx2_nix_rx_queue_release(rxq[i]);
1157 goto release_tx_queues;
1161 free(rx_qconf); rx_qconf = NULL;
1166 txq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;
1167 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1168 otx2_nix_tx_queue_release(txq[i]);
1179 nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)
1181 RTE_SET_USED(queue);
1182 RTE_SET_USED(mbufs);
1189 nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)
1191 /* These dummy functions are required for supporting
1192 * some applications which reconfigure queues without
1193 * stopping tx burst and rx burst threads(eg kni app)
1194 * When the queues context is saved, txq/rxqs are released
1195 * which caused app crash since rx/tx burst is still
1196 * on different lcores
1198 eth_dev->tx_pkt_burst = nix_eth_nop_burst;
1199 eth_dev->rx_pkt_burst = nix_eth_nop_burst;
1204 otx2_nix_configure(struct rte_eth_dev *eth_dev)
1206 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1207 struct rte_eth_dev_data *data = eth_dev->data;
1208 struct rte_eth_conf *conf = &data->dev_conf;
1209 struct rte_eth_rxmode *rxmode = &conf->rxmode;
1210 struct rte_eth_txmode *txmode = &conf->txmode;
1211 char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
1212 struct rte_ether_addr *ea;
1213 uint8_t nb_rxq, nb_txq;
1219 if (rte_eal_has_hugepages() == 0) {
1220 otx2_err("Huge page is not configured");
1221 goto fail_configure;
1224 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1225 otx2_err("Setting link speed/duplex not supported");
1226 goto fail_configure;
1229 if (conf->dcb_capability_en == 1) {
1230 otx2_err("dcb enable is not supported");
1231 goto fail_configure;
1234 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1235 otx2_err("Flow director is not supported");
1236 goto fail_configure;
1239 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1240 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1241 otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
1242 goto fail_configure;
1245 if (txmode->mq_mode != ETH_MQ_TX_NONE) {
1246 otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
1247 goto fail_configure;
1250 if (otx2_dev_is_Ax(dev) &&
1251 (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
1252 ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
1253 (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
1254 otx2_err("Outer IP and SCTP checksum unsupported");
1255 goto fail_configure;
1258 /* Free the resources allocated from the previous configure */
1259 if (dev->configured == 1) {
1260 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1261 otx2_nix_vlan_fini(eth_dev);
1262 otx2_flow_free_all_resources(dev);
1263 oxt2_nix_unregister_queue_irqs(eth_dev);
1264 if (eth_dev->data->dev_conf.intr_conf.rxq)
1265 oxt2_nix_unregister_cq_irqs(eth_dev);
1266 nix_set_nop_rxtx_function(eth_dev);
1267 rc = nix_store_queue_cfg_and_then_release(eth_dev);
1269 goto fail_configure;
1270 otx2_nix_tm_fini(eth_dev);
1274 dev->rx_offloads = rxmode->offloads;
1275 dev->tx_offloads = txmode->offloads;
1276 dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
1277 dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
1278 dev->rss_info.rss_grps = NIX_RSS_GRPS;
1280 nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
1281 nb_txq = RTE_MAX(data->nb_tx_queues, 1);
1283 /* Alloc a nix lf */
1284 rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
1286 otx2_err("Failed to init nix_lf rc=%d", rc);
1291 rc = otx2_nix_rss_config(eth_dev);
1293 otx2_err("Failed to configure rss rc=%d", rc);
1297 /* Init the default TM scheduler hierarchy */
1298 rc = otx2_nix_tm_init_default(eth_dev);
1300 otx2_err("Failed to init traffic manager rc=%d", rc);
1304 rc = otx2_nix_vlan_offload_init(eth_dev);
1306 otx2_err("Failed to init vlan offload rc=%d", rc);
1310 /* Register queue IRQs */
1311 rc = oxt2_nix_register_queue_irqs(eth_dev);
1313 otx2_err("Failed to register queue interrupts rc=%d", rc);
1317 /* Register cq IRQs */
1318 if (eth_dev->data->dev_conf.intr_conf.rxq) {
1319 if (eth_dev->data->nb_rx_queues > dev->cints) {
1320 otx2_err("Rx interrupt cannot be enabled, rxq > %d",
1324 /* Rx interrupt feature cannot work with vector mode because,
1325 * vector mode doesn't process packets unless min 4 pkts are
1326 * received, while cq interrupts are generated even for 1 pkt
1329 dev->scalar_ena = true;
1331 rc = oxt2_nix_register_cq_irqs(eth_dev);
1333 otx2_err("Failed to register CQ interrupts rc=%d", rc);
1338 /* Configure loop back mode */
1339 rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
1341 otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
1345 rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
1347 otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
1352 * Restore queue config when reconfigure followed by
1353 * reconfigure and no queue configure invoked from application case.
1355 if (dev->configured == 1) {
1356 rc = nix_restore_queue_cfg(eth_dev);
1361 /* Update the mac address */
1362 ea = eth_dev->data->mac_addrs;
1363 memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1364 if (rte_is_zero_ether_addr(ea))
1365 rte_eth_random_addr((uint8_t *)ea);
1367 rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
1369 otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
1370 " rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
1371 " rx_flags=0x%x tx_flags=0x%x",
1372 eth_dev->data->port_id, ea_fmt, nb_rxq,
1373 nb_txq, dev->rx_offloads, dev->tx_offloads,
1374 dev->rx_offload_flags, dev->tx_offload_flags);
1377 dev->configured = 1;
1378 dev->configured_nb_rx_qs = data->nb_rx_queues;
1379 dev->configured_nb_tx_qs = data->nb_tx_queues;
1383 oxt2_nix_unregister_cq_irqs(eth_dev);
1385 oxt2_nix_unregister_queue_irqs(eth_dev);
1387 otx2_nix_vlan_fini(eth_dev);
1389 otx2_nix_tm_fini(eth_dev);
1393 dev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);
1394 dev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);
1396 dev->configured = 0;
1401 otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1403 struct rte_eth_dev_data *data = eth_dev->data;
1404 struct otx2_eth_txq *txq;
1407 txq = eth_dev->data->tx_queues[qidx];
1409 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1412 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1414 otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
1419 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1426 otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1428 struct rte_eth_dev_data *data = eth_dev->data;
1429 struct otx2_eth_txq *txq;
1432 txq = eth_dev->data->tx_queues[qidx];
1434 if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1437 txq->fc_cache_pkts = 0;
1439 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1441 otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
1446 data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1453 otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
1455 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1456 struct rte_eth_dev_data *data = eth_dev->data;
1459 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
1462 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
1464 otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
1468 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
1475 otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
1477 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
1478 struct rte_eth_dev_data *data = eth_dev->data;
1481 if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
1484 rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
1486 otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
1490 data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
1497 otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
1499 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1500 struct rte_mbuf *rx_pkts[32];
1501 struct otx2_eth_rxq *rxq;
1502 int count, i, j, rc;
1504 nix_cgx_stop_link_event(dev);
1505 npc_rx_disable(dev);
1507 /* Stop rx queues and free up pkts pending */
1508 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1509 rc = otx2_nix_rx_queue_stop(eth_dev, i);
1513 rxq = eth_dev->data->rx_queues[i];
1514 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1516 for (j = 0; j < count; j++)
1517 rte_pktmbuf_free(rx_pkts[j]);
1518 count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
1522 /* Stop tx queues */
1523 for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
1524 otx2_nix_tx_queue_stop(eth_dev, i);
1528 otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
1530 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1533 if (eth_dev->data->nb_rx_queues != 0) {
1534 rc = otx2_nix_recalc_mtu(eth_dev);
1539 /* Start rx queues */
1540 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1541 rc = otx2_nix_rx_queue_start(eth_dev, i);
1546 /* Start tx queues */
1547 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1548 rc = otx2_nix_tx_queue_start(eth_dev, i);
1553 rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
1555 otx2_err("Failed to update flow ctrl mode %d", rc);
1559 /* Enable PTP if it was requested by the app or if it is already
1560 * enabled in PF owning this VF
1562 memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
1563 if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
1564 otx2_ethdev_is_ptp_en(dev))
1565 otx2_nix_timesync_enable(eth_dev);
1567 otx2_nix_timesync_disable(eth_dev);
1569 rc = npc_rx_enable(dev);
1571 otx2_err("Failed to enable NPC rx %d", rc);
1575 otx2_nix_toggle_flag_link_cfg(dev, true);
1577 rc = nix_cgx_start_link_event(dev);
1579 otx2_err("Failed to start cgx link event %d", rc);
1583 otx2_nix_toggle_flag_link_cfg(dev, false);
1584 otx2_eth_set_tx_function(eth_dev);
1585 otx2_eth_set_rx_function(eth_dev);
1590 npc_rx_disable(dev);
1591 otx2_nix_toggle_flag_link_cfg(dev, false);
1595 static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
1596 static void otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
1598 /* Initialize and register driver with DPDK Application */
1599 static const struct eth_dev_ops otx2_eth_dev_ops = {
1600 .dev_infos_get = otx2_nix_info_get,
1601 .dev_configure = otx2_nix_configure,
1602 .link_update = otx2_nix_link_update,
1603 .tx_queue_setup = otx2_nix_tx_queue_setup,
1604 .tx_queue_release = otx2_nix_tx_queue_release,
1605 .rx_queue_setup = otx2_nix_rx_queue_setup,
1606 .rx_queue_release = otx2_nix_rx_queue_release,
1607 .dev_start = otx2_nix_dev_start,
1608 .dev_stop = otx2_nix_dev_stop,
1609 .dev_close = otx2_nix_dev_close,
1610 .tx_queue_start = otx2_nix_tx_queue_start,
1611 .tx_queue_stop = otx2_nix_tx_queue_stop,
1612 .rx_queue_start = otx2_nix_rx_queue_start,
1613 .rx_queue_stop = otx2_nix_rx_queue_stop,
1614 .dev_set_link_up = otx2_nix_dev_set_link_up,
1615 .dev_set_link_down = otx2_nix_dev_set_link_down,
1616 .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
1617 .dev_reset = otx2_nix_dev_reset,
1618 .stats_get = otx2_nix_dev_stats_get,
1619 .stats_reset = otx2_nix_dev_stats_reset,
1620 .get_reg = otx2_nix_dev_get_reg,
1621 .mtu_set = otx2_nix_mtu_set,
1622 .mac_addr_add = otx2_nix_mac_addr_add,
1623 .mac_addr_remove = otx2_nix_mac_addr_del,
1624 .mac_addr_set = otx2_nix_mac_addr_set,
1625 .promiscuous_enable = otx2_nix_promisc_enable,
1626 .promiscuous_disable = otx2_nix_promisc_disable,
1627 .allmulticast_enable = otx2_nix_allmulticast_enable,
1628 .allmulticast_disable = otx2_nix_allmulticast_disable,
1629 .queue_stats_mapping_set = otx2_nix_queue_stats_mapping,
1630 .reta_update = otx2_nix_dev_reta_update,
1631 .reta_query = otx2_nix_dev_reta_query,
1632 .rss_hash_update = otx2_nix_rss_hash_update,
1633 .rss_hash_conf_get = otx2_nix_rss_hash_conf_get,
1634 .xstats_get = otx2_nix_xstats_get,
1635 .xstats_get_names = otx2_nix_xstats_get_names,
1636 .xstats_reset = otx2_nix_xstats_reset,
1637 .xstats_get_by_id = otx2_nix_xstats_get_by_id,
1638 .xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
1639 .rxq_info_get = otx2_nix_rxq_info_get,
1640 .txq_info_get = otx2_nix_txq_info_get,
1641 .rx_queue_count = otx2_nix_rx_queue_count,
1642 .rx_descriptor_done = otx2_nix_rx_descriptor_done,
1643 .rx_descriptor_status = otx2_nix_rx_descriptor_status,
1644 .tx_done_cleanup = otx2_nix_tx_done_cleanup,
1645 .pool_ops_supported = otx2_nix_pool_ops_supported,
1646 .filter_ctrl = otx2_nix_dev_filter_ctrl,
1647 .get_module_info = otx2_nix_get_module_info,
1648 .get_module_eeprom = otx2_nix_get_module_eeprom,
1649 .fw_version_get = otx2_nix_fw_version_get,
1650 .flow_ctrl_get = otx2_nix_flow_ctrl_get,
1651 .flow_ctrl_set = otx2_nix_flow_ctrl_set,
1652 .timesync_enable = otx2_nix_timesync_enable,
1653 .timesync_disable = otx2_nix_timesync_disable,
1654 .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
1655 .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
1656 .timesync_adjust_time = otx2_nix_timesync_adjust_time,
1657 .timesync_read_time = otx2_nix_timesync_read_time,
1658 .timesync_write_time = otx2_nix_timesync_write_time,
1659 .vlan_offload_set = otx2_nix_vlan_offload_set,
1660 .vlan_filter_set = otx2_nix_vlan_filter_set,
1661 .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
1662 .vlan_tpid_set = otx2_nix_vlan_tpid_set,
1663 .vlan_pvid_set = otx2_nix_vlan_pvid_set,
1664 .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
1665 .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
1666 .read_clock = otx2_nix_read_clock,
1670 nix_lf_attach(struct otx2_eth_dev *dev)
1672 struct otx2_mbox *mbox = dev->mbox;
1673 struct rsrc_attach_req *req;
1675 /* Attach NIX(lf) */
1676 req = otx2_mbox_alloc_msg_attach_resources(mbox);
1680 return otx2_mbox_process(mbox);
1684 nix_lf_get_msix_offset(struct otx2_eth_dev *dev)
1686 struct otx2_mbox *mbox = dev->mbox;
1687 struct msix_offset_rsp *msix_rsp;
1690 /* Get NPA and NIX MSIX vector offsets */
1691 otx2_mbox_alloc_msg_msix_offset(mbox);
1693 rc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);
1695 dev->nix_msixoff = msix_rsp->nix_msixoff;
1701 otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)
1703 struct rsrc_detach_req *req;
1705 req = otx2_mbox_alloc_msg_detach_resources(mbox);
1707 /* Detach all except npa lf */
1708 req->partial = true;
1715 return otx2_mbox_process(mbox);
1719 otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
1721 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1722 struct rte_pci_device *pci_dev;
1723 int rc, max_entries;
1725 eth_dev->dev_ops = &otx2_eth_dev_ops;
1727 /* For secondary processes, the primary has done all the work */
1728 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1729 /* Setup callbacks for secondary process */
1730 otx2_eth_set_tx_function(eth_dev);
1731 otx2_eth_set_rx_function(eth_dev);
1735 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1737 rte_eth_copy_pci_info(eth_dev, pci_dev);
1738 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1740 /* Zero out everything after OTX2_DEV to allow proper dev_reset() */
1741 memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -
1742 offsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));
1744 /* Parse devargs string */
1745 rc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);
1747 otx2_err("Failed to parse devargs rc=%d", rc);
1751 if (!dev->mbox_active) {
1752 /* Initialize the base otx2_dev object
1753 * only if already present
1755 rc = otx2_dev_init(pci_dev, dev);
1757 otx2_err("Failed to initialize otx2_dev rc=%d", rc);
1761 /* Device generic callbacks */
1762 dev->ops = &otx2_dev_ops;
1763 dev->eth_dev = eth_dev;
1765 /* Grab the NPA LF if required */
1766 rc = otx2_npa_lf_init(pci_dev, dev);
1768 goto otx2_dev_uninit;
1770 dev->configured = 0;
1771 dev->drv_inited = true;
1772 dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
1773 dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
1776 rc = nix_lf_attach(dev);
1778 goto otx2_npa_uninit;
1780 /* Get NIX MSIX offset */
1781 rc = nix_lf_get_msix_offset(dev);
1783 goto otx2_npa_uninit;
1785 /* Register LF irq handlers */
1786 rc = otx2_nix_register_irqs(eth_dev);
1790 /* Get maximum number of supported MAC entries */
1791 max_entries = otx2_cgx_mac_max_entries_get(dev);
1792 if (max_entries < 0) {
1793 otx2_err("Failed to get max entries for mac addr");
1795 goto unregister_irq;
1798 /* For VFs, returned max_entries will be 0. But to keep default MAC
1799 * address, one entry must be allocated. So setting up to 1.
1801 if (max_entries == 0)
1804 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", max_entries *
1805 RTE_ETHER_ADDR_LEN, 0);
1806 if (eth_dev->data->mac_addrs == NULL) {
1807 otx2_err("Failed to allocate memory for mac addr");
1809 goto unregister_irq;
1812 dev->max_mac_entries = max_entries;
1814 rc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);
1816 goto free_mac_addrs;
1818 /* Update the mac address */
1819 memcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);
1821 /* Also sync same MAC address to CGX table */
1822 otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
1824 /* Initialize the tm data structures */
1825 otx2_nix_tm_conf_init(eth_dev);
1827 dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
1828 dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
1830 if (otx2_dev_is_Ax(dev)) {
1831 dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
1832 dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
1835 /* Initialize rte-flow */
1836 rc = otx2_flow_init(dev);
1838 goto free_mac_addrs;
1840 otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
1841 " rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
1842 eth_dev->data->port_id, dev->pf, dev->vf,
1843 OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,
1844 dev->rx_offload_capa, dev->tx_offload_capa);
1848 rte_free(eth_dev->data->mac_addrs);
1850 otx2_nix_unregister_irqs(eth_dev);
1852 otx2_eth_dev_lf_detach(dev->mbox);
1856 otx2_dev_fini(pci_dev, dev);
1858 otx2_err("Failed to init nix eth_dev rc=%d", rc);
1863 otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
1865 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1866 struct rte_pci_device *pci_dev;
1869 /* Nothing to be done for secondary processes */
1870 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1873 /* Clear the flag since we are closing down */
1874 dev->configured = 0;
1876 /* Disable nix bpid config */
1877 otx2_nix_rxchan_bpid_cfg(eth_dev, false);
1879 npc_rx_disable(dev);
1881 /* Disable vlan offloads */
1882 otx2_nix_vlan_fini(eth_dev);
1884 /* Disable other rte_flow entries */
1885 otx2_flow_fini(dev);
1887 /* Disable PTP if already enabled */
1888 if (otx2_ethdev_is_ptp_en(dev))
1889 otx2_nix_timesync_disable(eth_dev);
1891 nix_cgx_stop_link_event(dev);
1894 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1895 otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
1896 eth_dev->data->tx_queues[i] = NULL;
1898 eth_dev->data->nb_tx_queues = 0;
1900 /* Free up RQ's and CQ's */
1901 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1902 otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
1903 eth_dev->data->rx_queues[i] = NULL;
1905 eth_dev->data->nb_rx_queues = 0;
1907 /* Free tm resources */
1908 rc = otx2_nix_tm_fini(eth_dev);
1910 otx2_err("Failed to cleanup tm, rc=%d", rc);
1912 /* Unregister queue irqs */
1913 oxt2_nix_unregister_queue_irqs(eth_dev);
1915 /* Unregister cq irqs */
1916 if (eth_dev->data->dev_conf.intr_conf.rxq)
1917 oxt2_nix_unregister_cq_irqs(eth_dev);
1919 rc = nix_lf_free(dev);
1921 otx2_err("Failed to free nix lf, rc=%d", rc);
1923 rc = otx2_npa_lf_fini();
1925 otx2_err("Failed to cleanup npa lf, rc=%d", rc);
1927 rte_free(eth_dev->data->mac_addrs);
1928 eth_dev->data->mac_addrs = NULL;
1929 dev->drv_inited = false;
1931 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1932 otx2_nix_unregister_irqs(eth_dev);
1934 rc = otx2_eth_dev_lf_detach(dev->mbox);
1936 otx2_err("Failed to detach resources, rc=%d", rc);
1938 /* Check if mbox close is needed */
1942 if (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {
1943 /* Will be freed later by PMD */
1944 eth_dev->data->dev_private = NULL;
1948 otx2_dev_fini(pci_dev, dev);
1953 otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
1955 otx2_eth_dev_uninit(eth_dev, true);
1959 otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
1963 rc = otx2_eth_dev_uninit(eth_dev, false);
1967 return otx2_eth_dev_init(eth_dev);
1971 nix_remove(struct rte_pci_device *pci_dev)
1973 struct rte_eth_dev *eth_dev;
1974 struct otx2_idev_cfg *idev;
1975 struct otx2_dev *otx2_dev;
1978 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
1980 /* Cleanup eth dev */
1981 rc = otx2_eth_dev_uninit(eth_dev, true);
1985 rte_eth_dev_pci_release(eth_dev);
1988 /* Nothing to be done for secondary processes */
1989 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1992 /* Check for common resources */
1993 idev = otx2_intra_dev_get_cfg();
1994 if (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)
1997 otx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);
1999 if (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))
2002 /* Safe to cleanup mbox as no more users */
2003 otx2_dev_fini(pci_dev, otx2_dev);
2008 otx2_info("%s: common resource in use by other devices", pci_dev->name);
2013 nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
2017 RTE_SET_USED(pci_drv);
2019 rc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),
2022 /* On error on secondary, recheck if port exists in primary or
2023 * in mid of detach state.
2025 if (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)
2026 if (!rte_eth_dev_allocated(pci_dev->device.name))
2031 static const struct rte_pci_id pci_nix_map[] = {
2033 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)
2036 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)
2039 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
2040 PCI_DEVID_OCTEONTX2_RVU_AF_VF)
2047 static struct rte_pci_driver pci_nix = {
2048 .id_table = pci_nix_map,
2049 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
2050 RTE_PCI_DRV_INTR_LSC,
2052 .remove = nix_remove,
2055 RTE_PMD_REGISTER_PCI(net_octeontx2, pci_nix);
2056 RTE_PMD_REGISTER_PCI_TABLE(net_octeontx2, pci_nix_map);
2057 RTE_PMD_REGISTER_KMOD_DEP(net_octeontx2, "vfio-pci");