1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_ETHDEV_H__
6 #define __OTX2_ETHDEV_H__
10 #include <rte_common.h>
11 #include <rte_ethdev.h>
12 #include <rte_kvargs.h>
14 #include <rte_mempool.h>
15 #include <rte_string_fns.h>
17 #include "otx2_common.h"
20 #include "otx2_mempool.h"
25 #define OTX2_ETH_DEV_PMD_VERSION "1.0"
27 /* Ethdev HWCAP and Fixup flags. Use from MSB bits to avoid conflict with dev */
29 /* Minimum CQ size should be 4K */
30 #define OTX2_FIXUP_F_MIN_4K_Q BIT_ULL(63)
31 #define otx2_ethdev_fixup_is_min_4k_q(dev) \
32 ((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)
33 /* Limit CQ being full */
34 #define OTX2_FIXUP_F_LIMIT_CQ_FULL BIT_ULL(62)
35 #define otx2_ethdev_fixup_is_limit_cq_full(dev) \
36 ((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)
38 /* Used for struct otx2_eth_dev::flags */
39 #define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
41 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
42 * In Tx space is always reserved for this in FRS.
44 #define NIX_MAX_VTAG_INS 2
45 #define NIX_MAX_VTAG_ACT_SIZE (4 * NIX_MAX_VTAG_INS)
47 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
48 #define NIX_L2_OVERHEAD \
49 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
51 /* HW config of frame size doesn't include FCS */
52 #define NIX_MAX_HW_FRS 9212
53 #define NIX_MIN_HW_FRS 60
55 /* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
57 (NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)
60 (NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
63 (NIX_MAX_FRS - NIX_L2_OVERHEAD)
65 #define NIX_MAX_SQB 512
66 #define NIX_MIN_SQB 32
67 #define NIX_SQB_LIST_SPACE 2
68 #define NIX_RSS_RETA_SIZE_MAX 256
69 /* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
70 #define NIX_RSS_GRPS 8
71 #define NIX_HASH_KEY_SIZE 48 /* 352 Bits */
72 #define NIX_RSS_RETA_SIZE 64
73 #define NIX_RX_MIN_DESC 16
74 #define NIX_RX_MIN_DESC_ALIGN 16
75 #define NIX_RX_NB_SEG_MAX 6
76 #define NIX_CQ_ENTRY_SZ 128
77 #define NIX_CQ_ALIGN 512
78 #define NIX_SQB_LOWER_THRESH 90
79 #define LMT_SLOT_MASK 0x7f
81 /* If PTP is enabled additional SEND MEM DESC is required which
82 * takes 2 words, hence max 7 iova address are possible
84 #if defined(RTE_LIBRTE_IEEE1588)
85 #define NIX_TX_NB_SEG_MAX 7
87 #define NIX_TX_NB_SEG_MAX 9
90 /* Apply BP when CQ is 75% full */
91 #define NIX_CQ_BP_LEVEL (25 * 256 / 100)
93 #define CQ_OP_STAT_OP_ERR 63
94 #define CQ_OP_STAT_CQ_ERR 46
96 #define OP_ERR BIT_ULL(CQ_OP_STAT_OP_ERR)
97 #define CQ_ERR BIT_ULL(CQ_OP_STAT_CQ_ERR)
99 #define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
100 ETH_RSS_TCP | ETH_RSS_SCTP | \
101 ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD)
103 #define NIX_TX_OFFLOAD_CAPA ( \
104 DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
105 DEV_TX_OFFLOAD_MT_LOCKFREE | \
106 DEV_TX_OFFLOAD_VLAN_INSERT | \
107 DEV_TX_OFFLOAD_QINQ_INSERT | \
108 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
109 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
110 DEV_TX_OFFLOAD_TCP_CKSUM | \
111 DEV_TX_OFFLOAD_UDP_CKSUM | \
112 DEV_TX_OFFLOAD_SCTP_CKSUM | \
113 DEV_TX_OFFLOAD_MULTI_SEGS | \
114 DEV_TX_OFFLOAD_IPV4_CKSUM)
116 #define NIX_RX_OFFLOAD_CAPA ( \
117 DEV_RX_OFFLOAD_CHECKSUM | \
118 DEV_RX_OFFLOAD_SCTP_CKSUM | \
119 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
120 DEV_RX_OFFLOAD_SCATTER | \
121 DEV_RX_OFFLOAD_JUMBO_FRAME | \
122 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
123 DEV_RX_OFFLOAD_VLAN_STRIP | \
124 DEV_RX_OFFLOAD_VLAN_FILTER | \
125 DEV_RX_OFFLOAD_QINQ_STRIP | \
126 DEV_RX_OFFLOAD_TIMESTAMP)
128 #define NIX_DEFAULT_RSS_CTX_GROUP 0
129 #define NIX_DEFAULT_RSS_MCAM_IDX -1
132 nix_q_size_16, /* 16 entries */
133 nix_q_size_64, /* 64 entries */
140 nix_q_size_1M, /* Million entries */
145 struct rte_eth_dev *eth_dev;
149 struct otx2_rss_info {
151 uint32_t flowkey_cfg;
154 uint8_t alg_idx; /* Selected algo index */
155 uint16_t ind_tbl[NIX_RSS_RETA_SIZE_MAX];
156 uint8_t key[NIX_HASH_KEY_SIZE];
159 struct otx2_eth_qconf {
161 struct rte_eth_txconf tx;
162 struct rte_eth_rxconf rx;
169 struct otx2_npc_flow_info {
170 uint16_t channel; /*rx channel */
171 uint16_t flow_prealloc_size;
172 uint16_t flow_max_priority;
175 struct otx2_fc_info {
176 enum rte_eth_fc_mode mode; /**< Link flow control mode */
180 uint16_t bpid[NIX_MAX_CHAN];
183 struct otx2_eth_dev {
184 OTX2_DEV; /* Base class */
185 MARKER otx2_eth_dev_data_start;
187 uint16_t rx_chan_base;
188 uint16_t tx_chan_base;
191 uint8_t lso_tsov4_idx;
192 uint8_t lso_tsov6_idx;
193 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
194 uint8_t max_mac_entries;
201 uint8_t configured_qints;
202 uint8_t configured_nb_rx_qs;
203 uint8_t configured_nb_tx_qs;
204 uint16_t nix_msixoff;
208 uint16_t max_sqb_count;
209 uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
210 uint64_t rx_offloads;
211 uint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */
212 uint64_t tx_offloads;
213 uint64_t rx_offload_capa;
214 uint64_t tx_offload_capa;
215 struct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];
216 uint16_t txschq[NIX_TXSCH_LVL_CNT];
217 uint16_t txschq_contig[NIX_TXSCH_LVL_CNT];
218 uint16_t txschq_index[NIX_TXSCH_LVL_CNT];
219 uint16_t txschq_contig_index[NIX_TXSCH_LVL_CNT];
220 /* Dis-contiguous queues */
221 uint16_t txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
222 /* Contiguous queues */
223 uint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
224 uint16_t otx2_tm_root_lvl;
226 uint16_t tm_leaf_cnt;
227 struct otx2_nix_tm_node_list node_list;
228 struct otx2_nix_tm_shaper_profile_list shaper_profile_list;
229 struct otx2_rss_info rss_info;
230 struct otx2_fc_info fc_info;
231 uint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
232 uint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
233 struct otx2_npc_flow_info npc_flow;
234 struct otx2_eth_qconf *tx_qconf;
235 struct otx2_eth_qconf *rx_qconf;
236 struct rte_eth_dev *eth_dev;
237 } __rte_cache_aligned;
239 struct otx2_eth_txq {
241 int64_t fc_cache_pkts;
246 uint16_t sqes_per_sqb_log2;
247 int16_t nb_sqb_bufs_adj;
248 MARKER slow_path_start;
249 uint16_t nb_sqb_bufs;
252 struct otx2_eth_dev *dev;
253 struct rte_mempool *sqb_pool;
254 struct otx2_eth_qconf qconf;
255 } __rte_cache_aligned;
257 struct otx2_eth_rxq {
258 uint64_t mbuf_initializer;
269 struct otx2_timesync_info *tstamp;
270 MARKER slow_path_start;
274 struct rte_mempool *pool;
275 enum nix_q_size_e qsize;
276 struct rte_eth_dev *eth_dev;
277 struct otx2_eth_qconf qconf;
278 } __rte_cache_aligned;
280 static inline struct otx2_eth_dev *
281 otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
283 return eth_dev->data->dev_private;
287 void otx2_nix_info_get(struct rte_eth_dev *eth_dev,
288 struct rte_eth_dev_info *dev_info);
289 int otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
290 struct rte_eth_dev_module_info *modinfo);
291 int otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
292 struct rte_dev_eeprom_info *info);
293 int otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
294 void otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
295 struct rte_eth_rxq_info *qinfo);
296 void otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
297 struct rte_eth_txq_info *qinfo);
298 uint32_t otx2_nix_rx_queue_count(struct rte_eth_dev *eth_dev, uint16_t qidx);
299 int otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
300 int otx2_nix_rx_descriptor_done(void *rxq, uint16_t offset);
301 int otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset);
303 void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en);
304 void otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);
305 void otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);
306 void otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
307 void otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
308 int otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx);
309 int otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx);
310 uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);
313 void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
314 int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
315 void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
316 struct cgx_link_user_info *link);
319 int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
320 int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);
321 void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
322 void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
325 int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);
326 int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
327 struct rte_dev_reg_info *regs);
328 int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
329 void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
332 int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
333 struct rte_eth_stats *stats);
334 void otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev);
336 int otx2_nix_queue_stats_mapping(struct rte_eth_dev *dev,
337 uint16_t queue_id, uint8_t stat_idx,
339 int otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,
340 struct rte_eth_xstat *xstats, unsigned int n);
341 int otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
342 struct rte_eth_xstat_name *xstats_names,
344 void otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev);
346 int otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev,
348 uint64_t *values, unsigned int n);
349 int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
350 struct rte_eth_xstat_name *xstats_names,
351 const uint64_t *ids, unsigned int limit);
354 void otx2_nix_rss_set_key(struct otx2_eth_dev *dev,
355 uint8_t *key, uint32_t key_len);
356 uint32_t otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev,
357 uint64_t ethdev_rss, uint8_t rss_level);
358 int otx2_rss_set_hf(struct otx2_eth_dev *dev,
359 uint32_t flowkey_cfg, uint8_t *alg_idx,
360 uint8_t group, int mcam_index);
361 int otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev, uint8_t group,
363 int otx2_nix_rss_config(struct rte_eth_dev *eth_dev);
365 int otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,
366 struct rte_eth_rss_reta_entry64 *reta_conf,
368 int otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,
369 struct rte_eth_rss_reta_entry64 *reta_conf,
371 int otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
372 struct rte_eth_rss_conf *rss_conf);
374 int otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
375 struct rte_eth_rss_conf *rss_conf);
378 int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
379 int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);
380 int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
381 struct rte_ether_addr *addr);
384 int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
385 struct rte_eth_fc_conf *fc_conf);
387 int otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
388 struct rte_eth_fc_conf *fc_conf);
390 int otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb);
392 int otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev);
394 /* Lookup configuration */
395 void *otx2_nix_fastpath_lookup_mem_get(void);
398 const uint32_t *otx2_nix_supported_ptypes_get(struct rte_eth_dev *dev);
400 /* Mac address handling */
401 int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
402 struct rte_ether_addr *addr);
403 int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
404 int otx2_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
405 struct rte_ether_addr *addr,
406 uint32_t index, uint32_t pool);
407 void otx2_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
408 int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
411 int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
412 struct otx2_eth_dev *dev);
414 /* Rx and Tx routines */
415 void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);
417 #endif /* __OTX2_ETHDEV_H__ */