1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_ETHDEV_H__
6 #define __OTX2_ETHDEV_H__
10 #include <rte_common.h>
11 #include <rte_ethdev.h>
12 #include <rte_kvargs.h>
14 #include <rte_mempool.h>
15 #include <rte_string_fns.h>
17 #include "otx2_common.h"
20 #include "otx2_mempool.h"
24 #define OTX2_ETH_DEV_PMD_VERSION "1.0"
26 /* Ethdev HWCAP and Fixup flags. Use from MSB bits to avoid conflict with dev */
28 /* Minimum CQ size should be 4K */
29 #define OTX2_FIXUP_F_MIN_4K_Q BIT_ULL(63)
30 #define otx2_ethdev_fixup_is_min_4k_q(dev) \
31 ((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)
32 /* Limit CQ being full */
33 #define OTX2_FIXUP_F_LIMIT_CQ_FULL BIT_ULL(62)
34 #define otx2_ethdev_fixup_is_limit_cq_full(dev) \
35 ((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)
37 /* Used for struct otx2_eth_dev::flags */
38 #define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
40 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
41 * In Tx space is always reserved for this in FRS.
43 #define NIX_MAX_VTAG_INS 2
44 #define NIX_MAX_VTAG_ACT_SIZE (4 * NIX_MAX_VTAG_INS)
46 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
47 #define NIX_L2_OVERHEAD \
48 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
50 /* HW config of frame size doesn't include FCS */
51 #define NIX_MAX_HW_FRS 9212
52 #define NIX_MIN_HW_FRS 60
54 /* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
56 (NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)
59 (NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
62 (NIX_MAX_FRS - NIX_L2_OVERHEAD)
64 #define NIX_MAX_SQB 512
65 #define NIX_MIN_SQB 32
66 #define NIX_SQB_LIST_SPACE 2
67 #define NIX_RSS_RETA_SIZE_MAX 256
68 /* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
69 #define NIX_RSS_GRPS 8
70 #define NIX_HASH_KEY_SIZE 48 /* 352 Bits */
71 #define NIX_RSS_RETA_SIZE 64
72 #define NIX_RX_MIN_DESC 16
73 #define NIX_RX_MIN_DESC_ALIGN 16
74 #define NIX_RX_NB_SEG_MAX 6
75 #define NIX_CQ_ENTRY_SZ 128
76 #define NIX_CQ_ALIGN 512
77 #define NIX_SQB_LOWER_THRESH 90
78 #define LMT_SLOT_MASK 0x7f
80 /* If PTP is enabled additional SEND MEM DESC is required which
81 * takes 2 words, hence max 7 iova address are possible
83 #if defined(RTE_LIBRTE_IEEE1588)
84 #define NIX_TX_NB_SEG_MAX 7
86 #define NIX_TX_NB_SEG_MAX 9
89 #define CQ_OP_STAT_OP_ERR 63
90 #define CQ_OP_STAT_CQ_ERR 46
92 #define OP_ERR BIT_ULL(CQ_OP_STAT_OP_ERR)
93 #define CQ_ERR BIT_ULL(CQ_OP_STAT_CQ_ERR)
95 #define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
96 ETH_RSS_TCP | ETH_RSS_SCTP | \
97 ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD)
99 #define NIX_TX_OFFLOAD_CAPA ( \
100 DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
101 DEV_TX_OFFLOAD_MT_LOCKFREE | \
102 DEV_TX_OFFLOAD_VLAN_INSERT | \
103 DEV_TX_OFFLOAD_QINQ_INSERT | \
104 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
105 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
106 DEV_TX_OFFLOAD_TCP_CKSUM | \
107 DEV_TX_OFFLOAD_UDP_CKSUM | \
108 DEV_TX_OFFLOAD_SCTP_CKSUM | \
109 DEV_TX_OFFLOAD_MULTI_SEGS | \
110 DEV_TX_OFFLOAD_IPV4_CKSUM)
112 #define NIX_RX_OFFLOAD_CAPA ( \
113 DEV_RX_OFFLOAD_CHECKSUM | \
114 DEV_RX_OFFLOAD_SCTP_CKSUM | \
115 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
116 DEV_RX_OFFLOAD_SCATTER | \
117 DEV_RX_OFFLOAD_JUMBO_FRAME | \
118 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
119 DEV_RX_OFFLOAD_VLAN_STRIP | \
120 DEV_RX_OFFLOAD_VLAN_FILTER | \
121 DEV_RX_OFFLOAD_QINQ_STRIP | \
122 DEV_RX_OFFLOAD_TIMESTAMP)
124 #define NIX_DEFAULT_RSS_CTX_GROUP 0
125 #define NIX_DEFAULT_RSS_MCAM_IDX -1
128 nix_q_size_16, /* 16 entries */
129 nix_q_size_64, /* 64 entries */
136 nix_q_size_1M, /* Million entries */
141 struct rte_eth_dev *eth_dev;
145 struct otx2_rss_info {
147 uint32_t flowkey_cfg;
150 uint8_t alg_idx; /* Selected algo index */
151 uint16_t ind_tbl[NIX_RSS_RETA_SIZE_MAX];
152 uint8_t key[NIX_HASH_KEY_SIZE];
155 struct otx2_eth_qconf {
157 struct rte_eth_txconf tx;
158 struct rte_eth_rxconf rx;
165 struct otx2_npc_flow_info {
166 uint16_t channel; /*rx channel */
167 uint16_t flow_prealloc_size;
168 uint16_t flow_max_priority;
171 struct otx2_eth_dev {
172 OTX2_DEV; /* Base class */
173 MARKER otx2_eth_dev_data_start;
175 uint16_t rx_chan_base;
176 uint16_t tx_chan_base;
179 uint8_t lso_tsov4_idx;
180 uint8_t lso_tsov6_idx;
181 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
182 uint8_t max_mac_entries;
189 uint8_t configured_qints;
190 uint8_t configured_nb_rx_qs;
191 uint8_t configured_nb_tx_qs;
192 uint16_t nix_msixoff;
196 uint16_t max_sqb_count;
197 uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
198 uint64_t rx_offloads;
199 uint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */
200 uint64_t tx_offloads;
201 uint64_t rx_offload_capa;
202 uint64_t tx_offload_capa;
203 struct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];
204 struct otx2_rss_info rss_info;
205 uint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
206 uint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
207 struct otx2_npc_flow_info npc_flow;
208 struct otx2_eth_qconf *tx_qconf;
209 struct otx2_eth_qconf *rx_qconf;
210 struct rte_eth_dev *eth_dev;
211 } __rte_cache_aligned;
213 struct otx2_eth_txq {
215 int64_t fc_cache_pkts;
220 uint16_t sqes_per_sqb_log2;
221 int16_t nb_sqb_bufs_adj;
222 MARKER slow_path_start;
223 uint16_t nb_sqb_bufs;
226 struct otx2_eth_dev *dev;
227 struct rte_mempool *sqb_pool;
228 struct otx2_eth_qconf qconf;
229 } __rte_cache_aligned;
231 struct otx2_eth_rxq {
232 uint64_t mbuf_initializer;
243 struct otx2_timesync_info *tstamp;
244 MARKER slow_path_start;
248 struct rte_mempool *pool;
249 enum nix_q_size_e qsize;
250 struct rte_eth_dev *eth_dev;
251 struct otx2_eth_qconf qconf;
252 } __rte_cache_aligned;
254 static inline struct otx2_eth_dev *
255 otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
257 return eth_dev->data->dev_private;
261 void otx2_nix_info_get(struct rte_eth_dev *eth_dev,
262 struct rte_eth_dev_info *dev_info);
264 void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en);
265 void otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);
266 void otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);
267 void otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
268 void otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
269 int otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx);
270 int otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx);
271 uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);
274 void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
275 int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
276 void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
277 struct cgx_link_user_info *link);
280 int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
281 int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);
282 void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
283 void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
286 int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);
287 int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
288 struct rte_dev_reg_info *regs);
289 int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
290 void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
293 int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
294 struct rte_eth_stats *stats);
295 void otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev);
297 int otx2_nix_queue_stats_mapping(struct rte_eth_dev *dev,
298 uint16_t queue_id, uint8_t stat_idx,
300 int otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,
301 struct rte_eth_xstat *xstats, unsigned int n);
302 int otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
303 struct rte_eth_xstat_name *xstats_names,
305 void otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev);
307 int otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev,
309 uint64_t *values, unsigned int n);
310 int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
311 struct rte_eth_xstat_name *xstats_names,
312 const uint64_t *ids, unsigned int limit);
315 void otx2_nix_rss_set_key(struct otx2_eth_dev *dev,
316 uint8_t *key, uint32_t key_len);
317 uint32_t otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev,
318 uint64_t ethdev_rss, uint8_t rss_level);
319 int otx2_rss_set_hf(struct otx2_eth_dev *dev,
320 uint32_t flowkey_cfg, uint8_t *alg_idx,
321 uint8_t group, int mcam_index);
322 int otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev, uint8_t group,
324 int otx2_nix_rss_config(struct rte_eth_dev *eth_dev);
326 int otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,
327 struct rte_eth_rss_reta_entry64 *reta_conf,
329 int otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,
330 struct rte_eth_rss_reta_entry64 *reta_conf,
332 int otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
333 struct rte_eth_rss_conf *rss_conf);
335 int otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
336 struct rte_eth_rss_conf *rss_conf);
339 int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
340 int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);
341 int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
342 struct rte_ether_addr *addr);
344 /* Mac address handling */
345 int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
346 struct rte_ether_addr *addr);
347 int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
348 int otx2_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
349 struct rte_ether_addr *addr,
350 uint32_t index, uint32_t pool);
351 void otx2_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
352 int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
355 int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
356 struct otx2_eth_dev *dev);
358 /* Rx and Tx routines */
359 void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);
361 #endif /* __OTX2_ETHDEV_H__ */