1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_ETHDEV_H__
6 #define __OTX2_ETHDEV_H__
10 #include <rte_common.h>
11 #include <rte_ethdev.h>
12 #include <rte_kvargs.h>
14 #include "otx2_common.h"
17 #include "otx2_mempool.h"
20 #define OTX2_ETH_DEV_PMD_VERSION "1.0"
22 /* Ethdev HWCAP and Fixup flags. Use from MSB bits to avoid conflict with dev */
24 /* Minimum CQ size should be 4K */
25 #define OTX2_FIXUP_F_MIN_4K_Q BIT_ULL(63)
26 #define otx2_ethdev_fixup_is_min_4k_q(dev) \
27 ((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)
28 /* Limit CQ being full */
29 #define OTX2_FIXUP_F_LIMIT_CQ_FULL BIT_ULL(62)
30 #define otx2_ethdev_fixup_is_limit_cq_full(dev) \
31 ((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)
33 /* Used for struct otx2_eth_dev::flags */
34 #define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
36 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
37 * In Tx space is always reserved for this in FRS.
39 #define NIX_MAX_VTAG_INS 2
40 #define NIX_MAX_VTAG_ACT_SIZE (4 * NIX_MAX_VTAG_INS)
42 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
43 #define NIX_L2_OVERHEAD \
44 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
46 /* HW config of frame size doesn't include FCS */
47 #define NIX_MAX_HW_FRS 9212
48 #define NIX_MIN_HW_FRS 60
50 /* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
52 (NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)
55 (NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
58 (NIX_MAX_FRS - NIX_L2_OVERHEAD)
60 #define NIX_MAX_SQB 512
61 #define NIX_MIN_SQB 32
62 #define NIX_HASH_KEY_SIZE 48 /* 352 Bits */
63 #define NIX_RSS_RETA_SIZE 64
64 #define NIX_RX_MIN_DESC 16
65 #define NIX_RX_MIN_DESC_ALIGN 16
66 #define NIX_RX_NB_SEG_MAX 6
68 /* If PTP is enabled additional SEND MEM DESC is required which
69 * takes 2 words, hence max 7 iova address are possible
71 #if defined(RTE_LIBRTE_IEEE1588)
72 #define NIX_TX_NB_SEG_MAX 7
74 #define NIX_TX_NB_SEG_MAX 9
77 #define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
78 ETH_RSS_TCP | ETH_RSS_SCTP | \
79 ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD)
81 #define NIX_TX_OFFLOAD_CAPA ( \
82 DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
83 DEV_TX_OFFLOAD_MT_LOCKFREE | \
84 DEV_TX_OFFLOAD_VLAN_INSERT | \
85 DEV_TX_OFFLOAD_QINQ_INSERT | \
86 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
87 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
88 DEV_TX_OFFLOAD_TCP_CKSUM | \
89 DEV_TX_OFFLOAD_UDP_CKSUM | \
90 DEV_TX_OFFLOAD_SCTP_CKSUM | \
91 DEV_TX_OFFLOAD_MULTI_SEGS | \
92 DEV_TX_OFFLOAD_IPV4_CKSUM)
94 #define NIX_RX_OFFLOAD_CAPA ( \
95 DEV_RX_OFFLOAD_CHECKSUM | \
96 DEV_RX_OFFLOAD_SCTP_CKSUM | \
97 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
98 DEV_RX_OFFLOAD_SCATTER | \
99 DEV_RX_OFFLOAD_JUMBO_FRAME | \
100 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
101 DEV_RX_OFFLOAD_VLAN_STRIP | \
102 DEV_RX_OFFLOAD_VLAN_FILTER | \
103 DEV_RX_OFFLOAD_QINQ_STRIP | \
104 DEV_RX_OFFLOAD_TIMESTAMP)
106 struct otx2_rss_info {
110 struct otx2_npc_flow_info {
111 uint16_t flow_prealloc_size;
112 uint16_t flow_max_priority;
115 struct otx2_eth_dev {
116 OTX2_DEV; /* Base class */
117 MARKER otx2_eth_dev_data_start;
119 uint16_t rx_chan_base;
120 uint16_t tx_chan_base;
123 uint8_t lso_tsov4_idx;
124 uint8_t lso_tsov6_idx;
125 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
126 uint8_t max_mac_entries;
128 uint16_t nix_msixoff;
132 uint16_t max_sqb_count;
133 uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
134 uint64_t rx_offloads;
135 uint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */
136 uint64_t tx_offloads;
137 uint64_t rx_offload_capa;
138 uint64_t tx_offload_capa;
139 struct otx2_rss_info rss_info;
140 struct otx2_npc_flow_info npc_flow;
141 } __rte_cache_aligned;
143 static inline struct otx2_eth_dev *
144 otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
146 return eth_dev->data->dev_private;
150 void otx2_nix_info_get(struct rte_eth_dev *eth_dev,
151 struct rte_eth_dev_info *dev_info);
154 int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
155 void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
158 int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
159 int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);
160 int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
161 struct rte_ether_addr *addr);
163 /* Mac address handling */
164 int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
165 int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
168 int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
169 struct otx2_eth_dev *dev);
171 #endif /* __OTX2_ETHDEV_H__ */