1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_ETHDEV_H__
6 #define __OTX2_ETHDEV_H__
11 #include <rte_common.h>
12 #include <rte_ethdev.h>
13 #include <rte_kvargs.h>
15 #include <rte_mempool.h>
16 #include <rte_string_fns.h>
19 #include "otx2_common.h"
21 #include "otx2_flow.h"
23 #include "otx2_mempool.h"
28 #define OTX2_ETH_DEV_PMD_VERSION "1.0"
30 /* Ethdev HWCAP and Fixup flags. Use from MSB bits to avoid conflict with dev */
32 /* Minimum CQ size should be 4K */
33 #define OTX2_FIXUP_F_MIN_4K_Q BIT_ULL(63)
34 #define otx2_ethdev_fixup_is_min_4k_q(dev) \
35 ((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)
36 /* Limit CQ being full */
37 #define OTX2_FIXUP_F_LIMIT_CQ_FULL BIT_ULL(62)
38 #define otx2_ethdev_fixup_is_limit_cq_full(dev) \
39 ((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)
41 /* Used for struct otx2_eth_dev::flags */
42 #define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
44 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
45 * In Tx space is always reserved for this in FRS.
47 #define NIX_MAX_VTAG_INS 2
48 #define NIX_MAX_VTAG_ACT_SIZE (4 * NIX_MAX_VTAG_INS)
50 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
51 #define NIX_L2_OVERHEAD \
52 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
54 /* HW config of frame size doesn't include FCS */
55 #define NIX_MAX_HW_FRS 9212
56 #define NIX_MIN_HW_FRS 60
58 /* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
60 (NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)
63 (NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
66 (NIX_MAX_FRS - NIX_L2_OVERHEAD)
68 #define NIX_MAX_SQB 512
69 #define NIX_MIN_SQB 32
70 #define NIX_SQB_LIST_SPACE 2
71 #define NIX_RSS_RETA_SIZE_MAX 256
72 /* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
73 #define NIX_RSS_GRPS 8
74 #define NIX_HASH_KEY_SIZE 48 /* 352 Bits */
75 #define NIX_RSS_RETA_SIZE 64
76 #define NIX_RX_MIN_DESC 16
77 #define NIX_RX_MIN_DESC_ALIGN 16
78 #define NIX_RX_NB_SEG_MAX 6
79 #define NIX_CQ_ENTRY_SZ 128
80 #define NIX_CQ_ALIGN 512
81 #define NIX_SQB_LOWER_THRESH 90
82 #define LMT_SLOT_MASK 0x7f
84 /* If PTP is enabled additional SEND MEM DESC is required which
85 * takes 2 words, hence max 7 iova address are possible
87 #if defined(RTE_LIBRTE_IEEE1588)
88 #define NIX_TX_NB_SEG_MAX 7
90 #define NIX_TX_NB_SEG_MAX 9
93 #define NIX_TX_MSEG_SG_DWORDS \
94 ((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3) \
97 /* Apply BP when CQ is 75% full */
98 #define NIX_CQ_BP_LEVEL (25 * 256 / 100)
100 #define CQ_OP_STAT_OP_ERR 63
101 #define CQ_OP_STAT_CQ_ERR 46
103 #define OP_ERR BIT_ULL(CQ_OP_STAT_OP_ERR)
104 #define CQ_ERR BIT_ULL(CQ_OP_STAT_CQ_ERR)
106 #define CQ_CQE_THRESH_DEFAULT 0x1ULL /* IRQ triggered when
107 * NIX_LF_CINTX_CNT[QCOUNT]
110 #define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
111 #define CQ_TIMER_THRESH_MAX 255
113 #define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
114 ETH_RSS_TCP | ETH_RSS_SCTP | \
115 ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD)
117 #define NIX_TX_OFFLOAD_CAPA ( \
118 DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
119 DEV_TX_OFFLOAD_MT_LOCKFREE | \
120 DEV_TX_OFFLOAD_VLAN_INSERT | \
121 DEV_TX_OFFLOAD_QINQ_INSERT | \
122 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
123 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
124 DEV_TX_OFFLOAD_TCP_CKSUM | \
125 DEV_TX_OFFLOAD_UDP_CKSUM | \
126 DEV_TX_OFFLOAD_SCTP_CKSUM | \
127 DEV_TX_OFFLOAD_MULTI_SEGS | \
128 DEV_TX_OFFLOAD_IPV4_CKSUM)
130 #define NIX_RX_OFFLOAD_CAPA ( \
131 DEV_RX_OFFLOAD_CHECKSUM | \
132 DEV_RX_OFFLOAD_SCTP_CKSUM | \
133 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
134 DEV_RX_OFFLOAD_SCATTER | \
135 DEV_RX_OFFLOAD_JUMBO_FRAME | \
136 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
137 DEV_RX_OFFLOAD_VLAN_STRIP | \
138 DEV_RX_OFFLOAD_VLAN_FILTER | \
139 DEV_RX_OFFLOAD_QINQ_STRIP | \
140 DEV_RX_OFFLOAD_TIMESTAMP)
142 #define NIX_DEFAULT_RSS_CTX_GROUP 0
143 #define NIX_DEFAULT_RSS_MCAM_IDX -1
145 #define otx2_ethdev_is_ptp_en(dev) ((dev)->ptp_en)
147 #define NIX_TIMESYNC_TX_CMD_LEN 8
148 /* Additional timesync values. */
149 #define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL
152 nix_q_size_16, /* 16 entries */
153 nix_q_size_64, /* 64 entries */
160 nix_q_size_1M, /* Million entries */
165 struct rte_eth_dev *eth_dev;
169 struct otx2_rss_info {
171 uint32_t flowkey_cfg;
174 uint8_t alg_idx; /* Selected algo index */
175 uint16_t ind_tbl[NIX_RSS_RETA_SIZE_MAX];
176 uint8_t key[NIX_HASH_KEY_SIZE];
179 struct otx2_eth_qconf {
181 struct rte_eth_txconf tx;
182 struct rte_eth_rxconf rx;
189 struct otx2_fc_info {
190 enum rte_eth_fc_mode mode; /**< Link flow control mode */
194 uint16_t bpid[NIX_MAX_CHAN];
197 struct vlan_mkex_info {
198 struct npc_xtract_info la_xtract;
199 struct npc_xtract_info lb_xtract;
200 uint64_t lb_lt_offset;
206 TAILQ_ENTRY(vlan_entry) next;
209 TAILQ_HEAD(otx2_vlan_filter_tbl, vlan_entry);
211 struct otx2_vlan_info {
212 struct otx2_vlan_filter_tbl fltr_tbl;
213 /* MKEX layer info */
214 struct mcam_entry def_tx_mcam_ent;
215 struct mcam_entry def_rx_mcam_ent;
216 struct vlan_mkex_info mkex;
217 /* Default mcam entry that matches vlan packets */
218 uint32_t def_rx_mcam_idx;
219 uint32_t def_tx_mcam_idx;
220 /* MCAM entry that matches double vlan packets */
221 uint32_t qinq_mcam_idx;
222 /* Indices of tx_vtag def registers */
223 uint32_t outer_vlan_idx;
224 uint32_t inner_vlan_idx;
225 uint16_t outer_vlan_tpid;
226 uint16_t inner_vlan_tpid;
228 /* QinQ entry allocated before default one */
229 uint8_t qinq_before_def;
230 uint8_t pvid_insert_on;
231 /* Rx vtag action type */
232 uint8_t vtag_type_idx;
239 struct otx2_eth_dev {
240 OTX2_DEV; /* Base class */
241 MARKER otx2_eth_dev_data_start;
243 uint16_t rx_chan_base;
244 uint16_t tx_chan_base;
247 uint8_t lso_tsov4_idx;
248 uint8_t lso_tsov6_idx;
249 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
250 uint8_t mkex_pfl_name[MKEX_NAME_LEN];
251 uint8_t max_mac_entries;
258 uint8_t configured_qints;
259 uint8_t configured_cints;
260 uint8_t configured_nb_rx_qs;
261 uint8_t configured_nb_tx_qs;
262 uint16_t nix_msixoff;
266 uint16_t max_sqb_count;
267 uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
268 uint64_t rx_offloads;
269 uint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */
270 uint64_t tx_offloads;
271 uint64_t rx_offload_capa;
272 uint64_t tx_offload_capa;
273 struct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];
274 struct otx2_qint cints_mem[RTE_MAX_QUEUES_PER_PORT];
275 uint16_t txschq[NIX_TXSCH_LVL_CNT];
276 uint16_t txschq_contig[NIX_TXSCH_LVL_CNT];
277 uint16_t txschq_index[NIX_TXSCH_LVL_CNT];
278 uint16_t txschq_contig_index[NIX_TXSCH_LVL_CNT];
279 /* Dis-contiguous queues */
280 uint16_t txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
281 /* Contiguous queues */
282 uint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
283 uint16_t otx2_tm_root_lvl;
285 uint16_t tm_leaf_cnt;
286 struct otx2_nix_tm_node_list node_list;
287 struct otx2_nix_tm_shaper_profile_list shaper_profile_list;
288 struct otx2_rss_info rss_info;
289 struct otx2_fc_info fc_info;
290 uint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
291 uint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
292 struct otx2_npc_flow_info npc_flow;
293 struct otx2_vlan_info vlan_info;
294 struct otx2_eth_qconf *tx_qconf;
295 struct otx2_eth_qconf *rx_qconf;
296 struct rte_eth_dev *eth_dev;
297 eth_rx_burst_t rx_pkt_burst_no_offload;
300 struct otx2_timesync_info tstamp;
301 struct rte_timecounter systime_tc;
302 struct rte_timecounter rx_tstamp_tc;
303 struct rte_timecounter tx_tstamp_tc;
304 double clk_freq_mult;
306 } __rte_cache_aligned;
308 struct otx2_eth_txq {
310 int64_t fc_cache_pkts;
315 uint16_t sqes_per_sqb_log2;
316 int16_t nb_sqb_bufs_adj;
317 MARKER slow_path_start;
318 uint16_t nb_sqb_bufs;
321 struct otx2_eth_dev *dev;
322 struct rte_mempool *sqb_pool;
323 struct otx2_eth_qconf qconf;
324 } __rte_cache_aligned;
326 struct otx2_eth_rxq {
327 uint64_t mbuf_initializer;
338 struct otx2_timesync_info *tstamp;
339 MARKER slow_path_start;
343 struct rte_mempool *pool;
344 enum nix_q_size_e qsize;
345 struct rte_eth_dev *eth_dev;
346 struct otx2_eth_qconf qconf;
347 } __rte_cache_aligned;
349 static inline struct otx2_eth_dev *
350 otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
352 return eth_dev->data->dev_private;
356 void otx2_nix_info_get(struct rte_eth_dev *eth_dev,
357 struct rte_eth_dev_info *dev_info);
358 int otx2_nix_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
359 enum rte_filter_type filter_type,
360 enum rte_filter_op filter_op, void *arg);
361 int otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
363 int otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
364 struct rte_eth_dev_module_info *modinfo);
365 int otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
366 struct rte_dev_eeprom_info *info);
367 int otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
368 void otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
369 struct rte_eth_rxq_info *qinfo);
370 void otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
371 struct rte_eth_txq_info *qinfo);
372 uint32_t otx2_nix_rx_queue_count(struct rte_eth_dev *eth_dev, uint16_t qidx);
373 int otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
374 int otx2_nix_rx_descriptor_done(void *rxq, uint16_t offset);
375 int otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset);
377 void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en);
378 void otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);
379 void otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);
380 void otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
381 void otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
382 int otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx);
383 int otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx);
384 uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);
387 int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
388 int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);
391 void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
392 int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
393 void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
394 struct cgx_link_user_info *link);
395 int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);
396 int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);
399 int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
400 int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);
401 int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
402 void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
403 void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
404 void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
406 int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
407 uint16_t rx_queue_id);
408 int otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
409 uint16_t rx_queue_id);
412 int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);
413 int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
414 struct rte_dev_reg_info *regs);
415 int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
416 void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
419 int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
420 struct rte_eth_stats *stats);
421 void otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev);
423 int otx2_nix_queue_stats_mapping(struct rte_eth_dev *dev,
424 uint16_t queue_id, uint8_t stat_idx,
426 int otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,
427 struct rte_eth_xstat *xstats, unsigned int n);
428 int otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
429 struct rte_eth_xstat_name *xstats_names,
431 void otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev);
433 int otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev,
435 uint64_t *values, unsigned int n);
436 int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
437 struct rte_eth_xstat_name *xstats_names,
438 const uint64_t *ids, unsigned int limit);
441 void otx2_nix_rss_set_key(struct otx2_eth_dev *dev,
442 uint8_t *key, uint32_t key_len);
443 uint32_t otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev,
444 uint64_t ethdev_rss, uint8_t rss_level);
445 int otx2_rss_set_hf(struct otx2_eth_dev *dev,
446 uint32_t flowkey_cfg, uint8_t *alg_idx,
447 uint8_t group, int mcam_index);
448 int otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev, uint8_t group,
450 int otx2_nix_rss_config(struct rte_eth_dev *eth_dev);
452 int otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,
453 struct rte_eth_rss_reta_entry64 *reta_conf,
455 int otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,
456 struct rte_eth_rss_reta_entry64 *reta_conf,
458 int otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
459 struct rte_eth_rss_conf *rss_conf);
461 int otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
462 struct rte_eth_rss_conf *rss_conf);
465 int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
466 int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);
467 int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
468 struct rte_ether_addr *addr);
471 int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
472 struct rte_eth_fc_conf *fc_conf);
474 int otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
475 struct rte_eth_fc_conf *fc_conf);
477 int otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb);
479 int otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev);
482 int otx2_nix_vlan_offload_init(struct rte_eth_dev *eth_dev);
483 int otx2_nix_vlan_fini(struct rte_eth_dev *eth_dev);
484 int otx2_nix_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);
485 void otx2_nix_vlan_update_promisc(struct rte_eth_dev *eth_dev, int enable);
486 int otx2_nix_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
488 void otx2_nix_vlan_strip_queue_set(struct rte_eth_dev *dev,
489 uint16_t queue, int on);
490 int otx2_nix_vlan_tpid_set(struct rte_eth_dev *eth_dev,
491 enum rte_vlan_type type, uint16_t tpid);
492 int otx2_nix_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
494 /* Lookup configuration */
495 void *otx2_nix_fastpath_lookup_mem_get(void);
498 const uint32_t *otx2_nix_supported_ptypes_get(struct rte_eth_dev *dev);
500 /* Mac address handling */
501 int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
502 struct rte_ether_addr *addr);
503 int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
504 int otx2_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
505 struct rte_ether_addr *addr,
506 uint32_t index, uint32_t pool);
507 void otx2_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
508 int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
511 int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
512 struct otx2_eth_dev *dev);
514 /* Rx and Tx routines */
515 void otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev);
516 void otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev);
517 void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);
519 /* Timesync - PTP routines */
520 int otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev);
521 int otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev);
522 int otx2_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
523 struct timespec *timestamp,
525 int otx2_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
526 struct timespec *timestamp);
527 int otx2_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
528 int otx2_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
529 const struct timespec *ts);
530 int otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
531 struct timespec *ts);
532 int otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en);
533 int otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *time);
534 int otx2_nix_raw_clock_tsc_conv(struct otx2_eth_dev *dev);
536 #endif /* __OTX2_ETHDEV_H__ */