1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_ETHDEV_H__
6 #define __OTX2_ETHDEV_H__
10 #include <rte_common.h>
11 #include <rte_ethdev.h>
12 #include <rte_kvargs.h>
14 #include <rte_mempool.h>
15 #include <rte_string_fns.h>
18 #include "otx2_common.h"
20 #include "otx2_flow.h"
22 #include "otx2_mempool.h"
27 #define OTX2_ETH_DEV_PMD_VERSION "1.0"
29 /* Ethdev HWCAP and Fixup flags. Use from MSB bits to avoid conflict with dev */
31 /* Minimum CQ size should be 4K */
32 #define OTX2_FIXUP_F_MIN_4K_Q BIT_ULL(63)
33 #define otx2_ethdev_fixup_is_min_4k_q(dev) \
34 ((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)
35 /* Limit CQ being full */
36 #define OTX2_FIXUP_F_LIMIT_CQ_FULL BIT_ULL(62)
37 #define otx2_ethdev_fixup_is_limit_cq_full(dev) \
38 ((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)
40 /* Used for struct otx2_eth_dev::flags */
41 #define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
43 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
44 * In Tx space is always reserved for this in FRS.
46 #define NIX_MAX_VTAG_INS 2
47 #define NIX_MAX_VTAG_ACT_SIZE (4 * NIX_MAX_VTAG_INS)
49 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
50 #define NIX_L2_OVERHEAD \
51 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
53 /* HW config of frame size doesn't include FCS */
54 #define NIX_MAX_HW_FRS 9212
55 #define NIX_MIN_HW_FRS 60
57 /* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
59 (NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)
62 (NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
65 (NIX_MAX_FRS - NIX_L2_OVERHEAD)
67 #define NIX_MAX_SQB 512
68 #define NIX_MIN_SQB 32
69 #define NIX_SQB_LIST_SPACE 2
70 #define NIX_RSS_RETA_SIZE_MAX 256
71 /* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
72 #define NIX_RSS_GRPS 8
73 #define NIX_HASH_KEY_SIZE 48 /* 352 Bits */
74 #define NIX_RSS_RETA_SIZE 64
75 #define NIX_RX_MIN_DESC 16
76 #define NIX_RX_MIN_DESC_ALIGN 16
77 #define NIX_RX_NB_SEG_MAX 6
78 #define NIX_CQ_ENTRY_SZ 128
79 #define NIX_CQ_ALIGN 512
80 #define NIX_SQB_LOWER_THRESH 90
81 #define LMT_SLOT_MASK 0x7f
83 /* If PTP is enabled additional SEND MEM DESC is required which
84 * takes 2 words, hence max 7 iova address are possible
86 #if defined(RTE_LIBRTE_IEEE1588)
87 #define NIX_TX_NB_SEG_MAX 7
89 #define NIX_TX_NB_SEG_MAX 9
92 #define NIX_TX_MSEG_SG_DWORDS \
93 ((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3) \
96 /* Apply BP when CQ is 75% full */
97 #define NIX_CQ_BP_LEVEL (25 * 256 / 100)
99 #define CQ_OP_STAT_OP_ERR 63
100 #define CQ_OP_STAT_CQ_ERR 46
102 #define OP_ERR BIT_ULL(CQ_OP_STAT_OP_ERR)
103 #define CQ_ERR BIT_ULL(CQ_OP_STAT_CQ_ERR)
105 #define CQ_CQE_THRESH_DEFAULT 0x1ULL /* IRQ triggered when
106 * NIX_LF_CINTX_CNT[QCOUNT]
109 #define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
110 #define CQ_TIMER_THRESH_MAX 255
112 #define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
113 ETH_RSS_TCP | ETH_RSS_SCTP | \
114 ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD)
116 #define NIX_TX_OFFLOAD_CAPA ( \
117 DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
118 DEV_TX_OFFLOAD_MT_LOCKFREE | \
119 DEV_TX_OFFLOAD_VLAN_INSERT | \
120 DEV_TX_OFFLOAD_QINQ_INSERT | \
121 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
122 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
123 DEV_TX_OFFLOAD_TCP_CKSUM | \
124 DEV_TX_OFFLOAD_UDP_CKSUM | \
125 DEV_TX_OFFLOAD_SCTP_CKSUM | \
126 DEV_TX_OFFLOAD_MULTI_SEGS | \
127 DEV_TX_OFFLOAD_IPV4_CKSUM)
129 #define NIX_RX_OFFLOAD_CAPA ( \
130 DEV_RX_OFFLOAD_CHECKSUM | \
131 DEV_RX_OFFLOAD_SCTP_CKSUM | \
132 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
133 DEV_RX_OFFLOAD_SCATTER | \
134 DEV_RX_OFFLOAD_JUMBO_FRAME | \
135 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
136 DEV_RX_OFFLOAD_VLAN_STRIP | \
137 DEV_RX_OFFLOAD_VLAN_FILTER | \
138 DEV_RX_OFFLOAD_QINQ_STRIP | \
139 DEV_RX_OFFLOAD_TIMESTAMP)
141 #define NIX_DEFAULT_RSS_CTX_GROUP 0
142 #define NIX_DEFAULT_RSS_MCAM_IDX -1
144 #define otx2_ethdev_is_ptp_en(dev) ((dev)->ptp_en)
146 #define NIX_TIMESYNC_TX_CMD_LEN 8
147 /* Additional timesync values. */
148 #define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL
151 nix_q_size_16, /* 16 entries */
152 nix_q_size_64, /* 64 entries */
159 nix_q_size_1M, /* Million entries */
164 struct rte_eth_dev *eth_dev;
168 struct otx2_rss_info {
170 uint32_t flowkey_cfg;
173 uint8_t alg_idx; /* Selected algo index */
174 uint16_t ind_tbl[NIX_RSS_RETA_SIZE_MAX];
175 uint8_t key[NIX_HASH_KEY_SIZE];
178 struct otx2_eth_qconf {
180 struct rte_eth_txconf tx;
181 struct rte_eth_rxconf rx;
188 struct otx2_fc_info {
189 enum rte_eth_fc_mode mode; /**< Link flow control mode */
193 uint16_t bpid[NIX_MAX_CHAN];
196 struct vlan_mkex_info {
197 struct npc_xtract_info la_xtract;
198 struct npc_xtract_info lb_xtract;
199 uint64_t lb_lt_offset;
205 TAILQ_ENTRY(vlan_entry) next;
208 TAILQ_HEAD(otx2_vlan_filter_tbl, vlan_entry);
210 struct otx2_vlan_info {
211 struct otx2_vlan_filter_tbl fltr_tbl;
212 /* MKEX layer info */
213 struct mcam_entry def_tx_mcam_ent;
214 struct mcam_entry def_rx_mcam_ent;
215 struct vlan_mkex_info mkex;
216 /* Default mcam entry that matches vlan packets */
217 uint32_t def_rx_mcam_idx;
218 uint32_t def_tx_mcam_idx;
219 /* MCAM entry that matches double vlan packets */
220 uint32_t qinq_mcam_idx;
221 /* Indices of tx_vtag def registers */
222 uint32_t outer_vlan_idx;
223 uint32_t inner_vlan_idx;
224 uint16_t outer_vlan_tpid;
225 uint16_t inner_vlan_tpid;
227 /* QinQ entry allocated before default one */
228 uint8_t qinq_before_def;
229 uint8_t pvid_insert_on;
230 /* Rx vtag action type */
231 uint8_t vtag_type_idx;
238 struct otx2_eth_dev {
239 OTX2_DEV; /* Base class */
240 MARKER otx2_eth_dev_data_start;
242 uint16_t rx_chan_base;
243 uint16_t tx_chan_base;
246 uint8_t lso_tsov4_idx;
247 uint8_t lso_tsov6_idx;
248 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
249 uint8_t mkex_pfl_name[MKEX_NAME_LEN];
250 uint8_t max_mac_entries;
257 uint8_t configured_qints;
258 uint8_t configured_cints;
259 uint8_t configured_nb_rx_qs;
260 uint8_t configured_nb_tx_qs;
261 uint16_t nix_msixoff;
265 uint16_t max_sqb_count;
266 uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
267 uint64_t rx_offloads;
268 uint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */
269 uint64_t tx_offloads;
270 uint64_t rx_offload_capa;
271 uint64_t tx_offload_capa;
272 struct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];
273 struct otx2_qint cints_mem[RTE_MAX_QUEUES_PER_PORT];
274 uint16_t txschq[NIX_TXSCH_LVL_CNT];
275 uint16_t txschq_contig[NIX_TXSCH_LVL_CNT];
276 uint16_t txschq_index[NIX_TXSCH_LVL_CNT];
277 uint16_t txschq_contig_index[NIX_TXSCH_LVL_CNT];
278 /* Dis-contiguous queues */
279 uint16_t txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
280 /* Contiguous queues */
281 uint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
282 uint16_t otx2_tm_root_lvl;
284 uint16_t tm_leaf_cnt;
285 struct otx2_nix_tm_node_list node_list;
286 struct otx2_nix_tm_shaper_profile_list shaper_profile_list;
287 struct otx2_rss_info rss_info;
288 struct otx2_fc_info fc_info;
289 uint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
290 uint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
291 struct otx2_npc_flow_info npc_flow;
292 struct otx2_vlan_info vlan_info;
293 struct otx2_eth_qconf *tx_qconf;
294 struct otx2_eth_qconf *rx_qconf;
295 struct rte_eth_dev *eth_dev;
296 eth_rx_burst_t rx_pkt_burst_no_offload;
299 struct otx2_timesync_info tstamp;
300 struct rte_timecounter systime_tc;
301 struct rte_timecounter rx_tstamp_tc;
302 struct rte_timecounter tx_tstamp_tc;
303 } __rte_cache_aligned;
305 struct otx2_eth_txq {
307 int64_t fc_cache_pkts;
312 uint16_t sqes_per_sqb_log2;
313 int16_t nb_sqb_bufs_adj;
314 MARKER slow_path_start;
315 uint16_t nb_sqb_bufs;
318 struct otx2_eth_dev *dev;
319 struct rte_mempool *sqb_pool;
320 struct otx2_eth_qconf qconf;
321 } __rte_cache_aligned;
323 struct otx2_eth_rxq {
324 uint64_t mbuf_initializer;
335 struct otx2_timesync_info *tstamp;
336 MARKER slow_path_start;
340 struct rte_mempool *pool;
341 enum nix_q_size_e qsize;
342 struct rte_eth_dev *eth_dev;
343 struct otx2_eth_qconf qconf;
344 } __rte_cache_aligned;
346 static inline struct otx2_eth_dev *
347 otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
349 return eth_dev->data->dev_private;
353 void otx2_nix_info_get(struct rte_eth_dev *eth_dev,
354 struct rte_eth_dev_info *dev_info);
355 int otx2_nix_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
356 enum rte_filter_type filter_type,
357 enum rte_filter_op filter_op, void *arg);
358 int otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
360 int otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
361 struct rte_eth_dev_module_info *modinfo);
362 int otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
363 struct rte_dev_eeprom_info *info);
364 int otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
365 void otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
366 struct rte_eth_rxq_info *qinfo);
367 void otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
368 struct rte_eth_txq_info *qinfo);
369 uint32_t otx2_nix_rx_queue_count(struct rte_eth_dev *eth_dev, uint16_t qidx);
370 int otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
371 int otx2_nix_rx_descriptor_done(void *rxq, uint16_t offset);
372 int otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset);
374 void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en);
375 void otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);
376 void otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);
377 void otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
378 void otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
379 int otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx);
380 int otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx);
381 uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);
384 int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
385 int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);
388 void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
389 int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
390 void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
391 struct cgx_link_user_info *link);
392 int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);
393 int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);
396 int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
397 int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);
398 int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
399 void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
400 void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
401 void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
403 int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
404 uint16_t rx_queue_id);
405 int otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
406 uint16_t rx_queue_id);
409 int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);
410 int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
411 struct rte_dev_reg_info *regs);
412 int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
413 void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
416 int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
417 struct rte_eth_stats *stats);
418 void otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev);
420 int otx2_nix_queue_stats_mapping(struct rte_eth_dev *dev,
421 uint16_t queue_id, uint8_t stat_idx,
423 int otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,
424 struct rte_eth_xstat *xstats, unsigned int n);
425 int otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
426 struct rte_eth_xstat_name *xstats_names,
428 void otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev);
430 int otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev,
432 uint64_t *values, unsigned int n);
433 int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
434 struct rte_eth_xstat_name *xstats_names,
435 const uint64_t *ids, unsigned int limit);
438 void otx2_nix_rss_set_key(struct otx2_eth_dev *dev,
439 uint8_t *key, uint32_t key_len);
440 uint32_t otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev,
441 uint64_t ethdev_rss, uint8_t rss_level);
442 int otx2_rss_set_hf(struct otx2_eth_dev *dev,
443 uint32_t flowkey_cfg, uint8_t *alg_idx,
444 uint8_t group, int mcam_index);
445 int otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev, uint8_t group,
447 int otx2_nix_rss_config(struct rte_eth_dev *eth_dev);
449 int otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,
450 struct rte_eth_rss_reta_entry64 *reta_conf,
452 int otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,
453 struct rte_eth_rss_reta_entry64 *reta_conf,
455 int otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
456 struct rte_eth_rss_conf *rss_conf);
458 int otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
459 struct rte_eth_rss_conf *rss_conf);
462 int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
463 int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);
464 int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
465 struct rte_ether_addr *addr);
468 int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
469 struct rte_eth_fc_conf *fc_conf);
471 int otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
472 struct rte_eth_fc_conf *fc_conf);
474 int otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb);
476 int otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev);
479 int otx2_nix_vlan_offload_init(struct rte_eth_dev *eth_dev);
480 int otx2_nix_vlan_fini(struct rte_eth_dev *eth_dev);
481 int otx2_nix_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);
482 void otx2_nix_vlan_update_promisc(struct rte_eth_dev *eth_dev, int enable);
483 int otx2_nix_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
485 void otx2_nix_vlan_strip_queue_set(struct rte_eth_dev *dev,
486 uint16_t queue, int on);
487 int otx2_nix_vlan_tpid_set(struct rte_eth_dev *eth_dev,
488 enum rte_vlan_type type, uint16_t tpid);
489 int otx2_nix_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
491 /* Lookup configuration */
492 void *otx2_nix_fastpath_lookup_mem_get(void);
495 const uint32_t *otx2_nix_supported_ptypes_get(struct rte_eth_dev *dev);
497 /* Mac address handling */
498 int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
499 struct rte_ether_addr *addr);
500 int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
501 int otx2_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
502 struct rte_ether_addr *addr,
503 uint32_t index, uint32_t pool);
504 void otx2_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
505 int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
508 int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
509 struct otx2_eth_dev *dev);
511 /* Rx and Tx routines */
512 void otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev);
513 void otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev);
514 void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);
516 /* Timesync - PTP routines */
517 int otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev);
518 int otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev);
519 int otx2_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
520 struct timespec *timestamp,
522 int otx2_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
523 struct timespec *timestamp);
524 int otx2_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
525 int otx2_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
526 const struct timespec *ts);
527 int otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
528 struct timespec *ts);
529 int otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en);
531 #endif /* __OTX2_ETHDEV_H__ */