1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_ETHDEV_H__
6 #define __OTX2_ETHDEV_H__
11 #include <rte_common.h>
12 #include <rte_ethdev.h>
13 #include <rte_kvargs.h>
15 #include <rte_mempool.h>
16 #include <rte_string_fns.h>
19 #include "otx2_common.h"
21 #include "otx2_flow.h"
23 #include "otx2_mempool.h"
28 #define OTX2_ETH_DEV_PMD_VERSION "1.0"
30 /* Ethdev HWCAP and Fixup flags. Use from MSB bits to avoid conflict with dev */
32 /* Minimum CQ size should be 4K */
33 #define OTX2_FIXUP_F_MIN_4K_Q BIT_ULL(63)
34 #define otx2_ethdev_fixup_is_min_4k_q(dev) \
35 ((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)
36 /* Limit CQ being full */
37 #define OTX2_FIXUP_F_LIMIT_CQ_FULL BIT_ULL(62)
38 #define otx2_ethdev_fixup_is_limit_cq_full(dev) \
39 ((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)
41 /* Used for struct otx2_eth_dev::flags */
42 #define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
44 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
45 * In Tx space is always reserved for this in FRS.
47 #define NIX_MAX_VTAG_INS 2
48 #define NIX_MAX_VTAG_ACT_SIZE (4 * NIX_MAX_VTAG_INS)
50 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
51 #define NIX_L2_OVERHEAD \
52 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
54 /* HW config of frame size doesn't include FCS */
55 #define NIX_MAX_HW_FRS 9212
56 #define NIX_MIN_HW_FRS 60
58 /* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
60 (NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)
63 (NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
66 (NIX_MAX_FRS - NIX_L2_OVERHEAD)
68 #define NIX_MAX_SQB 512
69 #define NIX_DEF_SQB 16
71 #define NIX_SQB_LIST_SPACE 2
72 #define NIX_RSS_RETA_SIZE_MAX 256
73 /* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
74 #define NIX_RSS_GRPS 8
75 #define NIX_HASH_KEY_SIZE 48 /* 352 Bits */
76 #define NIX_RSS_RETA_SIZE 64
77 #define NIX_RX_MIN_DESC 16
78 #define NIX_RX_MIN_DESC_ALIGN 16
79 #define NIX_RX_NB_SEG_MAX 6
80 #define NIX_CQ_ENTRY_SZ 128
81 #define NIX_CQ_ALIGN 512
82 #define NIX_SQB_LOWER_THRESH 70
83 #define LMT_SLOT_MASK 0x7f
84 #define NIX_RX_DEFAULT_RING_SZ 4096
86 /* If PTP is enabled additional SEND MEM DESC is required which
87 * takes 2 words, hence max 7 iova address are possible
89 #if defined(RTE_LIBRTE_IEEE1588)
90 #define NIX_TX_NB_SEG_MAX 7
92 #define NIX_TX_NB_SEG_MAX 9
95 #define NIX_TX_MSEG_SG_DWORDS \
96 ((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3) \
99 /* Apply BP/DROP when CQ is 95% full */
100 #define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)
101 #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
103 #define CQ_OP_STAT_OP_ERR 63
104 #define CQ_OP_STAT_CQ_ERR 46
106 #define OP_ERR BIT_ULL(CQ_OP_STAT_OP_ERR)
107 #define CQ_ERR BIT_ULL(CQ_OP_STAT_CQ_ERR)
109 #define CQ_CQE_THRESH_DEFAULT 0x1ULL /* IRQ triggered when
110 * NIX_LF_CINTX_CNT[QCOUNT]
113 #define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
114 #define CQ_TIMER_THRESH_MAX 255
116 #define NIX_RSS_L3_L4_SRC_DST (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY \
117 | ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY)
119 #define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
120 ETH_RSS_TCP | ETH_RSS_SCTP | \
121 ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
122 NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK)
124 #define NIX_TX_OFFLOAD_CAPA ( \
125 DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
126 DEV_TX_OFFLOAD_MT_LOCKFREE | \
127 DEV_TX_OFFLOAD_VLAN_INSERT | \
128 DEV_TX_OFFLOAD_QINQ_INSERT | \
129 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
130 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
131 DEV_TX_OFFLOAD_TCP_CKSUM | \
132 DEV_TX_OFFLOAD_UDP_CKSUM | \
133 DEV_TX_OFFLOAD_SCTP_CKSUM | \
134 DEV_TX_OFFLOAD_TCP_TSO | \
135 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
136 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
137 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
138 DEV_TX_OFFLOAD_MULTI_SEGS | \
139 DEV_TX_OFFLOAD_IPV4_CKSUM)
141 #define NIX_RX_OFFLOAD_CAPA ( \
142 DEV_RX_OFFLOAD_CHECKSUM | \
143 DEV_RX_OFFLOAD_SCTP_CKSUM | \
144 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
145 DEV_RX_OFFLOAD_SCATTER | \
146 DEV_RX_OFFLOAD_JUMBO_FRAME | \
147 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
148 DEV_RX_OFFLOAD_VLAN_STRIP | \
149 DEV_RX_OFFLOAD_VLAN_FILTER | \
150 DEV_RX_OFFLOAD_QINQ_STRIP | \
151 DEV_RX_OFFLOAD_TIMESTAMP | \
152 DEV_RX_OFFLOAD_RSS_HASH)
154 #define NIX_DEFAULT_RSS_CTX_GROUP 0
155 #define NIX_DEFAULT_RSS_MCAM_IDX -1
157 #define otx2_ethdev_is_ptp_en(dev) ((dev)->ptp_en)
159 #define NIX_TIMESYNC_TX_CMD_LEN 8
160 /* Additional timesync values. */
161 #define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL
164 nix_q_size_16, /* 16 entries */
165 nix_q_size_64, /* 64 entries */
172 nix_q_size_1M, /* Million entries */
177 struct rte_eth_dev *eth_dev;
181 struct otx2_rss_info {
183 uint32_t flowkey_cfg;
186 uint8_t alg_idx; /* Selected algo index */
187 uint16_t ind_tbl[NIX_RSS_RETA_SIZE_MAX];
188 uint8_t key[NIX_HASH_KEY_SIZE];
191 struct otx2_eth_qconf {
193 struct rte_eth_txconf tx;
194 struct rte_eth_rxconf rx;
202 struct otx2_fc_info {
203 enum rte_eth_fc_mode mode; /**< Link flow control mode */
207 uint16_t bpid[NIX_MAX_CHAN];
210 struct vlan_mkex_info {
211 struct npc_xtract_info la_xtract;
212 struct npc_xtract_info lb_xtract;
213 uint64_t lb_lt_offset;
217 struct rte_ether_addr mcast_mac;
219 TAILQ_ENTRY(mcast_entry) next;
222 TAILQ_HEAD(otx2_nix_mc_filter_tbl, mcast_entry);
227 TAILQ_ENTRY(vlan_entry) next;
230 TAILQ_HEAD(otx2_vlan_filter_tbl, vlan_entry);
232 struct otx2_vlan_info {
233 struct otx2_vlan_filter_tbl fltr_tbl;
234 /* MKEX layer info */
235 struct mcam_entry def_tx_mcam_ent;
236 struct mcam_entry def_rx_mcam_ent;
237 struct vlan_mkex_info mkex;
238 /* Default mcam entry that matches vlan packets */
239 uint32_t def_rx_mcam_idx;
240 uint32_t def_tx_mcam_idx;
241 /* MCAM entry that matches double vlan packets */
242 uint32_t qinq_mcam_idx;
243 /* Indices of tx_vtag def registers */
244 uint32_t outer_vlan_idx;
245 uint32_t inner_vlan_idx;
246 uint16_t outer_vlan_tpid;
247 uint16_t inner_vlan_tpid;
249 /* QinQ entry allocated before default one */
250 uint8_t qinq_before_def;
251 uint8_t pvid_insert_on;
252 /* Rx vtag action type */
253 uint8_t vtag_type_idx;
260 struct otx2_eth_dev {
261 OTX2_DEV; /* Base class */
262 RTE_MARKER otx2_eth_dev_data_start;
264 uint16_t rx_chan_base;
265 uint16_t tx_chan_base;
268 uint8_t lso_tsov4_idx;
269 uint8_t lso_tsov6_idx;
270 uint8_t lso_base_idx;
271 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
272 uint8_t mkex_pfl_name[MKEX_NAME_LEN];
273 uint8_t max_mac_entries;
274 bool dmac_filter_enable;
283 uint8_t configured_qints;
284 uint8_t configured_cints;
285 uint8_t configured_nb_rx_qs;
286 uint8_t configured_nb_tx_qs;
287 uint8_t ptype_disable;
288 uint16_t nix_msixoff;
292 uint16_t rss_tag_as_xor;
293 uint16_t max_sqb_count;
294 uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
295 uint64_t rx_offloads;
296 uint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */
297 uint64_t tx_offloads;
298 uint64_t rx_offload_capa;
299 uint64_t tx_offload_capa;
300 struct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];
301 struct otx2_qint cints_mem[RTE_MAX_QUEUES_PER_PORT];
302 uint16_t txschq[NIX_TXSCH_LVL_CNT];
303 uint16_t txschq_contig[NIX_TXSCH_LVL_CNT];
304 uint16_t txschq_index[NIX_TXSCH_LVL_CNT];
305 uint16_t txschq_contig_index[NIX_TXSCH_LVL_CNT];
306 /* Dis-contiguous queues */
307 uint16_t txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
308 /* Contiguous queues */
309 uint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
310 uint16_t otx2_tm_root_lvl;
311 uint16_t link_cfg_lvl;
313 uint16_t tm_leaf_cnt;
314 uint64_t tm_rate_min;
315 struct otx2_nix_tm_node_list node_list;
316 struct otx2_nix_tm_shaper_profile_list shaper_profile_list;
317 struct otx2_rss_info rss_info;
318 struct otx2_fc_info fc_info;
319 uint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
320 uint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
321 struct otx2_npc_flow_info npc_flow;
322 struct otx2_vlan_info vlan_info;
323 struct otx2_eth_qconf *tx_qconf;
324 struct otx2_eth_qconf *rx_qconf;
325 struct rte_eth_dev *eth_dev;
326 eth_rx_burst_t rx_pkt_burst_no_offload;
329 struct otx2_timesync_info tstamp;
330 struct rte_timecounter systime_tc;
331 struct rte_timecounter rx_tstamp_tc;
332 struct rte_timecounter tx_tstamp_tc;
333 double clk_freq_mult;
336 struct otx2_nix_mc_filter_tbl mc_fltr_tbl;
337 bool sdp_link; /* SDP flag */
338 /* Inline IPsec params */
339 uint16_t ipsec_in_max_spi;
342 } __rte_cache_aligned;
344 struct otx2_eth_txq {
346 int64_t fc_cache_pkts;
351 uint16_t sqes_per_sqb_log2;
352 int16_t nb_sqb_bufs_adj;
353 RTE_MARKER slow_path_start;
354 uint16_t nb_sqb_bufs;
357 struct otx2_eth_dev *dev;
358 struct rte_mempool *sqb_pool;
359 struct otx2_eth_qconf qconf;
360 } __rte_cache_aligned;
362 struct otx2_eth_rxq {
363 uint64_t mbuf_initializer;
374 struct otx2_timesync_info *tstamp;
375 RTE_MARKER slow_path_start;
379 struct rte_mempool *pool;
380 enum nix_q_size_e qsize;
381 struct rte_eth_dev *eth_dev;
382 struct otx2_eth_qconf qconf;
384 } __rte_cache_aligned;
386 static inline struct otx2_eth_dev *
387 otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
389 return eth_dev->data->dev_private;
393 int otx2_nix_info_get(struct rte_eth_dev *eth_dev,
394 struct rte_eth_dev_info *dev_info);
395 int otx2_nix_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
396 enum rte_filter_type filter_type,
397 enum rte_filter_op filter_op, void *arg);
398 int otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
400 int otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
401 struct rte_eth_dev_module_info *modinfo);
402 int otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
403 struct rte_dev_eeprom_info *info);
404 int otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
405 void otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
406 struct rte_eth_rxq_info *qinfo);
407 void otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
408 struct rte_eth_txq_info *qinfo);
409 int otx2_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
410 struct rte_eth_burst_mode *mode);
411 int otx2_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
412 struct rte_eth_burst_mode *mode);
413 uint32_t otx2_nix_rx_queue_count(struct rte_eth_dev *eth_dev, uint16_t qidx);
414 int otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
415 int otx2_nix_rx_descriptor_done(void *rxq, uint16_t offset);
416 int otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset);
417 int otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset);
419 void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en);
420 int otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);
421 int otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);
422 int otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
423 int otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
424 int otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx);
425 int otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx);
426 uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);
428 /* Multicast filter APIs */
429 void otx2_nix_mc_filter_init(struct otx2_eth_dev *dev);
430 void otx2_nix_mc_filter_fini(struct otx2_eth_dev *dev);
431 int otx2_nix_mc_addr_list_install(struct rte_eth_dev *eth_dev);
432 int otx2_nix_mc_addr_list_uninstall(struct rte_eth_dev *eth_dev);
433 int otx2_nix_set_mc_addr_list(struct rte_eth_dev *eth_dev,
434 struct rte_ether_addr *mc_addr_set,
435 uint32_t nb_mc_addr);
438 int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
439 int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);
442 void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
443 int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
444 void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
445 struct cgx_link_user_info *link);
446 int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);
447 int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);
448 int otx2_apply_link_speed(struct rte_eth_dev *eth_dev);
451 int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
452 int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);
453 int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
454 void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
455 void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
456 void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
457 void otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
458 void otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
460 int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
461 uint16_t rx_queue_id);
462 int otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
463 uint16_t rx_queue_id);
466 int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);
467 int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
468 struct rte_dev_reg_info *regs);
469 int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
470 void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
471 void otx2_nix_tm_dump(struct otx2_eth_dev *dev);
474 int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
475 struct rte_eth_stats *stats);
476 int otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev);
478 int otx2_nix_queue_stats_mapping(struct rte_eth_dev *dev,
479 uint16_t queue_id, uint8_t stat_idx,
481 int otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,
482 struct rte_eth_xstat *xstats, unsigned int n);
483 int otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
484 struct rte_eth_xstat_name *xstats_names,
486 int otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev);
488 int otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev,
490 uint64_t *values, unsigned int n);
491 int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
492 struct rte_eth_xstat_name *xstats_names,
493 const uint64_t *ids, unsigned int limit);
496 void otx2_nix_rss_set_key(struct otx2_eth_dev *dev,
497 uint8_t *key, uint32_t key_len);
498 uint32_t otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev,
499 uint64_t ethdev_rss, uint8_t rss_level);
500 int otx2_rss_set_hf(struct otx2_eth_dev *dev,
501 uint32_t flowkey_cfg, uint8_t *alg_idx,
502 uint8_t group, int mcam_index);
503 int otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev, uint8_t group,
505 int otx2_nix_rss_config(struct rte_eth_dev *eth_dev);
507 int otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,
508 struct rte_eth_rss_reta_entry64 *reta_conf,
510 int otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,
511 struct rte_eth_rss_reta_entry64 *reta_conf,
513 int otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
514 struct rte_eth_rss_conf *rss_conf);
516 int otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
517 struct rte_eth_rss_conf *rss_conf);
520 int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
521 int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);
522 int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
523 struct rte_ether_addr *addr);
526 int otx2_nix_flow_ctrl_init(struct rte_eth_dev *eth_dev);
528 int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
529 struct rte_eth_fc_conf *fc_conf);
531 int otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
532 struct rte_eth_fc_conf *fc_conf);
534 int otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb);
536 int otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev);
539 int otx2_nix_vlan_offload_init(struct rte_eth_dev *eth_dev);
540 int otx2_nix_vlan_fini(struct rte_eth_dev *eth_dev);
541 int otx2_nix_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);
542 void otx2_nix_vlan_update_promisc(struct rte_eth_dev *eth_dev, int enable);
543 int otx2_nix_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
545 void otx2_nix_vlan_strip_queue_set(struct rte_eth_dev *dev,
546 uint16_t queue, int on);
547 int otx2_nix_vlan_tpid_set(struct rte_eth_dev *eth_dev,
548 enum rte_vlan_type type, uint16_t tpid);
549 int otx2_nix_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
551 /* Lookup configuration */
552 void *otx2_nix_fastpath_lookup_mem_get(void);
555 const uint32_t *otx2_nix_supported_ptypes_get(struct rte_eth_dev *dev);
556 int otx2_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask);
558 /* Mac address handling */
559 int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
560 struct rte_ether_addr *addr);
561 int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
562 int otx2_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
563 struct rte_ether_addr *addr,
564 uint32_t index, uint32_t pool);
565 void otx2_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
566 int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
569 int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
570 struct otx2_eth_dev *dev);
572 /* Rx and Tx routines */
573 void otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev);
574 void otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev);
575 void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);
577 /* Timesync - PTP routines */
578 int otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev);
579 int otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev);
580 int otx2_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
581 struct timespec *timestamp,
583 int otx2_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
584 struct timespec *timestamp);
585 int otx2_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
586 int otx2_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
587 const struct timespec *ts);
588 int otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
589 struct timespec *ts);
590 int otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en);
591 int otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *time);
592 int otx2_nix_raw_clock_tsc_conv(struct otx2_eth_dev *dev);
593 void otx2_nix_ptp_enable_vf(struct rte_eth_dev *eth_dev);
595 #endif /* __OTX2_ETHDEV_H__ */