1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_ETHDEV_H__
6 #define __OTX2_ETHDEV_H__
11 #include <rte_common.h>
12 #include <rte_ethdev.h>
13 #include <rte_kvargs.h>
15 #include <rte_mempool.h>
16 #include <rte_security_driver.h>
17 #include <rte_spinlock.h>
18 #include <rte_string_fns.h>
21 #include "otx2_common.h"
23 #include "otx2_flow.h"
25 #include "otx2_mempool.h"
30 #define OTX2_ETH_DEV_PMD_VERSION "1.0"
32 /* Ethdev HWCAP and Fixup flags. Use from MSB bits to avoid conflict with dev */
34 /* Minimum CQ size should be 4K */
35 #define OTX2_FIXUP_F_MIN_4K_Q BIT_ULL(63)
36 #define otx2_ethdev_fixup_is_min_4k_q(dev) \
37 ((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)
38 /* Limit CQ being full */
39 #define OTX2_FIXUP_F_LIMIT_CQ_FULL BIT_ULL(62)
40 #define otx2_ethdev_fixup_is_limit_cq_full(dev) \
41 ((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)
43 /* Used for struct otx2_eth_dev::flags */
44 #define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
46 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
47 * In Tx space is always reserved for this in FRS.
49 #define NIX_MAX_VTAG_INS 2
50 #define NIX_MAX_VTAG_ACT_SIZE (4 * NIX_MAX_VTAG_INS)
52 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
53 #define NIX_L2_OVERHEAD \
54 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
55 #define NIX_L2_MAX_LEN \
56 (RTE_ETHER_MTU + NIX_L2_OVERHEAD)
58 /* HW config of frame size doesn't include FCS */
59 #define NIX_MAX_HW_FRS 9212
60 #define NIX_MIN_HW_FRS 60
62 /* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
64 (NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)
67 (NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
70 (NIX_MAX_FRS - NIX_L2_OVERHEAD)
72 #define NIX_MAX_SQB 512
73 #define NIX_DEF_SQB 16
75 #define NIX_SQB_LIST_SPACE 2
76 #define NIX_RSS_RETA_SIZE_MAX 256
77 /* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
78 #define NIX_RSS_GRPS 8
79 #define NIX_HASH_KEY_SIZE 48 /* 352 Bits */
80 #define NIX_RSS_RETA_SIZE 64
81 #define NIX_RX_MIN_DESC 16
82 #define NIX_RX_MIN_DESC_ALIGN 16
83 #define NIX_RX_NB_SEG_MAX 6
84 #define NIX_CQ_ENTRY_SZ 128
85 #define NIX_CQ_ALIGN 512
86 #define NIX_SQB_LOWER_THRESH 70
87 #define LMT_SLOT_MASK 0x7f
88 #define NIX_RX_DEFAULT_RING_SZ 4096
90 /* If PTP is enabled additional SEND MEM DESC is required which
91 * takes 2 words, hence max 7 iova address are possible
93 #if defined(RTE_LIBRTE_IEEE1588)
94 #define NIX_TX_NB_SEG_MAX 7
96 #define NIX_TX_NB_SEG_MAX 9
99 #define NIX_TX_MSEG_SG_DWORDS \
100 ((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3) \
103 /* Apply BP/DROP when CQ is 95% full */
104 #define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)
105 #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
107 #define CQ_OP_STAT_OP_ERR 63
108 #define CQ_OP_STAT_CQ_ERR 46
110 #define OP_ERR BIT_ULL(CQ_OP_STAT_OP_ERR)
111 #define CQ_ERR BIT_ULL(CQ_OP_STAT_CQ_ERR)
113 #define CQ_CQE_THRESH_DEFAULT 0x1ULL /* IRQ triggered when
114 * NIX_LF_CINTX_CNT[QCOUNT]
117 #define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
118 #define CQ_TIMER_THRESH_MAX 255
120 #define NIX_RSS_L3_L4_SRC_DST (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY \
121 | RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)
123 #define NIX_RSS_OFFLOAD (RTE_ETH_RSS_PORT | RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP |\
124 RTE_ETH_RSS_TCP | RTE_ETH_RSS_SCTP | \
125 RTE_ETH_RSS_TUNNEL | RTE_ETH_RSS_L2_PAYLOAD | \
126 NIX_RSS_L3_L4_SRC_DST | RTE_ETH_RSS_LEVEL_MASK | \
129 #define NIX_TX_OFFLOAD_CAPA ( \
130 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE | \
131 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | \
132 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | \
133 RTE_ETH_TX_OFFLOAD_QINQ_INSERT | \
134 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
135 RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | \
136 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | \
137 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \
138 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | \
139 RTE_ETH_TX_OFFLOAD_TCP_TSO | \
140 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | \
141 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | \
142 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO | \
143 RTE_ETH_TX_OFFLOAD_MULTI_SEGS | \
144 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)
146 #define NIX_RX_OFFLOAD_CAPA ( \
147 RTE_ETH_RX_OFFLOAD_CHECKSUM | \
148 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | \
149 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
150 RTE_ETH_RX_OFFLOAD_SCATTER | \
151 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | \
152 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | \
153 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | \
154 RTE_ETH_RX_OFFLOAD_QINQ_STRIP | \
155 RTE_ETH_RX_OFFLOAD_TIMESTAMP | \
156 RTE_ETH_RX_OFFLOAD_RSS_HASH)
158 #define NIX_DEFAULT_RSS_CTX_GROUP 0
159 #define NIX_DEFAULT_RSS_MCAM_IDX -1
161 #define otx2_ethdev_is_ptp_en(dev) ((dev)->ptp_en)
163 #define NIX_TIMESYNC_TX_CMD_LEN 8
164 /* Additional timesync values. */
165 #define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL
167 #define OCTEONTX2_PMD net_octeontx2
169 #define otx2_ethdev_is_same_driver(dev) \
170 (strcmp((dev)->device->driver->name, RTE_STR(OCTEONTX2_PMD)) == 0)
173 nix_q_size_16, /* 16 entries */
174 nix_q_size_64, /* 64 entries */
181 nix_q_size_1M, /* Million entries */
185 enum nix_lso_tun_type {
194 struct rte_eth_dev *eth_dev;
198 struct otx2_rss_info {
200 uint32_t flowkey_cfg;
203 uint8_t alg_idx; /* Selected algo index */
204 uint16_t ind_tbl[NIX_RSS_RETA_SIZE_MAX];
205 uint8_t key[NIX_HASH_KEY_SIZE];
208 struct otx2_eth_qconf {
210 struct rte_eth_txconf tx;
211 struct rte_eth_rxconf rx;
219 struct otx2_fc_info {
220 enum rte_eth_fc_mode mode; /**< Link flow control mode */
224 uint16_t bpid[NIX_MAX_CHAN];
227 struct vlan_mkex_info {
228 struct npc_xtract_info la_xtract;
229 struct npc_xtract_info lb_xtract;
230 uint64_t lb_lt_offset;
234 struct rte_ether_addr mcast_mac;
236 TAILQ_ENTRY(mcast_entry) next;
239 TAILQ_HEAD(otx2_nix_mc_filter_tbl, mcast_entry);
244 TAILQ_ENTRY(vlan_entry) next;
247 TAILQ_HEAD(otx2_vlan_filter_tbl, vlan_entry);
249 struct otx2_vlan_info {
250 struct otx2_vlan_filter_tbl fltr_tbl;
251 /* MKEX layer info */
252 struct mcam_entry def_tx_mcam_ent;
253 struct mcam_entry def_rx_mcam_ent;
254 struct vlan_mkex_info mkex;
255 /* Default mcam entry that matches vlan packets */
256 uint32_t def_rx_mcam_idx;
257 uint32_t def_tx_mcam_idx;
258 /* MCAM entry that matches double vlan packets */
259 uint32_t qinq_mcam_idx;
260 /* Indices of tx_vtag def registers */
261 uint32_t outer_vlan_idx;
262 uint32_t inner_vlan_idx;
263 uint16_t outer_vlan_tpid;
264 uint16_t inner_vlan_tpid;
266 /* QinQ entry allocated before default one */
267 uint8_t qinq_before_def;
268 uint8_t pvid_insert_on;
269 /* Rx vtag action type */
270 uint8_t vtag_type_idx;
277 struct otx2_eth_dev {
278 OTX2_DEV; /* Base class */
279 RTE_MARKER otx2_eth_dev_data_start;
281 uint16_t rx_chan_base;
282 uint16_t tx_chan_base;
285 uint8_t lso_tsov4_idx;
286 uint8_t lso_tsov6_idx;
287 uint8_t lso_udp_tun_idx[NIX_LSO_TUN_MAX];
288 uint8_t lso_tun_idx[NIX_LSO_TUN_MAX];
289 uint64_t lso_tun_fmt;
290 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
291 uint8_t mkex_pfl_name[MKEX_NAME_LEN];
292 uint8_t max_mac_entries;
293 bool dmac_filter_enable;
302 uint8_t configured_qints;
303 uint8_t configured_cints;
304 uint8_t configured_nb_rx_qs;
305 uint8_t configured_nb_tx_qs;
306 uint8_t ptype_disable;
307 uint16_t nix_msixoff;
311 uint16_t rss_tag_as_xor;
312 uint16_t max_sqb_count;
313 uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
314 uint64_t rx_offloads;
315 uint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */
316 uint64_t tx_offloads;
317 uint64_t rx_offload_capa;
318 uint64_t tx_offload_capa;
319 struct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];
320 struct otx2_qint cints_mem[RTE_MAX_QUEUES_PER_PORT];
321 uint16_t txschq[NIX_TXSCH_LVL_CNT];
322 uint16_t txschq_contig[NIX_TXSCH_LVL_CNT];
323 uint16_t txschq_index[NIX_TXSCH_LVL_CNT];
324 uint16_t txschq_contig_index[NIX_TXSCH_LVL_CNT];
325 /* Dis-contiguous queues */
326 uint16_t txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
327 /* Contiguous queues */
328 uint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
329 uint16_t otx2_tm_root_lvl;
330 uint16_t link_cfg_lvl;
332 uint16_t tm_leaf_cnt;
333 uint64_t tm_rate_min;
334 struct otx2_nix_tm_node_list node_list;
335 struct otx2_nix_tm_shaper_profile_list shaper_profile_list;
336 struct otx2_rss_info rss_info;
337 struct otx2_fc_info fc_info;
338 uint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
339 uint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
340 struct otx2_npc_flow_info npc_flow;
341 struct otx2_vlan_info vlan_info;
342 struct otx2_eth_qconf *tx_qconf;
343 struct otx2_eth_qconf *rx_qconf;
344 struct rte_eth_dev *eth_dev;
345 eth_rx_burst_t rx_pkt_burst_no_offload;
348 struct otx2_timesync_info tstamp;
349 struct rte_timecounter systime_tc;
350 struct rte_timecounter rx_tstamp_tc;
351 struct rte_timecounter tx_tstamp_tc;
352 double clk_freq_mult;
355 struct otx2_nix_mc_filter_tbl mc_fltr_tbl;
356 bool sdp_link; /* SDP flag */
357 /* Inline IPsec params */
358 uint16_t ipsec_in_max_spi;
359 rte_spinlock_t ipsec_tbl_lock;
362 } __rte_cache_aligned;
364 struct otx2_eth_txq {
366 int64_t fc_cache_pkts;
371 uint16_t sqes_per_sqb_log2;
372 int16_t nb_sqb_bufs_adj;
373 uint64_t lso_tun_fmt;
374 RTE_MARKER slow_path_start;
375 uint16_t nb_sqb_bufs;
378 struct otx2_eth_dev *dev;
379 struct rte_mempool *sqb_pool;
380 struct otx2_eth_qconf qconf;
381 } __rte_cache_aligned;
383 struct otx2_eth_rxq {
384 uint64_t mbuf_initializer;
395 struct otx2_timesync_info *tstamp;
396 RTE_MARKER slow_path_start;
400 struct rte_mempool *pool;
401 enum nix_q_size_e qsize;
402 struct rte_eth_dev *eth_dev;
403 struct otx2_eth_qconf qconf;
405 } __rte_cache_aligned;
407 static inline struct otx2_eth_dev *
408 otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
410 return eth_dev->data->dev_private;
414 int otx2_nix_info_get(struct rte_eth_dev *eth_dev,
415 struct rte_eth_dev_info *dev_info);
416 int otx2_nix_dev_flow_ops_get(struct rte_eth_dev *eth_dev,
417 const struct rte_flow_ops **ops);
418 int otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
420 int otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
421 struct rte_eth_dev_module_info *modinfo);
422 int otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
423 struct rte_dev_eeprom_info *info);
424 int otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
425 void otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
426 struct rte_eth_rxq_info *qinfo);
427 void otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
428 struct rte_eth_txq_info *qinfo);
429 int otx2_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
430 struct rte_eth_burst_mode *mode);
431 int otx2_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
432 struct rte_eth_burst_mode *mode);
433 uint32_t otx2_nix_rx_queue_count(void *rx_queue);
434 int otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
435 int otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset);
436 int otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset);
438 void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en);
439 int otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);
440 int otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);
441 int otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
442 int otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
443 int otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx);
444 int otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx);
445 uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);
447 /* Multicast filter APIs */
448 void otx2_nix_mc_filter_init(struct otx2_eth_dev *dev);
449 void otx2_nix_mc_filter_fini(struct otx2_eth_dev *dev);
450 int otx2_nix_mc_addr_list_install(struct rte_eth_dev *eth_dev);
451 int otx2_nix_mc_addr_list_uninstall(struct rte_eth_dev *eth_dev);
452 int otx2_nix_set_mc_addr_list(struct rte_eth_dev *eth_dev,
453 struct rte_ether_addr *mc_addr_set,
454 uint32_t nb_mc_addr);
457 int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
458 int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);
459 void otx2_nix_enable_mseg_on_jumbo(struct otx2_eth_rxq *rxq);
463 void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
464 int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
465 void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
466 struct cgx_link_user_info *link);
467 void otx2_eth_dev_link_status_get(struct otx2_dev *dev,
468 struct cgx_link_user_info *link);
469 int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);
470 int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);
471 int otx2_apply_link_speed(struct rte_eth_dev *eth_dev);
474 int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
475 int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);
476 int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
477 void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
478 void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
479 void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
480 void otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
481 void otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
483 int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
484 uint16_t rx_queue_id);
485 int otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
486 uint16_t rx_queue_id);
489 int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);
490 int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
491 struct rte_dev_reg_info *regs);
492 int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
493 void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
494 void otx2_nix_tm_dump(struct otx2_eth_dev *dev);
497 int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
498 struct rte_eth_stats *stats);
499 int otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev);
501 int otx2_nix_queue_stats_mapping(struct rte_eth_dev *dev,
502 uint16_t queue_id, uint8_t stat_idx,
504 int otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,
505 struct rte_eth_xstat *xstats, unsigned int n);
506 int otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
507 struct rte_eth_xstat_name *xstats_names,
509 int otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev);
511 int otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev,
513 uint64_t *values, unsigned int n);
514 int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
516 struct rte_eth_xstat_name *xstats_names,
520 void otx2_nix_rss_set_key(struct otx2_eth_dev *dev,
521 uint8_t *key, uint32_t key_len);
522 uint32_t otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev,
523 uint64_t ethdev_rss, uint8_t rss_level);
524 int otx2_rss_set_hf(struct otx2_eth_dev *dev,
525 uint32_t flowkey_cfg, uint8_t *alg_idx,
526 uint8_t group, int mcam_index);
527 int otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev, uint8_t group,
529 int otx2_nix_rss_config(struct rte_eth_dev *eth_dev);
531 int otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,
532 struct rte_eth_rss_reta_entry64 *reta_conf,
534 int otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,
535 struct rte_eth_rss_reta_entry64 *reta_conf,
537 int otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
538 struct rte_eth_rss_conf *rss_conf);
540 int otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
541 struct rte_eth_rss_conf *rss_conf);
544 int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
545 int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);
546 int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
547 struct rte_ether_addr *addr);
550 int otx2_nix_flow_ctrl_init(struct rte_eth_dev *eth_dev);
552 int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
553 struct rte_eth_fc_conf *fc_conf);
555 int otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
556 struct rte_eth_fc_conf *fc_conf);
558 int otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb);
560 int otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev);
563 int otx2_nix_vlan_offload_init(struct rte_eth_dev *eth_dev);
564 int otx2_nix_vlan_fini(struct rte_eth_dev *eth_dev);
565 int otx2_nix_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);
566 void otx2_nix_vlan_update_promisc(struct rte_eth_dev *eth_dev, int enable);
567 int otx2_nix_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
569 void otx2_nix_vlan_strip_queue_set(struct rte_eth_dev *dev,
570 uint16_t queue, int on);
571 int otx2_nix_vlan_tpid_set(struct rte_eth_dev *eth_dev,
572 enum rte_vlan_type type, uint16_t tpid);
573 int otx2_nix_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
575 /* Lookup configuration */
576 void *otx2_nix_fastpath_lookup_mem_get(void);
579 const uint32_t *otx2_nix_supported_ptypes_get(struct rte_eth_dev *dev);
580 int otx2_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask);
582 /* Mac address handling */
583 int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
584 struct rte_ether_addr *addr);
585 int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
586 int otx2_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
587 struct rte_ether_addr *addr,
588 uint32_t index, uint32_t pool);
589 void otx2_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
590 int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
593 int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
594 struct otx2_eth_dev *dev);
596 /* Rx and Tx routines */
597 void otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev);
598 void otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev);
599 void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);
601 /* Timesync - PTP routines */
602 int otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev);
603 int otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev);
604 int otx2_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
605 struct timespec *timestamp,
607 int otx2_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
608 struct timespec *timestamp);
609 int otx2_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
610 int otx2_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
611 const struct timespec *ts);
612 int otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
613 struct timespec *ts);
614 int otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en);
615 int otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *time);
616 int otx2_nix_raw_clock_tsc_conv(struct otx2_eth_dev *dev);
617 void otx2_nix_ptp_enable_vf(struct rte_eth_dev *eth_dev);
619 #endif /* __OTX2_ETHDEV_H__ */