1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_ETHDEV_H__
6 #define __OTX2_ETHDEV_H__
11 #include <rte_common.h>
12 #include <rte_ethdev.h>
13 #include <rte_kvargs.h>
15 #include <rte_mempool.h>
16 #include <rte_security_driver.h>
17 #include <rte_string_fns.h>
20 #include "otx2_common.h"
22 #include "otx2_flow.h"
24 #include "otx2_mempool.h"
29 #define OTX2_ETH_DEV_PMD_VERSION "1.0"
31 /* Ethdev HWCAP and Fixup flags. Use from MSB bits to avoid conflict with dev */
33 /* Minimum CQ size should be 4K */
34 #define OTX2_FIXUP_F_MIN_4K_Q BIT_ULL(63)
35 #define otx2_ethdev_fixup_is_min_4k_q(dev) \
36 ((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)
37 /* Limit CQ being full */
38 #define OTX2_FIXUP_F_LIMIT_CQ_FULL BIT_ULL(62)
39 #define otx2_ethdev_fixup_is_limit_cq_full(dev) \
40 ((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)
42 /* Used for struct otx2_eth_dev::flags */
43 #define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0)
45 /* VLAN tag inserted by NIX_TX_VTAG_ACTION.
46 * In Tx space is always reserved for this in FRS.
48 #define NIX_MAX_VTAG_INS 2
49 #define NIX_MAX_VTAG_ACT_SIZE (4 * NIX_MAX_VTAG_INS)
51 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
52 #define NIX_L2_OVERHEAD \
53 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
54 #define NIX_L2_MAX_LEN \
55 (RTE_ETHER_MTU + NIX_L2_OVERHEAD)
57 /* HW config of frame size doesn't include FCS */
58 #define NIX_MAX_HW_FRS 9212
59 #define NIX_MIN_HW_FRS 60
61 /* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */
63 (NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)
66 (NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)
69 (NIX_MAX_FRS - NIX_L2_OVERHEAD)
71 #define NIX_MAX_SQB 512
72 #define NIX_DEF_SQB 16
74 #define NIX_SQB_LIST_SPACE 2
75 #define NIX_RSS_RETA_SIZE_MAX 256
76 /* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
77 #define NIX_RSS_GRPS 8
78 #define NIX_HASH_KEY_SIZE 48 /* 352 Bits */
79 #define NIX_RSS_RETA_SIZE 64
80 #define NIX_RX_MIN_DESC 16
81 #define NIX_RX_MIN_DESC_ALIGN 16
82 #define NIX_RX_NB_SEG_MAX 6
83 #define NIX_CQ_ENTRY_SZ 128
84 #define NIX_CQ_ALIGN 512
85 #define NIX_SQB_LOWER_THRESH 70
86 #define LMT_SLOT_MASK 0x7f
87 #define NIX_RX_DEFAULT_RING_SZ 4096
89 /* If PTP is enabled additional SEND MEM DESC is required which
90 * takes 2 words, hence max 7 iova address are possible
92 #if defined(RTE_LIBRTE_IEEE1588)
93 #define NIX_TX_NB_SEG_MAX 7
95 #define NIX_TX_NB_SEG_MAX 9
98 #define NIX_TX_MSEG_SG_DWORDS \
99 ((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3) \
102 /* Apply BP/DROP when CQ is 95% full */
103 #define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)
104 #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
106 #define CQ_OP_STAT_OP_ERR 63
107 #define CQ_OP_STAT_CQ_ERR 46
109 #define OP_ERR BIT_ULL(CQ_OP_STAT_OP_ERR)
110 #define CQ_ERR BIT_ULL(CQ_OP_STAT_CQ_ERR)
112 #define CQ_CQE_THRESH_DEFAULT 0x1ULL /* IRQ triggered when
113 * NIX_LF_CINTX_CNT[QCOUNT]
116 #define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
117 #define CQ_TIMER_THRESH_MAX 255
119 #define NIX_RSS_L3_L4_SRC_DST (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY \
120 | ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY)
122 #define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
123 ETH_RSS_TCP | ETH_RSS_SCTP | \
124 ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
125 NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | \
128 #define NIX_TX_OFFLOAD_CAPA ( \
129 DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
130 DEV_TX_OFFLOAD_MT_LOCKFREE | \
131 DEV_TX_OFFLOAD_VLAN_INSERT | \
132 DEV_TX_OFFLOAD_QINQ_INSERT | \
133 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
134 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \
135 DEV_TX_OFFLOAD_TCP_CKSUM | \
136 DEV_TX_OFFLOAD_UDP_CKSUM | \
137 DEV_TX_OFFLOAD_SCTP_CKSUM | \
138 DEV_TX_OFFLOAD_TCP_TSO | \
139 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
140 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
141 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
142 DEV_TX_OFFLOAD_MULTI_SEGS | \
143 DEV_TX_OFFLOAD_IPV4_CKSUM)
145 #define NIX_RX_OFFLOAD_CAPA ( \
146 DEV_RX_OFFLOAD_CHECKSUM | \
147 DEV_RX_OFFLOAD_SCTP_CKSUM | \
148 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
149 DEV_RX_OFFLOAD_SCATTER | \
150 DEV_RX_OFFLOAD_JUMBO_FRAME | \
151 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \
152 DEV_RX_OFFLOAD_VLAN_STRIP | \
153 DEV_RX_OFFLOAD_VLAN_FILTER | \
154 DEV_RX_OFFLOAD_QINQ_STRIP | \
155 DEV_RX_OFFLOAD_TIMESTAMP | \
156 DEV_RX_OFFLOAD_RSS_HASH)
158 #define NIX_DEFAULT_RSS_CTX_GROUP 0
159 #define NIX_DEFAULT_RSS_MCAM_IDX -1
161 #define otx2_ethdev_is_ptp_en(dev) ((dev)->ptp_en)
163 #define NIX_TIMESYNC_TX_CMD_LEN 8
164 /* Additional timesync values. */
165 #define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL
167 #define OCTEONTX2_PMD net_octeontx2
169 #define otx2_ethdev_is_same_driver(dev) \
170 (strcmp((dev)->device->driver->name, RTE_STR(OCTEONTX2_PMD)) == 0)
173 nix_q_size_16, /* 16 entries */
174 nix_q_size_64, /* 64 entries */
181 nix_q_size_1M, /* Million entries */
186 struct rte_eth_dev *eth_dev;
190 struct otx2_rss_info {
192 uint32_t flowkey_cfg;
195 uint8_t alg_idx; /* Selected algo index */
196 uint16_t ind_tbl[NIX_RSS_RETA_SIZE_MAX];
197 uint8_t key[NIX_HASH_KEY_SIZE];
200 struct otx2_eth_qconf {
202 struct rte_eth_txconf tx;
203 struct rte_eth_rxconf rx;
211 struct otx2_fc_info {
212 enum rte_eth_fc_mode mode; /**< Link flow control mode */
216 uint16_t bpid[NIX_MAX_CHAN];
219 struct vlan_mkex_info {
220 struct npc_xtract_info la_xtract;
221 struct npc_xtract_info lb_xtract;
222 uint64_t lb_lt_offset;
226 struct rte_ether_addr mcast_mac;
228 TAILQ_ENTRY(mcast_entry) next;
231 TAILQ_HEAD(otx2_nix_mc_filter_tbl, mcast_entry);
236 TAILQ_ENTRY(vlan_entry) next;
239 TAILQ_HEAD(otx2_vlan_filter_tbl, vlan_entry);
241 struct otx2_vlan_info {
242 struct otx2_vlan_filter_tbl fltr_tbl;
243 /* MKEX layer info */
244 struct mcam_entry def_tx_mcam_ent;
245 struct mcam_entry def_rx_mcam_ent;
246 struct vlan_mkex_info mkex;
247 /* Default mcam entry that matches vlan packets */
248 uint32_t def_rx_mcam_idx;
249 uint32_t def_tx_mcam_idx;
250 /* MCAM entry that matches double vlan packets */
251 uint32_t qinq_mcam_idx;
252 /* Indices of tx_vtag def registers */
253 uint32_t outer_vlan_idx;
254 uint32_t inner_vlan_idx;
255 uint16_t outer_vlan_tpid;
256 uint16_t inner_vlan_tpid;
258 /* QinQ entry allocated before default one */
259 uint8_t qinq_before_def;
260 uint8_t pvid_insert_on;
261 /* Rx vtag action type */
262 uint8_t vtag_type_idx;
269 struct otx2_eth_dev {
270 OTX2_DEV; /* Base class */
271 RTE_MARKER otx2_eth_dev_data_start;
273 uint16_t rx_chan_base;
274 uint16_t tx_chan_base;
277 uint8_t lso_tsov4_idx;
278 uint8_t lso_tsov6_idx;
279 uint8_t lso_base_idx;
280 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
281 uint8_t mkex_pfl_name[MKEX_NAME_LEN];
282 uint8_t max_mac_entries;
283 bool dmac_filter_enable;
292 uint8_t configured_qints;
293 uint8_t configured_cints;
294 uint8_t configured_nb_rx_qs;
295 uint8_t configured_nb_tx_qs;
296 uint8_t ptype_disable;
297 uint16_t nix_msixoff;
301 uint16_t rss_tag_as_xor;
302 uint16_t max_sqb_count;
303 uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
304 uint64_t rx_offloads;
305 uint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */
306 uint64_t tx_offloads;
307 uint64_t rx_offload_capa;
308 uint64_t tx_offload_capa;
309 struct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];
310 struct otx2_qint cints_mem[RTE_MAX_QUEUES_PER_PORT];
311 uint16_t txschq[NIX_TXSCH_LVL_CNT];
312 uint16_t txschq_contig[NIX_TXSCH_LVL_CNT];
313 uint16_t txschq_index[NIX_TXSCH_LVL_CNT];
314 uint16_t txschq_contig_index[NIX_TXSCH_LVL_CNT];
315 /* Dis-contiguous queues */
316 uint16_t txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
317 /* Contiguous queues */
318 uint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
319 uint16_t otx2_tm_root_lvl;
320 uint16_t link_cfg_lvl;
322 uint16_t tm_leaf_cnt;
323 uint64_t tm_rate_min;
324 struct otx2_nix_tm_node_list node_list;
325 struct otx2_nix_tm_shaper_profile_list shaper_profile_list;
326 struct otx2_rss_info rss_info;
327 struct otx2_fc_info fc_info;
328 uint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
329 uint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];
330 struct otx2_npc_flow_info npc_flow;
331 struct otx2_vlan_info vlan_info;
332 struct otx2_eth_qconf *tx_qconf;
333 struct otx2_eth_qconf *rx_qconf;
334 struct rte_eth_dev *eth_dev;
335 eth_rx_burst_t rx_pkt_burst_no_offload;
338 struct otx2_timesync_info tstamp;
339 struct rte_timecounter systime_tc;
340 struct rte_timecounter rx_tstamp_tc;
341 struct rte_timecounter tx_tstamp_tc;
342 double clk_freq_mult;
345 struct otx2_nix_mc_filter_tbl mc_fltr_tbl;
346 bool sdp_link; /* SDP flag */
347 /* Inline IPsec params */
348 uint16_t ipsec_in_max_spi;
351 } __rte_cache_aligned;
353 struct otx2_eth_txq {
355 int64_t fc_cache_pkts;
360 uint16_t sqes_per_sqb_log2;
361 int16_t nb_sqb_bufs_adj;
362 RTE_MARKER slow_path_start;
363 uint16_t nb_sqb_bufs;
366 struct otx2_eth_dev *dev;
367 struct rte_mempool *sqb_pool;
368 struct otx2_eth_qconf qconf;
369 } __rte_cache_aligned;
371 struct otx2_eth_rxq {
372 uint64_t mbuf_initializer;
383 struct otx2_timesync_info *tstamp;
384 RTE_MARKER slow_path_start;
388 struct rte_mempool *pool;
389 enum nix_q_size_e qsize;
390 struct rte_eth_dev *eth_dev;
391 struct otx2_eth_qconf qconf;
393 } __rte_cache_aligned;
395 static inline struct otx2_eth_dev *
396 otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
398 return eth_dev->data->dev_private;
402 int otx2_nix_info_get(struct rte_eth_dev *eth_dev,
403 struct rte_eth_dev_info *dev_info);
404 int otx2_nix_dev_flow_ops_get(struct rte_eth_dev *eth_dev,
405 const struct rte_flow_ops **ops);
406 int otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
408 int otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
409 struct rte_eth_dev_module_info *modinfo);
410 int otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
411 struct rte_dev_eeprom_info *info);
412 int otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);
413 void otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
414 struct rte_eth_rxq_info *qinfo);
415 void otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
416 struct rte_eth_txq_info *qinfo);
417 int otx2_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
418 struct rte_eth_burst_mode *mode);
419 int otx2_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
420 struct rte_eth_burst_mode *mode);
421 uint32_t otx2_nix_rx_queue_count(struct rte_eth_dev *eth_dev, uint16_t qidx);
422 int otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);
423 int otx2_nix_rx_descriptor_done(void *rxq, uint16_t offset);
424 int otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset);
425 int otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset);
427 void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en);
428 int otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);
429 int otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);
430 int otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);
431 int otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);
432 int otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx);
433 int otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx);
434 uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);
436 /* Multicast filter APIs */
437 void otx2_nix_mc_filter_init(struct otx2_eth_dev *dev);
438 void otx2_nix_mc_filter_fini(struct otx2_eth_dev *dev);
439 int otx2_nix_mc_addr_list_install(struct rte_eth_dev *eth_dev);
440 int otx2_nix_mc_addr_list_uninstall(struct rte_eth_dev *eth_dev);
441 int otx2_nix_set_mc_addr_list(struct rte_eth_dev *eth_dev,
442 struct rte_ether_addr *mc_addr_set,
443 uint32_t nb_mc_addr);
446 int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
447 int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);
448 void otx2_nix_enable_mseg_on_jumbo(struct otx2_eth_rxq *rxq);
452 void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
453 int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
454 void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
455 struct cgx_link_user_info *link);
456 int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);
457 int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);
458 int otx2_apply_link_speed(struct rte_eth_dev *eth_dev);
461 int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
462 int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);
463 int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
464 void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
465 void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
466 void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
467 void otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
468 void otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
470 int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
471 uint16_t rx_queue_id);
472 int otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
473 uint16_t rx_queue_id);
476 int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);
477 int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
478 struct rte_dev_reg_info *regs);
479 int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
480 void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
481 void otx2_nix_tm_dump(struct otx2_eth_dev *dev);
484 int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
485 struct rte_eth_stats *stats);
486 int otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev);
488 int otx2_nix_queue_stats_mapping(struct rte_eth_dev *dev,
489 uint16_t queue_id, uint8_t stat_idx,
491 int otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,
492 struct rte_eth_xstat *xstats, unsigned int n);
493 int otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,
494 struct rte_eth_xstat_name *xstats_names,
496 int otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev);
498 int otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev,
500 uint64_t *values, unsigned int n);
501 int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
502 struct rte_eth_xstat_name *xstats_names,
503 const uint64_t *ids, unsigned int limit);
506 void otx2_nix_rss_set_key(struct otx2_eth_dev *dev,
507 uint8_t *key, uint32_t key_len);
508 uint32_t otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev,
509 uint64_t ethdev_rss, uint8_t rss_level);
510 int otx2_rss_set_hf(struct otx2_eth_dev *dev,
511 uint32_t flowkey_cfg, uint8_t *alg_idx,
512 uint8_t group, int mcam_index);
513 int otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev, uint8_t group,
515 int otx2_nix_rss_config(struct rte_eth_dev *eth_dev);
517 int otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,
518 struct rte_eth_rss_reta_entry64 *reta_conf,
520 int otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,
521 struct rte_eth_rss_reta_entry64 *reta_conf,
523 int otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,
524 struct rte_eth_rss_conf *rss_conf);
526 int otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
527 struct rte_eth_rss_conf *rss_conf);
530 int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);
531 int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);
532 int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
533 struct rte_ether_addr *addr);
536 int otx2_nix_flow_ctrl_init(struct rte_eth_dev *eth_dev);
538 int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
539 struct rte_eth_fc_conf *fc_conf);
541 int otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,
542 struct rte_eth_fc_conf *fc_conf);
544 int otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb);
546 int otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev);
549 int otx2_nix_vlan_offload_init(struct rte_eth_dev *eth_dev);
550 int otx2_nix_vlan_fini(struct rte_eth_dev *eth_dev);
551 int otx2_nix_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);
552 void otx2_nix_vlan_update_promisc(struct rte_eth_dev *eth_dev, int enable);
553 int otx2_nix_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,
555 void otx2_nix_vlan_strip_queue_set(struct rte_eth_dev *dev,
556 uint16_t queue, int on);
557 int otx2_nix_vlan_tpid_set(struct rte_eth_dev *eth_dev,
558 enum rte_vlan_type type, uint16_t tpid);
559 int otx2_nix_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
561 /* Lookup configuration */
562 void *otx2_nix_fastpath_lookup_mem_get(void);
565 const uint32_t *otx2_nix_supported_ptypes_get(struct rte_eth_dev *dev);
566 int otx2_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask);
568 /* Mac address handling */
569 int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev,
570 struct rte_ether_addr *addr);
571 int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);
572 int otx2_nix_mac_addr_add(struct rte_eth_dev *eth_dev,
573 struct rte_ether_addr *addr,
574 uint32_t index, uint32_t pool);
575 void otx2_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);
576 int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
579 int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
580 struct otx2_eth_dev *dev);
582 /* Rx and Tx routines */
583 void otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev);
584 void otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev);
585 void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);
587 /* Timesync - PTP routines */
588 int otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev);
589 int otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev);
590 int otx2_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,
591 struct timespec *timestamp,
593 int otx2_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,
594 struct timespec *timestamp);
595 int otx2_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
596 int otx2_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
597 const struct timespec *ts);
598 int otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
599 struct timespec *ts);
600 int otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en);
601 int otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *time);
602 int otx2_nix_raw_clock_tsc_conv(struct otx2_eth_dev *dev);
603 void otx2_nix_ptp_enable_vf(struct rte_eth_dev *eth_dev);
605 #endif /* __OTX2_ETHDEV_H__ */