drivers/net/octeontx2/otx2_ethdev_debug.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2019 Marvell International Ltd.
   3  */
   4
   5 #include "otx2_ethdev.h"
   6
   7 #define nix_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__)
   8 #define NIX_REG_INFO(reg) {reg, #reg}
   9 #define NIX_REG_NAME_SZ 48
  10
  11 struct nix_lf_reg_info {
  12         uint32_t offset;
  13         const char *name;
  14 };
  15
  16 static const struct
  17 nix_lf_reg_info nix_lf_reg[] = {
  18         NIX_REG_INFO(NIX_LF_RX_SECRETX(0)),
  19         NIX_REG_INFO(NIX_LF_RX_SECRETX(1)),
  20         NIX_REG_INFO(NIX_LF_RX_SECRETX(2)),
  21         NIX_REG_INFO(NIX_LF_RX_SECRETX(3)),
  22         NIX_REG_INFO(NIX_LF_RX_SECRETX(4)),
  23         NIX_REG_INFO(NIX_LF_RX_SECRETX(5)),
  24         NIX_REG_INFO(NIX_LF_CFG),
  25         NIX_REG_INFO(NIX_LF_GINT),
  26         NIX_REG_INFO(NIX_LF_GINT_W1S),
  27         NIX_REG_INFO(NIX_LF_GINT_ENA_W1C),
  28         NIX_REG_INFO(NIX_LF_GINT_ENA_W1S),
  29         NIX_REG_INFO(NIX_LF_ERR_INT),
  30         NIX_REG_INFO(NIX_LF_ERR_INT_W1S),
  31         NIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1C),
  32         NIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1S),
  33         NIX_REG_INFO(NIX_LF_RAS),
  34         NIX_REG_INFO(NIX_LF_RAS_W1S),
  35         NIX_REG_INFO(NIX_LF_RAS_ENA_W1C),
  36         NIX_REG_INFO(NIX_LF_RAS_ENA_W1S),
  37         NIX_REG_INFO(NIX_LF_SQ_OP_ERR_DBG),
  38         NIX_REG_INFO(NIX_LF_MNQ_ERR_DBG),
  39         NIX_REG_INFO(NIX_LF_SEND_ERR_DBG),
  40 };
  41
  42 static int
  43 nix_lf_get_reg_count(struct otx2_eth_dev *dev)
  44 {
  45         int reg_count = 0;
  46
  47         reg_count = RTE_DIM(nix_lf_reg);
  48         /* NIX_LF_TX_STATX */
  49         reg_count += dev->lf_tx_stats;
  50         /* NIX_LF_RX_STATX */
  51         reg_count += dev->lf_rx_stats;
  52         /* NIX_LF_QINTX_CNT*/
  53         reg_count += dev->qints;
  54         /* NIX_LF_QINTX_INT */
  55         reg_count += dev->qints;
  56         /* NIX_LF_QINTX_ENA_W1S */
  57         reg_count += dev->qints;
  58         /* NIX_LF_QINTX_ENA_W1C */
  59         reg_count += dev->qints;
  60         /* NIX_LF_CINTX_CNT */
  61         reg_count += dev->cints;
  62         /* NIX_LF_CINTX_WAIT */
  63         reg_count += dev->cints;
  64         /* NIX_LF_CINTX_INT */
  65         reg_count += dev->cints;
  66         /* NIX_LF_CINTX_INT_W1S */
  67         reg_count += dev->cints;
  68         /* NIX_LF_CINTX_ENA_W1S */
  69         reg_count += dev->cints;
  70         /* NIX_LF_CINTX_ENA_W1C */
  71         reg_count += dev->cints;
  72
  73         return reg_count;
  74 }
  75
  76 int
  77 otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data)
  78 {
  79         uintptr_t nix_lf_base = dev->base;
  80         bool dump_stdout;
  81         uint64_t reg;
  82         uint32_t i;
  83
  84         dump_stdout = data ? 0 : 1;
  85
  86         for (i = 0; i < RTE_DIM(nix_lf_reg); i++) {
  87                 reg = otx2_read64(nix_lf_base + nix_lf_reg[i].offset);
  88                 if (dump_stdout && reg)
  89                         nix_dump("%32s = 0x%" PRIx64,
  90                                  nix_lf_reg[i].name, reg);
  91                 if (data)
  92                         *data++ = reg;
  93         }
  94
  95         /* NIX_LF_TX_STATX */
  96         for (i = 0; i < dev->lf_tx_stats; i++) {
  97                 reg = otx2_read64(nix_lf_base + NIX_LF_TX_STATX(i));
  98                 if (dump_stdout && reg)
  99                         nix_dump("%32s_%d = 0x%" PRIx64,
 100                                  "NIX_LF_TX_STATX", i, reg);
 101                 if (data)
 102                         *data++ = reg;
 103         }
 104
 105         /* NIX_LF_RX_STATX */
 106         for (i = 0; i < dev->lf_rx_stats; i++) {
 107                 reg = otx2_read64(nix_lf_base + NIX_LF_RX_STATX(i));
 108                 if (dump_stdout && reg)
 109                         nix_dump("%32s_%d = 0x%" PRIx64,
 110                                  "NIX_LF_RX_STATX", i, reg);
 111                 if (data)
 112                         *data++ = reg;
 113         }
 114
 115         /* NIX_LF_QINTX_CNT*/
 116         for (i = 0; i < dev->qints; i++) {
 117                 reg = otx2_read64(nix_lf_base + NIX_LF_QINTX_CNT(i));
 118                 if (dump_stdout && reg)
 119                         nix_dump("%32s_%d = 0x%" PRIx64,
 120                                  "NIX_LF_QINTX_CNT", i, reg);
 121                 if (data)
 122                         *data++ = reg;
 123         }
 124
 125         /* NIX_LF_QINTX_INT */
 126         for (i = 0; i < dev->qints; i++) {
 127                 reg = otx2_read64(nix_lf_base + NIX_LF_QINTX_INT(i));
 128                 if (dump_stdout && reg)
 129                         nix_dump("%32s_%d = 0x%" PRIx64,
 130                                  "NIX_LF_QINTX_INT", i, reg);
 131                 if (data)
 132                         *data++ = reg;
 133         }
 134
 135         /* NIX_LF_QINTX_ENA_W1S */
 136         for (i = 0; i < dev->qints; i++) {
 137                 reg = otx2_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1S(i));
 138                 if (dump_stdout && reg)
 139                         nix_dump("%32s_%d = 0x%" PRIx64,
 140                                  "NIX_LF_QINTX_ENA_W1S", i, reg);
 141                 if (data)
 142                         *data++ = reg;
 143         }
 144
 145         /* NIX_LF_QINTX_ENA_W1C */
 146         for (i = 0; i < dev->qints; i++) {
 147                 reg = otx2_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1C(i));
 148                 if (dump_stdout && reg)
 149                         nix_dump("%32s_%d = 0x%" PRIx64,
 150                                  "NIX_LF_QINTX_ENA_W1C", i, reg);
 151                 if (data)
 152                         *data++ = reg;
 153         }
 154
 155         /* NIX_LF_CINTX_CNT */
 156         for (i = 0; i < dev->cints; i++) {
 157                 reg = otx2_read64(nix_lf_base + NIX_LF_CINTX_CNT(i));
 158                 if (dump_stdout && reg)
 159                         nix_dump("%32s_%d = 0x%" PRIx64,
 160                                  "NIX_LF_CINTX_CNT", i, reg);
 161                 if (data)
 162                         *data++ = reg;
 163         }
 164
 165         /* NIX_LF_CINTX_WAIT */
 166         for (i = 0; i < dev->cints; i++) {
 167                 reg = otx2_read64(nix_lf_base + NIX_LF_CINTX_WAIT(i));
 168                 if (dump_stdout && reg)
 169                         nix_dump("%32s_%d = 0x%" PRIx64,
 170                                  "NIX_LF_CINTX_WAIT", i, reg);
 171                 if (data)
 172                         *data++ = reg;
 173         }
 174
 175         /* NIX_LF_CINTX_INT */
 176         for (i = 0; i < dev->cints; i++) {
 177                 reg = otx2_read64(nix_lf_base + NIX_LF_CINTX_INT(i));
 178                 if (dump_stdout && reg)
 179                         nix_dump("%32s_%d = 0x%" PRIx64,
 180                                  "NIX_LF_CINTX_INT", i, reg);
 181                 if (data)
 182                         *data++ = reg;
 183         }
 184
 185         /* NIX_LF_CINTX_INT_W1S */
 186         for (i = 0; i < dev->cints; i++) {
 187                 reg = otx2_read64(nix_lf_base + NIX_LF_CINTX_INT_W1S(i));
 188                 if (dump_stdout && reg)
 189                         nix_dump("%32s_%d = 0x%" PRIx64,
 190                                  "NIX_LF_CINTX_INT_W1S", i, reg);
 191                 if (data)
 192                         *data++ = reg;
 193         }
 194
 195         /* NIX_LF_CINTX_ENA_W1S */
 196         for (i = 0; i < dev->cints; i++) {
 197                 reg = otx2_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1S(i));
 198                 if (dump_stdout && reg)
 199                         nix_dump("%32s_%d = 0x%" PRIx64,
 200                                  "NIX_LF_CINTX_ENA_W1S", i, reg);
 201                 if (data)
 202                         *data++ = reg;
 203         }
 204
 205         /* NIX_LF_CINTX_ENA_W1C */
 206         for (i = 0; i < dev->cints; i++) {
 207                 reg = otx2_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1C(i));
 208                 if (dump_stdout && reg)
 209                         nix_dump("%32s_%d = 0x%" PRIx64,
 210                                  "NIX_LF_CINTX_ENA_W1C", i, reg);
 211                 if (data)
 212                         *data++ = reg;
 213         }
 214         return 0;
 215 }
 216
 217 int
 218 otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)
 219 {
 220         struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
 221         uint64_t *data = regs->data;
 222
 223         if (data == NULL) {
 224                 regs->length = nix_lf_get_reg_count(dev);
 225                 regs->width = 8;
 226                 return 0;
 227         }
 228
 229         if (!regs->length ||
 230             regs->length == (uint32_t)nix_lf_get_reg_count(dev)) {
 231                 otx2_nix_reg_dump(dev, data);
 232                 return 0;
 233         }
 234
 235         return -ENOTSUP;
 236 }
 237
 238 static inline void
 239 nix_lf_sq_dump(__otx2_io struct nix_sq_ctx_s *ctx)
 240 {
 241         nix_dump("W0: sqe_way_mask \t\t%d\nW0: cq \t\t\t\t%d",
 242                  ctx->sqe_way_mask, ctx->cq);
 243         nix_dump("W0: sdp_mcast \t\t\t%d\nW0: substream \t\t\t0x%03x",
 244                  ctx->sdp_mcast, ctx->substream);
 245         nix_dump("W0: qint_idx \t\t\t%d\nW0: ena \t\t\t%d\n",
 246                  ctx->qint_idx, ctx->ena);
 247
 248         nix_dump("W1: sqb_count \t\t\t%d\nW1: default_chan \t\t%d",
 249                  ctx->sqb_count, ctx->default_chan);
 250         nix_dump("W1: smq_rr_quantum \t\t%d\nW1: sso_ena \t\t\t%d",
 251                  ctx->smq_rr_quantum, ctx->sso_ena);
 252         nix_dump("W1: xoff \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: smq\t\t\t\t%d\n",
 253                  ctx->xoff, ctx->cq_ena, ctx->smq);
 254
 255         nix_dump("W2: sqe_stype \t\t\t%d\nW2: sq_int_ena \t\t\t%d",
 256                  ctx->sqe_stype, ctx->sq_int_ena);
 257         nix_dump("W2: sq_int  \t\t\t%d\nW2: sqb_aura \t\t\t%d",
 258                  ctx->sq_int, ctx->sqb_aura);
 259         nix_dump("W2: smq_rr_count \t\t%d\n",  ctx->smq_rr_count);
 260
 261         nix_dump("W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d",
 262                  ctx->smq_next_sq_vld, ctx->smq_pend);
 263         nix_dump("W3: smenq_next_sqb_vld  \t%d\nW3: head_offset\t\t\t%d",
 264                  ctx->smenq_next_sqb_vld, ctx->head_offset);
 265         nix_dump("W3: smenq_offset\t\t%d\nW3: tail_offset \t\t%d",
 266                  ctx->smenq_offset, ctx->tail_offset);
 267         nix_dump("W3: smq_lso_segnum \t\t%d\nW3: smq_next_sq \t\t%d",
 268                  ctx->smq_lso_segnum, ctx->smq_next_sq);
 269         nix_dump("W3: mnq_dis \t\t\t%d\nW3: lmt_dis \t\t\t%d",
 270                  ctx->mnq_dis, ctx->lmt_dis);
 271         nix_dump("W3: cq_limit\t\t\t%d\nW3: max_sqe_size\t\t%d\n",
 272                  ctx->cq_limit, ctx->max_sqe_size);
 273
 274         nix_dump("W4: next_sqb \t\t\t0x%" PRIx64 "", ctx->next_sqb);
 275         nix_dump("W5: tail_sqb \t\t\t0x%" PRIx64 "", ctx->tail_sqb);
 276         nix_dump("W6: smenq_sqb \t\t\t0x%" PRIx64 "", ctx->smenq_sqb);
 277         nix_dump("W7: smenq_next_sqb \t\t0x%" PRIx64 "", ctx->smenq_next_sqb);
 278         nix_dump("W8: head_sqb \t\t\t0x%" PRIx64 "", ctx->head_sqb);
 279
 280         nix_dump("W9: vfi_lso_vld \t\t%d\nW9: vfi_lso_vlan1_ins_ena\t%d",
 281                  ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena);
 282         nix_dump("W9: vfi_lso_vlan0_ins_ena\t%d\nW9: vfi_lso_mps\t\t\t%d",
 283                  ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps);
 284         nix_dump("W9: vfi_lso_sb \t\t\t%d\nW9: vfi_lso_sizem1\t\t%d",
 285                  ctx->vfi_lso_sb, ctx->vfi_lso_sizem1);
 286         nix_dump("W9: vfi_lso_total\t\t%d", ctx->vfi_lso_total);
 287
 288         nix_dump("W10: scm_lso_rem \t\t0x%" PRIx64 "",
 289                  (uint64_t)ctx->scm_lso_rem);
 290         nix_dump("W11: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
 291         nix_dump("W12: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
 292         nix_dump("W14: dropped_octs \t\t0x%" PRIx64 "",
 293                  (uint64_t)ctx->drop_octs);
 294         nix_dump("W15: dropped_pkts \t\t0x%" PRIx64 "",
 295                  (uint64_t)ctx->drop_pkts);
 296 }
 297
 298 static inline void
 299 nix_lf_rq_dump(__otx2_io struct nix_rq_ctx_s *ctx)
 300 {
 301         nix_dump("W0: wqe_aura \t\t\t%d\nW0: substream \t\t\t0x%03x",
 302                  ctx->wqe_aura, ctx->substream);
 303         nix_dump("W0: cq \t\t\t\t%d\nW0: ena_wqwd \t\t\t%d",
 304                  ctx->cq, ctx->ena_wqwd);
 305         nix_dump("W0: ipsech_ena \t\t\t%d\nW0: sso_ena \t\t\t%d",
 306                  ctx->ipsech_ena, ctx->sso_ena);
 307         nix_dump("W0: ena \t\t\t%d\n", ctx->ena);
 308
 309         nix_dump("W1: lpb_drop_ena \t\t%d\nW1: spb_drop_ena \t\t%d",
 310                  ctx->lpb_drop_ena, ctx->spb_drop_ena);
 311         nix_dump("W1: xqe_drop_ena \t\t%d\nW1: wqe_caching \t\t%d",
 312                  ctx->xqe_drop_ena, ctx->wqe_caching);
 313         nix_dump("W1: pb_caching \t\t\t%d\nW1: sso_tt \t\t\t%d",
 314                  ctx->pb_caching, ctx->sso_tt);
 315         nix_dump("W1: sso_grp \t\t\t%d\nW1: lpb_aura \t\t\t%d",
 316                  ctx->sso_grp, ctx->lpb_aura);
 317         nix_dump("W1: spb_aura \t\t\t%d\n", ctx->spb_aura);
 318
 319         nix_dump("W2: xqe_hdr_split \t\t%d\nW2: xqe_imm_copy \t\t%d",
 320                  ctx->xqe_hdr_split, ctx->xqe_imm_copy);
 321         nix_dump("W2: xqe_imm_size \t\t%d\nW2: later_skip \t\t\t%d",
 322                  ctx->xqe_imm_size, ctx->later_skip);
 323         nix_dump("W2: first_skip \t\t\t%d\nW2: lpb_sizem1 \t\t\t%d",
 324                  ctx->first_skip, ctx->lpb_sizem1);
 325         nix_dump("W2: spb_ena \t\t\t%d\nW2: wqe_skip \t\t\t%d",
 326                  ctx->spb_ena, ctx->wqe_skip);
 327         nix_dump("W2: spb_sizem1 \t\t\t%d\n", ctx->spb_sizem1);
 328
 329         nix_dump("W3: spb_pool_pass \t\t%d\nW3: spb_pool_drop \t\t%d",
 330                  ctx->spb_pool_pass, ctx->spb_pool_drop);
 331         nix_dump("W3: spb_aura_pass \t\t%d\nW3: spb_aura_drop \t\t%d",
 332                  ctx->spb_aura_pass, ctx->spb_aura_drop);
 333         nix_dump("W3: wqe_pool_pass \t\t%d\nW3: wqe_pool_drop \t\t%d",
 334                  ctx->wqe_pool_pass, ctx->wqe_pool_drop);
 335         nix_dump("W3: xqe_pass \t\t\t%d\nW3: xqe_drop \t\t\t%d\n",
 336                  ctx->xqe_pass, ctx->xqe_drop);
 337
 338         nix_dump("W4: qint_idx \t\t\t%d\nW4: rq_int_ena \t\t\t%d",
 339                  ctx->qint_idx, ctx->rq_int_ena);
 340         nix_dump("W4: rq_int \t\t\t%d\nW4: lpb_pool_pass \t\t%d",
 341                  ctx->rq_int, ctx->lpb_pool_pass);
 342         nix_dump("W4: lpb_pool_drop \t\t%d\nW4: lpb_aura_pass \t\t%d",
 343                  ctx->lpb_pool_drop, ctx->lpb_aura_pass);
 344         nix_dump("W4: lpb_aura_drop \t\t%d\n", ctx->lpb_aura_drop);
 345
 346         nix_dump("W5: flow_tagw \t\t\t%d\nW5: bad_utag \t\t\t%d",
 347                  ctx->flow_tagw, ctx->bad_utag);
 348         nix_dump("W5: good_utag \t\t\t%d\nW5: ltag \t\t\t%d\n",
 349                  ctx->good_utag, ctx->ltag);
 350
 351         nix_dump("W6: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
 352         nix_dump("W7: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
 353         nix_dump("W8: drop_octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_octs);
 354         nix_dump("W9: drop_pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_pkts);
 355         nix_dump("W10: re_pkts \t\t\t0x%" PRIx64 "\n", (uint64_t)ctx->re_pkts);
 356 }
 357
 358 static inline void
 359 nix_lf_cq_dump(__otx2_io struct nix_cq_ctx_s *ctx)
 360 {
 361         nix_dump("W0: base \t\t\t0x%" PRIx64 "\n", ctx->base);
 362
 363         nix_dump("W1: wrptr \t\t\t%" PRIx64 "", (uint64_t)ctx->wrptr);
 364         nix_dump("W1: avg_con \t\t\t%d\nW1: cint_idx \t\t\t%d",
 365                  ctx->avg_con, ctx->cint_idx);
 366         nix_dump("W1: cq_err \t\t\t%d\nW1: qint_idx \t\t\t%d",
 367                  ctx->cq_err, ctx->qint_idx);
 368         nix_dump("W1: bpid  \t\t\t%d\nW1: bp_ena \t\t\t%d\n",
 369                  ctx->bpid, ctx->bp_ena);
 370
 371         nix_dump("W2: update_time \t\t%d\nW2: avg_level \t\t\t%d",
 372                  ctx->update_time, ctx->avg_level);
 373         nix_dump("W2: head \t\t\t%d\nW2: tail \t\t\t%d\n",
 374                  ctx->head, ctx->tail);
 375
 376         nix_dump("W3: cq_err_int_ena \t\t%d\nW3: cq_err_int \t\t\t%d",
 377                  ctx->cq_err_int_ena, ctx->cq_err_int);
 378         nix_dump("W3: qsize \t\t\t%d\nW3: caching \t\t\t%d",
 379                  ctx->qsize, ctx->caching);
 380         nix_dump("W3: substream \t\t\t0x%03x\nW3: ena \t\t\t%d",
 381                  ctx->substream, ctx->ena);
 382         nix_dump("W3: drop_ena \t\t\t%d\nW3: drop \t\t\t%d",
 383                  ctx->drop_ena, ctx->drop);
 384         nix_dump("W3: bp \t\t\t\t%d\n", ctx->bp);
 385 }
 386
 387 int
 388 otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev)
 389 {
 390         struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
 391         int rc, q, rq = eth_dev->data->nb_rx_queues;
 392         int sq = eth_dev->data->nb_tx_queues;
 393         struct otx2_mbox *mbox = dev->mbox;
 394         struct npa_aq_enq_rsp *npa_rsp;
 395         struct npa_aq_enq_req *npa_aq;
 396         struct otx2_npa_lf *npa_lf;
 397         struct nix_aq_enq_rsp *rsp;
 398         struct nix_aq_enq_req *aq;
 399
 400         npa_lf = otx2_npa_lf_obj_get();
 401
 402         for (q = 0; q < rq; q++) {
 403                 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
 404                 aq->qidx = q;
 405                 aq->ctype = NIX_AQ_CTYPE_CQ;
 406                 aq->op = NIX_AQ_INSTOP_READ;
 407
 408                 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
 409                 if (rc) {
 410                         otx2_err("Failed to get cq context");
 411                         goto fail;
 412                 }
 413                 nix_dump("============== port=%d cq=%d ===============",
 414                          eth_dev->data->port_id, q);
 415                 nix_lf_cq_dump(&rsp->cq);
 416         }
 417
 418         for (q = 0; q < rq; q++) {
 419                 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
 420                 aq->qidx = q;
 421                 aq->ctype = NIX_AQ_CTYPE_RQ;
 422                 aq->op = NIX_AQ_INSTOP_READ;
 423
 424                 rc = otx2_mbox_process_msg(mbox, (void **)&rsp);
 425                 if (rc) {
 426                         otx2_err("Failed to get rq context");
 427                         goto fail;
 428                 }
 429                 nix_dump("============== port=%d rq=%d ===============",
 430                          eth_dev->data->port_id, q);
 431                 nix_lf_rq_dump(&rsp->rq);
 432         }
 433         for (q = 0; q < sq; q++) {
 434                 aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
 435                 aq->qidx = q;
 436                 aq->ctype = NIX_AQ_CTYPE_SQ;
 437                 aq->op = NIX_AQ_INSTOP_READ;
 438
 439                 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
 440                 if (rc) {
 441                         otx2_err("Failed to get sq context");
 442                         goto fail;
 443                 }
 444                 nix_dump("============== port=%d sq=%d ===============",
 445                          eth_dev->data->port_id, q);
 446                 nix_lf_sq_dump(&rsp->sq);
 447
 448                 if (!npa_lf) {
 449                         otx2_err("NPA LF doesn't exist");
 450                         continue;
 451                 }
 452
 453                 /* Dump SQB Aura minimal info */
 454                 npa_aq = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
 455                 npa_aq->aura_id = rsp->sq.sqb_aura;
 456                 npa_aq->ctype = NPA_AQ_CTYPE_AURA;
 457                 npa_aq->op = NPA_AQ_INSTOP_READ;
 458
 459                 rc = otx2_mbox_process_msg(npa_lf->mbox, (void *)&npa_rsp);
 460                 if (rc) {
 461                         otx2_err("Failed to get sq's sqb_aura context");
 462                         continue;
 463                 }
 464
 465                 nix_dump("\nSQB Aura W0: Pool addr\t\t0x%"PRIx64"",
 466                          npa_rsp->aura.pool_addr);
 467                 nix_dump("SQB Aura W1: ena\t\t\t%d",
 468                          npa_rsp->aura.ena);
 469                 nix_dump("SQB Aura W2: count\t\t%"PRIx64"",
 470                          (uint64_t)npa_rsp->aura.count);
 471                 nix_dump("SQB Aura W3: limit\t\t%"PRIx64"",
 472                          (uint64_t)npa_rsp->aura.limit);
 473                 nix_dump("SQB Aura W3: fc_ena\t\t%d",
 474                          npa_rsp->aura.fc_ena);
 475                 nix_dump("SQB Aura W4: fc_addr\t\t0x%"PRIx64"\n",
 476                          npa_rsp->aura.fc_addr);
 477         }
 478
 479 fail:
 480         return rc;
 481 }
 482
 483 /* Dumps struct nix_cqe_hdr_s and struct nix_rx_parse_s */
 484 void
 485 otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq)
 486 {
 487         const struct nix_rx_parse_s *rx =
 488                  (const struct nix_rx_parse_s *)((const uint64_t *)cq + 1);
 489
 490         nix_dump("tag \t\t0x%x\tq \t\t%d\t\tnode \t\t%d\tcqe_type \t%d",
 491                  cq->tag, cq->q, cq->node, cq->cqe_type);
 492
 493         nix_dump("W0: chan \t%d\t\tdesc_sizem1 \t%d",
 494                  rx->chan, rx->desc_sizem1);
 495         nix_dump("W0: imm_copy \t%d\t\texpress \t%d",
 496                  rx->imm_copy, rx->express);
 497         nix_dump("W0: wqwd \t%d\t\terrlev \t\t%d\t\terrcode \t%d",
 498                  rx->wqwd, rx->errlev, rx->errcode);
 499         nix_dump("W0: latype \t%d\t\tlbtype \t\t%d\t\tlctype \t\t%d",
 500                  rx->latype, rx->lbtype, rx->lctype);
 501         nix_dump("W0: ldtype \t%d\t\tletype \t\t%d\t\tlftype \t\t%d",
 502                  rx->ldtype, rx->letype, rx->lftype);
 503         nix_dump("W0: lgtype \t%d \t\tlhtype \t\t%d",
 504                  rx->lgtype, rx->lhtype);
 505
 506         nix_dump("W1: pkt_lenm1 \t%d", rx->pkt_lenm1);
 507         nix_dump("W1: l2m \t%d\t\tl2b \t\t%d\t\tl3m \t\t%d\tl3b \t\t%d",
 508                  rx->l2m, rx->l2b, rx->l3m, rx->l3b);
 509         nix_dump("W1: vtag0_valid %d\t\tvtag0_gone \t%d",
 510                  rx->vtag0_valid, rx->vtag0_gone);
 511         nix_dump("W1: vtag1_valid %d\t\tvtag1_gone \t%d",
 512                  rx->vtag1_valid, rx->vtag1_gone);
 513         nix_dump("W1: pkind \t%d", rx->pkind);
 514         nix_dump("W1: vtag0_tci \t%d\t\tvtag1_tci \t%d",
 515                  rx->vtag0_tci, rx->vtag1_tci);
 516
 517         nix_dump("W2: laflags \t%d\t\tlbflags\t\t%d\t\tlcflags \t%d",
 518                  rx->laflags, rx->lbflags, rx->lcflags);
 519         nix_dump("W2: ldflags \t%d\t\tleflags\t\t%d\t\tlfflags \t%d",
 520                  rx->ldflags, rx->leflags, rx->lfflags);
 521         nix_dump("W2: lgflags \t%d\t\tlhflags \t%d",
 522                  rx->lgflags, rx->lhflags);
 523
 524         nix_dump("W3: eoh_ptr \t%d\t\twqe_aura \t%d\t\tpb_aura \t%d",
 525                  rx->eoh_ptr, rx->wqe_aura, rx->pb_aura);
 526         nix_dump("W3: match_id \t%d", rx->match_id);
 527
 528         nix_dump("W4: laptr \t%d\t\tlbptr \t\t%d\t\tlcptr \t\t%d",
 529                  rx->laptr, rx->lbptr, rx->lcptr);
 530         nix_dump("W4: ldptr \t%d\t\tleptr \t\t%d\t\tlfptr \t\t%d",
 531                  rx->ldptr, rx->leptr, rx->lfptr);
 532         nix_dump("W4: lgptr \t%d\t\tlhptr \t\t%d", rx->lgptr, rx->lhptr);
 533
 534         nix_dump("W5: vtag0_ptr \t%d\t\tvtag1_ptr \t%d\t\tflow_key_alg \t%d",
 535                  rx->vtag0_ptr, rx->vtag1_ptr, rx->flow_key_alg);
 536 }
 537
 538 static uint8_t
 539 prepare_nix_tm_reg_dump(uint16_t hw_lvl, uint16_t schq, uint16_t link,
 540                         uint64_t *reg, char regstr[][NIX_REG_NAME_SZ])
 541 {
 542         uint8_t k = 0;
 543
 544         switch (hw_lvl) {
 545         case NIX_TXSCH_LVL_SMQ:
 546                 reg[k] = NIX_AF_SMQX_CFG(schq);
 547                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 548                          "NIX_AF_SMQ[%u]_CFG", schq);
 549
 550                 reg[k] = NIX_AF_MDQX_PARENT(schq);
 551                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 552                          "NIX_AF_MDQ[%u]_PARENT", schq);
 553
 554                 reg[k] = NIX_AF_MDQX_SCHEDULE(schq);
 555                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 556                          "NIX_AF_MDQ[%u]_SCHEDULE", schq);
 557
 558                 reg[k] = NIX_AF_MDQX_PIR(schq);
 559                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 560                          "NIX_AF_MDQ[%u]_PIR", schq);
 561
 562                 reg[k] = NIX_AF_MDQX_CIR(schq);
 563                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 564                          "NIX_AF_MDQ[%u]_CIR", schq);
 565
 566                 reg[k] = NIX_AF_MDQX_SHAPE(schq);
 567                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 568                          "NIX_AF_MDQ[%u]_SHAPE", schq);
 569
 570                 reg[k] = NIX_AF_MDQX_SW_XOFF(schq);
 571                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 572                          "NIX_AF_MDQ[%u]_SW_XOFF", schq);
 573                 break;
 574         case NIX_TXSCH_LVL_TL4:
 575                 reg[k] = NIX_AF_TL4X_PARENT(schq);
 576                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 577                          "NIX_AF_TL4[%u]_PARENT", schq);
 578
 579                 reg[k] = NIX_AF_TL4X_TOPOLOGY(schq);
 580                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 581                          "NIX_AF_TL4[%u]_TOPOLOGY", schq);
 582
 583                 reg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq);
 584                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 585                          "NIX_AF_TL4[%u]_SDP_LINK_CFG", schq);
 586
 587                 reg[k] = NIX_AF_TL4X_SCHEDULE(schq);
 588                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 589                          "NIX_AF_TL4[%u]_SCHEDULE", schq);
 590
 591                 reg[k] = NIX_AF_TL4X_PIR(schq);
 592                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 593                          "NIX_AF_TL4[%u]_PIR", schq);
 594
 595                 reg[k] = NIX_AF_TL4X_CIR(schq);
 596                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 597                          "NIX_AF_TL4[%u]_CIR", schq);
 598
 599                 reg[k] = NIX_AF_TL4X_SHAPE(schq);
 600                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 601                          "NIX_AF_TL4[%u]_SHAPE", schq);
 602
 603                 reg[k] = NIX_AF_TL4X_SW_XOFF(schq);
 604                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 605                          "NIX_AF_TL4[%u]_SW_XOFF", schq);
 606                 break;
 607         case NIX_TXSCH_LVL_TL3:
 608                 reg[k] = NIX_AF_TL3X_PARENT(schq);
 609                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 610                          "NIX_AF_TL3[%u]_PARENT", schq);
 611
 612                 reg[k] = NIX_AF_TL3X_TOPOLOGY(schq);
 613                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 614                          "NIX_AF_TL3[%u]_TOPOLOGY", schq);
 615
 616                 reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
 617                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 618                          "NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq, link);
 619
 620                 reg[k] = NIX_AF_TL3X_SCHEDULE(schq);
 621                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 622                          "NIX_AF_TL3[%u]_SCHEDULE", schq);
 623
 624                 reg[k] = NIX_AF_TL3X_PIR(schq);
 625                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 626                          "NIX_AF_TL3[%u]_PIR", schq);
 627
 628                 reg[k] = NIX_AF_TL3X_CIR(schq);
 629                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 630                          "NIX_AF_TL3[%u]_CIR", schq);
 631
 632                 reg[k] = NIX_AF_TL3X_SHAPE(schq);
 633                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 634                          "NIX_AF_TL3[%u]_SHAPE", schq);
 635
 636                 reg[k] = NIX_AF_TL3X_SW_XOFF(schq);
 637                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 638                          "NIX_AF_TL3[%u]_SW_XOFF", schq);
 639                 break;
 640         case NIX_TXSCH_LVL_TL2:
 641                 reg[k] = NIX_AF_TL2X_PARENT(schq);
 642                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 643                          "NIX_AF_TL2[%u]_PARENT", schq);
 644
 645                 reg[k] = NIX_AF_TL2X_TOPOLOGY(schq);
 646                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 647                          "NIX_AF_TL2[%u]_TOPOLOGY", schq);
 648
 649                 reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
 650                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 651                          "NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq, link);
 652
 653                 reg[k] = NIX_AF_TL2X_SCHEDULE(schq);
 654                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 655                          "NIX_AF_TL2[%u]_SCHEDULE", schq);
 656
 657                 reg[k] = NIX_AF_TL2X_PIR(schq);
 658                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 659                          "NIX_AF_TL2[%u]_PIR", schq);
 660
 661                 reg[k] = NIX_AF_TL2X_CIR(schq);
 662                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 663                          "NIX_AF_TL2[%u]_CIR", schq);
 664
 665                 reg[k] = NIX_AF_TL2X_SHAPE(schq);
 666                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 667                          "NIX_AF_TL2[%u]_SHAPE", schq);
 668
 669                 reg[k] = NIX_AF_TL2X_SW_XOFF(schq);
 670                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 671                          "NIX_AF_TL2[%u]_SW_XOFF", schq);
 672                 break;
 673         case NIX_TXSCH_LVL_TL1:
 674
 675                 reg[k] = NIX_AF_TL1X_TOPOLOGY(schq);
 676                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 677                          "NIX_AF_TL1[%u]_TOPOLOGY", schq);
 678
 679                 reg[k] = NIX_AF_TL1X_SCHEDULE(schq);
 680                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 681                          "NIX_AF_TL1[%u]_SCHEDULE", schq);
 682
 683                 reg[k] = NIX_AF_TL1X_CIR(schq);
 684                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 685                          "NIX_AF_TL1[%u]_CIR", schq);
 686
 687                 reg[k] = NIX_AF_TL1X_SW_XOFF(schq);
 688                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 689                          "NIX_AF_TL1[%u]_SW_XOFF", schq);
 690
 691                 reg[k] = NIX_AF_TL1X_DROPPED_PACKETS(schq);
 692                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 693                          "NIX_AF_TL1[%u]_DROPPED_PACKETS", schq);
 694                 break;
 695         default:
 696                 break;
 697         }
 698
 699         if (k > MAX_REGS_PER_MBOX_MSG) {
 700                 nix_dump("\t!!!NIX TM Registers request overflow!!!");
 701                 return 0;
 702         }
 703         return k;
 704 }
 705
 706 /* Dump TM hierarchy and registers */
 707 void
 708 otx2_nix_tm_dump(struct otx2_eth_dev *dev)
 709 {
 710         char regstr[MAX_REGS_PER_MBOX_MSG * 2][NIX_REG_NAME_SZ];
 711         struct otx2_nix_tm_node *tm_node, *root_node, *parent;
 712         uint64_t reg[MAX_REGS_PER_MBOX_MSG * 2];
 713         struct nix_txschq_config *req;
 714         const char *lvlstr, *parent_lvlstr;
 715         struct nix_txschq_config *rsp;
 716         uint32_t schq, parent_schq;
 717         int hw_lvl, j, k, rc;
 718
 719         nix_dump("===TM hierarchy and registers dump of %s===",
 720                  dev->eth_dev->data->name);
 721
 722         root_node = NULL;
 723
 724         for (hw_lvl = 0; hw_lvl <= NIX_TXSCH_LVL_CNT; hw_lvl++) {
 725                 TAILQ_FOREACH(tm_node, &dev->node_list, node) {
 726                         if (tm_node->hw_lvl != hw_lvl)
 727                                 continue;
 728
 729                         parent = tm_node->parent;
 730                         if (hw_lvl == NIX_TXSCH_LVL_CNT) {
 731                                 lvlstr = "SQ";
 732                                 schq = tm_node->id;
 733                         } else {
 734                                 lvlstr = nix_hwlvl2str(tm_node->hw_lvl);
 735                                 schq = tm_node->hw_id;
 736                         }
 737
 738                         if (parent) {
 739                                 parent_schq = parent->hw_id;
 740                                 parent_lvlstr =
 741                                         nix_hwlvl2str(parent->hw_lvl);
 742                         } else if (tm_node->hw_lvl == NIX_TXSCH_LVL_TL1) {
 743                                 parent_schq = otx2_nix_get_link(dev);
 744                                 parent_lvlstr = "LINK";
 745                         } else {
 746                                 parent_schq = tm_node->parent_hw_id;
 747                                 parent_lvlstr =
 748                                         nix_hwlvl2str(tm_node->hw_lvl + 1);
 749                         }
 750
 751                         nix_dump("%s_%d->%s_%d", lvlstr, schq,
 752                                  parent_lvlstr, parent_schq);
 753
 754                         if (!(tm_node->flags & NIX_TM_NODE_HWRES))
 755                                 continue;
 756
 757                         /* Need to dump TL1 when root is TL2 */
 758                         if (tm_node->hw_lvl == dev->otx2_tm_root_lvl)
 759                                 root_node = tm_node;
 760
 761                         /* Dump registers only when HWRES is present */
 762                         k = prepare_nix_tm_reg_dump(tm_node->hw_lvl, schq,
 763                                                     otx2_nix_get_link(dev), reg,
 764                                                     regstr);
 765                         if (!k)
 766                                 continue;
 767
 768                         req = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);
 769                         req->read = 1;
 770                         req->lvl = tm_node->hw_lvl;
 771                         req->num_regs = k;
 772                         otx2_mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);
 773                         rc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);
 774                         if (!rc) {
 775                                 for (j = 0; j < k; j++)
 776                                         nix_dump("\t%s=0x%016"PRIx64,
 777                                                  regstr[j], rsp->regval[j]);
 778                         } else {
 779                                 nix_dump("\t!!!Failed to dump registers!!!");
 780                         }
 781                 }
 782                 nix_dump("\n");
 783         }
 784
 785         /* Dump TL1 node data when root level is TL2 */
 786         if (root_node && root_node->hw_lvl == NIX_TXSCH_LVL_TL2) {
 787                 k = prepare_nix_tm_reg_dump(NIX_TXSCH_LVL_TL1,
 788                                             root_node->parent_hw_id,
 789                                             otx2_nix_get_link(dev),
 790                                             reg, regstr);
 791                 if (!k)
 792                         return;
 793
 794
 795                 req = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);
 796                 req->read = 1;
 797                 req->lvl = NIX_TXSCH_LVL_TL1;
 798                 req->num_regs = k;
 799                 otx2_mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);
 800                 rc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);
 801                 if (!rc) {
 802                         for (j = 0; j < k; j++)
 803                                 nix_dump("\t%s=0x%016"PRIx64,
 804                                          regstr[j], rsp->regval[j]);
 805                 } else {
 806                         nix_dump("\t!!!Failed to dump registers!!!");
 807                 }
 808         }
 809
 810         otx2_nix_queues_ctx_dump(dev->eth_dev);
 811 }