1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
8 #include "otx2_ethdev.h"
11 parse_flow_max_priority(const char *key, const char *value, void *extra_args)
18 /* Limit the max priority to 32 */
19 if (val < 1 || val > 32)
22 *(uint16_t *)extra_args = val;
28 parse_flow_prealloc_size(const char *key, const char *value, void *extra_args)
35 /* Limit the prealloc size to 32 */
36 if (val < 1 || val > 32)
39 *(uint16_t *)extra_args = val;
45 parse_reta_size(const char *key, const char *value, void *extra_args)
52 if (val <= ETH_RSS_RETA_SIZE_64)
53 val = ETH_RSS_RETA_SIZE_64;
54 else if (val > ETH_RSS_RETA_SIZE_64 && val <= ETH_RSS_RETA_SIZE_128)
55 val = ETH_RSS_RETA_SIZE_128;
56 else if (val > ETH_RSS_RETA_SIZE_128 && val <= ETH_RSS_RETA_SIZE_256)
57 val = ETH_RSS_RETA_SIZE_256;
59 val = NIX_RSS_RETA_SIZE;
61 *(uint16_t *)extra_args = val;
67 parse_ipsec_in_max_spi(const char *key, const char *value, void *extra_args)
74 *(uint16_t *)extra_args = val;
80 parse_flag(const char *key, const char *value, void *extra_args)
84 *(uint16_t *)extra_args = atoi(value);
90 parse_sqb_count(const char *key, const char *value, void *extra_args)
97 if (val < NIX_MIN_SQB || val > NIX_MAX_SQB)
100 *(uint16_t *)extra_args = val;
106 parse_switch_header_type(const char *key, const char *value, void *extra_args)
110 if (strcmp(value, "higig2") == 0)
111 *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_HIGIG;
113 if (strcmp(value, "dsa") == 0)
114 *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EDSA;
116 if (strcmp(value, "chlen90b") == 0)
117 *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_CH_LEN_90B;
119 if (strcmp(value, "chlen24b") == 0)
120 *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_CH_LEN_24B;
122 if (strcmp(value, "exdsa") == 0)
123 *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EXDSA;
125 if (strcmp(value, "vlan_exdsa") == 0)
126 *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_VLAN_EXDSA;
131 #define OTX2_RSS_RETA_SIZE "reta_size"
132 #define OTX2_IPSEC_IN_MAX_SPI "ipsec_in_max_spi"
133 #define OTX2_SCL_ENABLE "scalar_enable"
134 #define OTX2_MAX_SQB_COUNT "max_sqb_count"
135 #define OTX2_FLOW_PREALLOC_SIZE "flow_prealloc_size"
136 #define OTX2_FLOW_MAX_PRIORITY "flow_max_priority"
137 #define OTX2_SWITCH_HEADER_TYPE "switch_header"
138 #define OTX2_RSS_TAG_AS_XOR "tag_as_xor"
139 #define OTX2_LOCK_RX_CTX "lock_rx_ctx"
140 #define OTX2_LOCK_TX_CTX "lock_tx_ctx"
143 otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
145 uint16_t rss_size = NIX_RSS_RETA_SIZE;
146 uint16_t sqb_count = NIX_MAX_SQB;
147 uint16_t flow_prealloc_size = 8;
148 uint16_t switch_header_type = 0;
149 uint16_t flow_max_priority = 3;
150 uint16_t ipsec_in_max_spi = 1;
151 uint16_t rss_tag_as_xor = 0;
152 uint16_t scalar_enable = 0;
153 struct rte_kvargs *kvlist;
154 uint16_t lock_rx_ctx = 0;
155 uint16_t lock_tx_ctx = 0;
160 kvlist = rte_kvargs_parse(devargs->args, NULL);
164 rte_kvargs_process(kvlist, OTX2_RSS_RETA_SIZE,
165 &parse_reta_size, &rss_size);
166 rte_kvargs_process(kvlist, OTX2_IPSEC_IN_MAX_SPI,
167 &parse_ipsec_in_max_spi, &ipsec_in_max_spi);
168 rte_kvargs_process(kvlist, OTX2_SCL_ENABLE,
169 &parse_flag, &scalar_enable);
170 rte_kvargs_process(kvlist, OTX2_MAX_SQB_COUNT,
171 &parse_sqb_count, &sqb_count);
172 rte_kvargs_process(kvlist, OTX2_FLOW_PREALLOC_SIZE,
173 &parse_flow_prealloc_size, &flow_prealloc_size);
174 rte_kvargs_process(kvlist, OTX2_FLOW_MAX_PRIORITY,
175 &parse_flow_max_priority, &flow_max_priority);
176 rte_kvargs_process(kvlist, OTX2_SWITCH_HEADER_TYPE,
177 &parse_switch_header_type, &switch_header_type);
178 rte_kvargs_process(kvlist, OTX2_RSS_TAG_AS_XOR,
179 &parse_flag, &rss_tag_as_xor);
180 rte_kvargs_process(kvlist, OTX2_LOCK_RX_CTX,
181 &parse_flag, &lock_rx_ctx);
182 rte_kvargs_process(kvlist, OTX2_LOCK_TX_CTX,
183 &parse_flag, &lock_tx_ctx);
184 otx2_parse_common_devargs(kvlist);
185 rte_kvargs_free(kvlist);
188 dev->ipsec_in_max_spi = ipsec_in_max_spi;
189 dev->scalar_ena = scalar_enable;
190 dev->rss_tag_as_xor = rss_tag_as_xor;
191 dev->max_sqb_count = sqb_count;
192 dev->lock_rx_ctx = lock_rx_ctx;
193 dev->lock_tx_ctx = lock_tx_ctx;
194 dev->rss_info.rss_size = rss_size;
195 dev->npc_flow.flow_prealloc_size = flow_prealloc_size;
196 dev->npc_flow.flow_max_priority = flow_max_priority;
197 dev->npc_flow.switch_header_type = switch_header_type;
204 RTE_PMD_REGISTER_PARAM_STRING(OCTEONTX2_PMD,
205 OTX2_RSS_RETA_SIZE "=<64|128|256>"
206 OTX2_IPSEC_IN_MAX_SPI "=<1-65535>"
208 OTX2_MAX_SQB_COUNT "=<8-512>"
209 OTX2_FLOW_PREALLOC_SIZE "=<1-32>"
210 OTX2_FLOW_MAX_PRIORITY "=<1-32>"
211 OTX2_SWITCH_HEADER_TYPE "=<higig2|dsa|chlen90b|chlen24b>"
212 OTX2_RSS_TAG_AS_XOR "=1"
213 OTX2_NPA_LOCK_MASK "=<1-65535>"
214 OTX2_LOCK_RX_CTX "=1"
215 OTX2_LOCK_TX_CTX "=1");