1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_bus_pci.h>
9 #include "otx2_ethdev.h"
12 nix_lf_err_irq(void *param)
14 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
15 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
18 intr = otx2_read64(dev->base + NIX_LF_ERR_INT);
22 otx2_err("Err_intr=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
25 otx2_write64(intr, dev->base + NIX_LF_ERR_INT);
27 /* Dump registers to std out */
28 otx2_nix_reg_dump(dev, NULL);
29 otx2_nix_queues_ctx_dump(eth_dev);
33 nix_lf_register_err_irq(struct rte_eth_dev *eth_dev)
35 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
36 struct rte_intr_handle *handle = &pci_dev->intr_handle;
37 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
40 vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
42 /* Clear err interrupt */
43 otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
44 /* Set used interrupt vectors */
45 rc = otx2_register_irq(handle, nix_lf_err_irq, eth_dev, vec);
46 /* Enable all dev interrupt except for RQ_DISABLED */
47 otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S);
53 nix_lf_unregister_err_irq(struct rte_eth_dev *eth_dev)
55 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
56 struct rte_intr_handle *handle = &pci_dev->intr_handle;
57 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
60 vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
62 /* Clear err interrupt */
63 otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
64 otx2_unregister_irq(handle, nix_lf_err_irq, eth_dev, vec);
68 nix_lf_ras_irq(void *param)
70 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
71 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
74 intr = otx2_read64(dev->base + NIX_LF_RAS);
78 otx2_err("Ras_intr=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
81 otx2_write64(intr, dev->base + NIX_LF_RAS);
83 /* Dump registers to std out */
84 otx2_nix_reg_dump(dev, NULL);
85 otx2_nix_queues_ctx_dump(eth_dev);
89 nix_lf_register_ras_irq(struct rte_eth_dev *eth_dev)
91 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
92 struct rte_intr_handle *handle = &pci_dev->intr_handle;
93 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
96 vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
98 /* Clear err interrupt */
99 otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
100 /* Set used interrupt vectors */
101 rc = otx2_register_irq(handle, nix_lf_ras_irq, eth_dev, vec);
102 /* Enable dev interrupt */
103 otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);
109 nix_lf_unregister_ras_irq(struct rte_eth_dev *eth_dev)
111 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
112 struct rte_intr_handle *handle = &pci_dev->intr_handle;
113 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
116 vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
118 /* Clear err interrupt */
119 otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
120 otx2_unregister_irq(handle, nix_lf_ras_irq, eth_dev, vec);
123 static inline uint8_t
124 nix_lf_q_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t q,
125 uint32_t off, uint64_t mask)
130 wdata = (uint64_t)q << 44;
131 reg = otx2_atomic64_add_nosync(wdata, (int64_t *)(dev->base + off));
133 if (reg & BIT_ULL(42) /* OP_ERR */) {
134 otx2_err("Failed execute irq get off=0x%x", off);
140 otx2_write64(wdata, dev->base + off);
145 static inline uint8_t
146 nix_lf_rq_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t rq)
148 return nix_lf_q_irq_get_and_clear(dev, rq, NIX_LF_RQ_OP_INT, ~0xff00);
151 static inline uint8_t
152 nix_lf_cq_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t cq)
154 return nix_lf_q_irq_get_and_clear(dev, cq, NIX_LF_CQ_OP_INT, ~0xff00);
157 static inline uint8_t
158 nix_lf_sq_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t sq)
160 return nix_lf_q_irq_get_and_clear(dev, sq, NIX_LF_SQ_OP_INT, ~0x1ff00);
164 nix_lf_sq_debug_reg(struct otx2_eth_dev *dev, uint32_t off)
168 reg = otx2_read64(dev->base + off);
169 if (reg & BIT_ULL(44))
170 otx2_err("SQ=%d err_code=0x%x",
171 (int)((reg >> 8) & 0xfffff), (uint8_t)(reg & 0xff));
175 nix_lf_q_irq(void *param)
177 struct otx2_qint *qint = (struct otx2_qint *)param;
178 struct rte_eth_dev *eth_dev = qint->eth_dev;
179 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
180 uint8_t irq, qintx = qint->qintx;
184 intr = otx2_read64(dev->base + NIX_LF_QINTX_INT(qintx));
188 otx2_err("Queue_intr=0x%" PRIx64 " qintx=%d pf=%d, vf=%d",
189 intr, qintx, dev->pf, dev->vf);
191 /* Handle RQ interrupts */
192 for (q = 0; q < eth_dev->data->nb_rx_queues; q++) {
194 irq = nix_lf_rq_irq_get_and_clear(dev, rq);
196 if (irq & BIT_ULL(NIX_RQINT_DROP))
197 otx2_err("RQ=%d NIX_RQINT_DROP", rq);
199 if (irq & BIT_ULL(NIX_RQINT_RED))
200 otx2_err("RQ=%d NIX_RQINT_RED", rq);
203 /* Handle CQ interrupts */
204 for (q = 0; q < eth_dev->data->nb_rx_queues; q++) {
206 irq = nix_lf_cq_irq_get_and_clear(dev, cq);
208 if (irq & BIT_ULL(NIX_CQERRINT_DOOR_ERR))
209 otx2_err("CQ=%d NIX_CQERRINT_DOOR_ERR", cq);
211 if (irq & BIT_ULL(NIX_CQERRINT_WR_FULL))
212 otx2_err("CQ=%d NIX_CQERRINT_WR_FULL", cq);
214 if (irq & BIT_ULL(NIX_CQERRINT_CQE_FAULT))
215 otx2_err("CQ=%d NIX_CQERRINT_CQE_FAULT", cq);
218 /* Handle SQ interrupts */
219 for (q = 0; q < eth_dev->data->nb_tx_queues; q++) {
221 irq = nix_lf_sq_irq_get_and_clear(dev, sq);
223 if (irq & BIT_ULL(NIX_SQINT_LMT_ERR)) {
224 otx2_err("SQ=%d NIX_SQINT_LMT_ERR", sq);
225 nix_lf_sq_debug_reg(dev, NIX_LF_SQ_OP_ERR_DBG);
227 if (irq & BIT_ULL(NIX_SQINT_MNQ_ERR)) {
228 otx2_err("SQ=%d NIX_SQINT_MNQ_ERR", sq);
229 nix_lf_sq_debug_reg(dev, NIX_LF_MNQ_ERR_DBG);
231 if (irq & BIT_ULL(NIX_SQINT_SEND_ERR)) {
232 otx2_err("SQ=%d NIX_SQINT_SEND_ERR", sq);
233 nix_lf_sq_debug_reg(dev, NIX_LF_SEND_ERR_DBG);
235 if (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) {
236 otx2_err("SQ=%d NIX_SQINT_SQB_ALLOC_FAIL", sq);
237 nix_lf_sq_debug_reg(dev, NIX_LF_SEND_ERR_DBG);
241 /* Clear interrupt */
242 otx2_write64(intr, dev->base + NIX_LF_QINTX_INT(qintx));
244 /* Dump registers to std out */
245 otx2_nix_reg_dump(dev, NULL);
246 otx2_nix_queues_ctx_dump(eth_dev);
250 oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev)
252 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
253 struct rte_intr_handle *handle = &pci_dev->intr_handle;
254 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
255 int vec, q, sqs, rqs, qs, rc = 0;
257 /* Figure out max qintx required */
258 rqs = RTE_MIN(dev->qints, eth_dev->data->nb_rx_queues);
259 sqs = RTE_MIN(dev->qints, eth_dev->data->nb_tx_queues);
260 qs = RTE_MAX(rqs, sqs);
262 dev->configured_qints = qs;
264 for (q = 0; q < qs; q++) {
265 vec = dev->nix_msixoff + NIX_LF_INT_VEC_QINT_START + q;
268 otx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q));
270 /* Clear interrupt */
271 otx2_write64(~0ull, dev->base + NIX_LF_QINTX_ENA_W1C(q));
273 dev->qints_mem[q].eth_dev = eth_dev;
274 dev->qints_mem[q].qintx = q;
276 /* Sync qints_mem update */
279 /* Register queue irq vector */
280 rc = otx2_register_irq(handle, nix_lf_q_irq,
281 &dev->qints_mem[q], vec);
285 otx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q));
286 otx2_write64(0, dev->base + NIX_LF_QINTX_INT(q));
287 /* Enable QINT interrupt */
288 otx2_write64(~0ull, dev->base + NIX_LF_QINTX_ENA_W1S(q));
295 oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev)
297 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
298 struct rte_intr_handle *handle = &pci_dev->intr_handle;
299 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
302 for (q = 0; q < dev->configured_qints; q++) {
303 vec = dev->nix_msixoff + NIX_LF_INT_VEC_QINT_START + q;
306 otx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q));
307 otx2_write64(0, dev->base + NIX_LF_QINTX_INT(q));
309 /* Clear interrupt */
310 otx2_write64(~0ull, dev->base + NIX_LF_QINTX_ENA_W1C(q));
312 /* Unregister queue irq vector */
313 otx2_unregister_irq(handle, nix_lf_q_irq,
314 &dev->qints_mem[q], vec);
319 otx2_nix_register_irqs(struct rte_eth_dev *eth_dev)
321 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
324 if (dev->nix_msixoff == MSIX_VECTOR_INVALID) {
325 otx2_err("Invalid NIXLF MSIX vector offset vector: 0x%x",
330 /* Register lf err interrupt */
331 rc = nix_lf_register_err_irq(eth_dev);
332 /* Register RAS interrupt */
333 rc |= nix_lf_register_ras_irq(eth_dev);
339 otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev)
341 nix_lf_unregister_err_irq(eth_dev);
342 nix_lf_unregister_ras_irq(eth_dev);