1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include <rte_bus_pci.h>
9 #include "otx2_ethdev.h"
12 nix_lf_err_irq(void *param)
14 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
15 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
18 intr = otx2_read64(dev->base + NIX_LF_ERR_INT);
22 otx2_err("Err_intr=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
25 otx2_write64(intr, dev->base + NIX_LF_ERR_INT);
29 nix_lf_register_err_irq(struct rte_eth_dev *eth_dev)
31 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
32 struct rte_intr_handle *handle = &pci_dev->intr_handle;
33 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
36 vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
38 /* Clear err interrupt */
39 otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
40 /* Set used interrupt vectors */
41 rc = otx2_register_irq(handle, nix_lf_err_irq, eth_dev, vec);
42 /* Enable all dev interrupt except for RQ_DISABLED */
43 otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S);
49 nix_lf_unregister_err_irq(struct rte_eth_dev *eth_dev)
51 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
52 struct rte_intr_handle *handle = &pci_dev->intr_handle;
53 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
56 vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
58 /* Clear err interrupt */
59 otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
60 otx2_unregister_irq(handle, nix_lf_err_irq, eth_dev, vec);
64 nix_lf_ras_irq(void *param)
66 struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
67 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
70 intr = otx2_read64(dev->base + NIX_LF_RAS);
74 otx2_err("Ras_intr=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
77 otx2_write64(intr, dev->base + NIX_LF_RAS);
81 nix_lf_register_ras_irq(struct rte_eth_dev *eth_dev)
83 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
84 struct rte_intr_handle *handle = &pci_dev->intr_handle;
85 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
88 vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
90 /* Clear err interrupt */
91 otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
92 /* Set used interrupt vectors */
93 rc = otx2_register_irq(handle, nix_lf_ras_irq, eth_dev, vec);
94 /* Enable dev interrupt */
95 otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);
101 nix_lf_unregister_ras_irq(struct rte_eth_dev *eth_dev)
103 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
104 struct rte_intr_handle *handle = &pci_dev->intr_handle;
105 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
108 vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
110 /* Clear err interrupt */
111 otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
112 otx2_unregister_irq(handle, nix_lf_ras_irq, eth_dev, vec);
115 static inline uint8_t
116 nix_lf_q_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t q,
117 uint32_t off, uint64_t mask)
122 wdata = (uint64_t)q << 44;
123 reg = otx2_atomic64_add_nosync(wdata, (int64_t *)(dev->base + off));
125 if (reg & BIT_ULL(42) /* OP_ERR */) {
126 otx2_err("Failed execute irq get off=0x%x", off);
132 otx2_write64(wdata, dev->base + off);
137 static inline uint8_t
138 nix_lf_rq_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t rq)
140 return nix_lf_q_irq_get_and_clear(dev, rq, NIX_LF_RQ_OP_INT, ~0xff00);
143 static inline uint8_t
144 nix_lf_cq_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t cq)
146 return nix_lf_q_irq_get_and_clear(dev, cq, NIX_LF_CQ_OP_INT, ~0xff00);
149 static inline uint8_t
150 nix_lf_sq_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t sq)
152 return nix_lf_q_irq_get_and_clear(dev, sq, NIX_LF_SQ_OP_INT, ~0x1ff00);
156 nix_lf_sq_debug_reg(struct otx2_eth_dev *dev, uint32_t off)
160 reg = otx2_read64(dev->base + off);
161 if (reg & BIT_ULL(44))
162 otx2_err("SQ=%d err_code=0x%x",
163 (int)((reg >> 8) & 0xfffff), (uint8_t)(reg & 0xff));
167 nix_lf_q_irq(void *param)
169 struct otx2_qint *qint = (struct otx2_qint *)param;
170 struct rte_eth_dev *eth_dev = qint->eth_dev;
171 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
172 uint8_t irq, qintx = qint->qintx;
176 intr = otx2_read64(dev->base + NIX_LF_QINTX_INT(qintx));
180 otx2_err("Queue_intr=0x%" PRIx64 " qintx=%d pf=%d, vf=%d",
181 intr, qintx, dev->pf, dev->vf);
183 /* Handle RQ interrupts */
184 for (q = 0; q < eth_dev->data->nb_rx_queues; q++) {
186 irq = nix_lf_rq_irq_get_and_clear(dev, rq);
188 if (irq & BIT_ULL(NIX_RQINT_DROP))
189 otx2_err("RQ=%d NIX_RQINT_DROP", rq);
191 if (irq & BIT_ULL(NIX_RQINT_RED))
192 otx2_err("RQ=%d NIX_RQINT_RED", rq);
195 /* Handle CQ interrupts */
196 for (q = 0; q < eth_dev->data->nb_rx_queues; q++) {
198 irq = nix_lf_cq_irq_get_and_clear(dev, cq);
200 if (irq & BIT_ULL(NIX_CQERRINT_DOOR_ERR))
201 otx2_err("CQ=%d NIX_CQERRINT_DOOR_ERR", cq);
203 if (irq & BIT_ULL(NIX_CQERRINT_WR_FULL))
204 otx2_err("CQ=%d NIX_CQERRINT_WR_FULL", cq);
206 if (irq & BIT_ULL(NIX_CQERRINT_CQE_FAULT))
207 otx2_err("CQ=%d NIX_CQERRINT_CQE_FAULT", cq);
210 /* Handle SQ interrupts */
211 for (q = 0; q < eth_dev->data->nb_tx_queues; q++) {
213 irq = nix_lf_sq_irq_get_and_clear(dev, sq);
215 if (irq & BIT_ULL(NIX_SQINT_LMT_ERR)) {
216 otx2_err("SQ=%d NIX_SQINT_LMT_ERR", sq);
217 nix_lf_sq_debug_reg(dev, NIX_LF_SQ_OP_ERR_DBG);
219 if (irq & BIT_ULL(NIX_SQINT_MNQ_ERR)) {
220 otx2_err("SQ=%d NIX_SQINT_MNQ_ERR", sq);
221 nix_lf_sq_debug_reg(dev, NIX_LF_MNQ_ERR_DBG);
223 if (irq & BIT_ULL(NIX_SQINT_SEND_ERR)) {
224 otx2_err("SQ=%d NIX_SQINT_SEND_ERR", sq);
225 nix_lf_sq_debug_reg(dev, NIX_LF_SEND_ERR_DBG);
227 if (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) {
228 otx2_err("SQ=%d NIX_SQINT_SQB_ALLOC_FAIL", sq);
229 nix_lf_sq_debug_reg(dev, NIX_LF_SEND_ERR_DBG);
233 /* Clear interrupt */
234 otx2_write64(intr, dev->base + NIX_LF_QINTX_INT(qintx));
238 oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev)
240 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
241 struct rte_intr_handle *handle = &pci_dev->intr_handle;
242 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
243 int vec, q, sqs, rqs, qs, rc = 0;
245 /* Figure out max qintx required */
246 rqs = RTE_MIN(dev->qints, eth_dev->data->nb_rx_queues);
247 sqs = RTE_MIN(dev->qints, eth_dev->data->nb_tx_queues);
248 qs = RTE_MAX(rqs, sqs);
250 dev->configured_qints = qs;
252 for (q = 0; q < qs; q++) {
253 vec = dev->nix_msixoff + NIX_LF_INT_VEC_QINT_START + q;
256 otx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q));
258 /* Clear interrupt */
259 otx2_write64(~0ull, dev->base + NIX_LF_QINTX_ENA_W1C(q));
261 dev->qints_mem[q].eth_dev = eth_dev;
262 dev->qints_mem[q].qintx = q;
264 /* Sync qints_mem update */
267 /* Register queue irq vector */
268 rc = otx2_register_irq(handle, nix_lf_q_irq,
269 &dev->qints_mem[q], vec);
273 otx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q));
274 otx2_write64(0, dev->base + NIX_LF_QINTX_INT(q));
275 /* Enable QINT interrupt */
276 otx2_write64(~0ull, dev->base + NIX_LF_QINTX_ENA_W1S(q));
283 oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev)
285 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
286 struct rte_intr_handle *handle = &pci_dev->intr_handle;
287 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
290 for (q = 0; q < dev->configured_qints; q++) {
291 vec = dev->nix_msixoff + NIX_LF_INT_VEC_QINT_START + q;
294 otx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q));
295 otx2_write64(0, dev->base + NIX_LF_QINTX_INT(q));
297 /* Clear interrupt */
298 otx2_write64(~0ull, dev->base + NIX_LF_QINTX_ENA_W1C(q));
300 /* Unregister queue irq vector */
301 otx2_unregister_irq(handle, nix_lf_q_irq,
302 &dev->qints_mem[q], vec);
307 otx2_nix_register_irqs(struct rte_eth_dev *eth_dev)
309 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
312 if (dev->nix_msixoff == MSIX_VECTOR_INVALID) {
313 otx2_err("Invalid NIXLF MSIX vector offset vector: 0x%x",
318 /* Register lf err interrupt */
319 rc = nix_lf_register_err_irq(eth_dev);
320 /* Register RAS interrupt */
321 rc |= nix_lf_register_ras_irq(eth_dev);
327 otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev)
329 nix_lf_unregister_err_irq(eth_dev);
330 nix_lf_unregister_ras_irq(eth_dev);