1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include "otx2_ethdev.h"
8 nix_cgx_promisc_config(struct rte_eth_dev *eth_dev, int en)
10 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
11 struct otx2_mbox *mbox = dev->mbox;
13 if (otx2_dev_is_vf(dev))
17 otx2_mbox_alloc_msg_cgx_promisc_enable(mbox);
19 otx2_mbox_alloc_msg_cgx_promisc_disable(mbox);
21 otx2_mbox_process(mbox);
25 otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en)
27 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
28 struct otx2_mbox *mbox = dev->mbox;
29 struct nix_rx_mode *req;
31 if (otx2_dev_is_vf(dev))
34 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
37 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
39 otx2_mbox_process(mbox);
40 eth_dev->data->promiscuous = en;
44 otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev)
46 otx2_nix_promisc_config(eth_dev, 1);
47 nix_cgx_promisc_config(eth_dev, 1);
51 otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev)
53 otx2_nix_promisc_config(eth_dev, 0);
54 nix_cgx_promisc_config(eth_dev, 0);
58 nix_allmulticast_config(struct rte_eth_dev *eth_dev, int en)
60 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
61 struct otx2_mbox *mbox = dev->mbox;
62 struct nix_rx_mode *req;
64 if (otx2_dev_is_vf(dev))
67 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
70 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_ALLMULTI;
71 else if (eth_dev->data->promiscuous)
72 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
74 otx2_mbox_process(mbox);
78 otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev)
80 nix_allmulticast_config(eth_dev, 1);
84 otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev)
86 nix_allmulticast_config(eth_dev, 0);
90 otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
92 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
93 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
95 devinfo->min_rx_bufsize = NIX_MIN_FRS;
96 devinfo->max_rx_pktlen = NIX_MAX_FRS;
97 devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;
98 devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
99 devinfo->max_mac_addrs = dev->max_mac_entries;
100 devinfo->max_vfs = pci_dev->max_vfs;
101 devinfo->max_mtu = devinfo->max_rx_pktlen - NIX_L2_OVERHEAD;
102 devinfo->min_mtu = devinfo->min_rx_bufsize - NIX_L2_OVERHEAD;
104 devinfo->rx_offload_capa = dev->rx_offload_capa;
105 devinfo->tx_offload_capa = dev->tx_offload_capa;
106 devinfo->rx_queue_offload_capa = 0;
107 devinfo->tx_queue_offload_capa = 0;
109 devinfo->reta_size = dev->rss_info.rss_size;
110 devinfo->hash_key_size = NIX_HASH_KEY_SIZE;
111 devinfo->flow_type_rss_offloads = NIX_RSS_OFFLOAD;
113 devinfo->default_rxconf = (struct rte_eth_rxconf) {
118 devinfo->default_txconf = (struct rte_eth_txconf) {
122 devinfo->rx_desc_lim = (struct rte_eth_desc_lim) {
123 .nb_max = UINT16_MAX,
124 .nb_min = NIX_RX_MIN_DESC,
125 .nb_align = NIX_RX_MIN_DESC_ALIGN,
126 .nb_seg_max = NIX_RX_NB_SEG_MAX,
127 .nb_mtu_seg_max = NIX_RX_NB_SEG_MAX,
129 devinfo->rx_desc_lim.nb_max =
130 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,
131 NIX_RX_MIN_DESC_ALIGN);
133 devinfo->tx_desc_lim = (struct rte_eth_desc_lim) {
134 .nb_max = UINT16_MAX,
137 .nb_seg_max = NIX_TX_NB_SEG_MAX,
138 .nb_mtu_seg_max = NIX_TX_NB_SEG_MAX,
141 /* Auto negotiation disabled */
142 devinfo->speed_capa = ETH_LINK_SPEED_FIXED;
143 devinfo->speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
144 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
145 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
147 devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP;