1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_ethdev.h>
6 #include <rte_mbuf_pool_ops.h>
8 #include "otx2_ethdev.h"
11 otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
13 uint32_t buffsz, frame_size = mtu + NIX_L2_OVERHEAD;
14 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
15 struct rte_eth_dev_data *data = eth_dev->data;
16 struct otx2_mbox *mbox = dev->mbox;
17 struct nix_frs_cfg *req;
20 frame_size += NIX_TIMESYNC_RX_OFFSET * otx2_ethdev_is_ptp_en(dev);
22 /* Check if MTU is within the allowed range */
23 if (frame_size < NIX_MIN_FRS || frame_size > NIX_MAX_FRS)
26 buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
28 /* Refuse MTU that requires the support of scattered packets
29 * when this feature has not been enabled before.
31 if (data->dev_started && frame_size > buffsz &&
32 !(dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER))
35 /* Check <seg size> * <max_seg> >= max_frame */
36 if ((dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER) &&
37 (frame_size > buffsz * NIX_RX_NB_SEG_MAX))
40 req = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);
41 req->update_smq = true;
42 if (otx2_dev_is_sdp(dev))
44 /* FRS HW config should exclude FCS but include NPC VTAG insert size */
45 req->maxlen = frame_size - RTE_ETHER_CRC_LEN + NIX_MAX_VTAG_ACT_SIZE;
47 rc = otx2_mbox_process(mbox);
51 /* Now just update Rx MAXLEN */
52 req = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);
53 req->maxlen = frame_size - RTE_ETHER_CRC_LEN;
54 if (otx2_dev_is_sdp(dev))
57 rc = otx2_mbox_process(mbox);
61 if (frame_size > NIX_L2_MAX_LEN)
62 dev->rx_offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
64 dev->rx_offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
66 /* Update max_rx_pkt_len */
67 data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
73 otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev)
75 struct rte_eth_dev_data *data = eth_dev->data;
76 struct otx2_eth_rxq *rxq;
80 rxq = data->rx_queues[0];
82 /* Setup scatter mode if needed by jumbo */
83 otx2_nix_enable_mseg_on_jumbo(rxq);
85 /* Setup MTU based on max_rx_pkt_len */
86 mtu = data->dev_conf.rxmode.max_rx_pkt_len - NIX_L2_OVERHEAD;
88 rc = otx2_nix_mtu_set(eth_dev, mtu);
90 otx2_err("Failed to set default MTU size %d", rc);
96 nix_cgx_promisc_config(struct rte_eth_dev *eth_dev, int en)
98 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
99 struct otx2_mbox *mbox = dev->mbox;
101 if (otx2_dev_is_vf_or_sdp(dev))
105 otx2_mbox_alloc_msg_cgx_promisc_enable(mbox);
107 otx2_mbox_alloc_msg_cgx_promisc_disable(mbox);
109 otx2_mbox_process(mbox);
113 otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en)
115 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
116 struct otx2_mbox *mbox = dev->mbox;
117 struct nix_rx_mode *req;
119 if (otx2_dev_is_vf(dev))
122 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
125 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
127 otx2_mbox_process(mbox);
128 eth_dev->data->promiscuous = en;
129 otx2_nix_vlan_update_promisc(eth_dev, en);
133 otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev)
135 otx2_nix_promisc_config(eth_dev, 1);
136 nix_cgx_promisc_config(eth_dev, 1);
142 otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev)
144 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
145 otx2_nix_promisc_config(eth_dev, dev->dmac_filter_enable);
146 nix_cgx_promisc_config(eth_dev, 0);
147 dev->dmac_filter_enable = false;
153 nix_allmulticast_config(struct rte_eth_dev *eth_dev, int en)
155 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
156 struct otx2_mbox *mbox = dev->mbox;
157 struct nix_rx_mode *req;
159 if (otx2_dev_is_vf(dev))
162 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
165 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_ALLMULTI;
166 else if (eth_dev->data->promiscuous)
167 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
169 otx2_mbox_process(mbox);
173 otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev)
175 nix_allmulticast_config(eth_dev, 1);
181 otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev)
183 nix_allmulticast_config(eth_dev, 0);
189 otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
190 struct rte_eth_rxq_info *qinfo)
192 struct otx2_eth_rxq *rxq;
194 rxq = eth_dev->data->rx_queues[queue_id];
196 qinfo->mp = rxq->pool;
197 qinfo->scattered_rx = eth_dev->data->scattered_rx;
198 qinfo->nb_desc = rxq->qconf.nb_desc;
200 qinfo->conf.rx_free_thresh = 0;
201 qinfo->conf.rx_drop_en = 0;
202 qinfo->conf.rx_deferred_start = 0;
203 qinfo->conf.offloads = rxq->offloads;
207 otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
208 struct rte_eth_txq_info *qinfo)
210 struct otx2_eth_txq *txq;
212 txq = eth_dev->data->tx_queues[queue_id];
214 qinfo->nb_desc = txq->qconf.nb_desc;
216 qinfo->conf.tx_thresh.pthresh = 0;
217 qinfo->conf.tx_thresh.hthresh = 0;
218 qinfo->conf.tx_thresh.wthresh = 0;
220 qinfo->conf.tx_free_thresh = 0;
221 qinfo->conf.tx_rs_thresh = 0;
222 qinfo->conf.offloads = txq->offloads;
223 qinfo->conf.tx_deferred_start = 0;
227 otx2_rx_burst_mode_get(struct rte_eth_dev *eth_dev,
228 __rte_unused uint16_t queue_id,
229 struct rte_eth_burst_mode *mode)
231 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
232 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
233 const struct burst_info {
236 } rx_offload_map[] = {
237 {NIX_RX_OFFLOAD_RSS_F, "RSS,"},
238 {NIX_RX_OFFLOAD_PTYPE_F, " Ptype,"},
239 {NIX_RX_OFFLOAD_CHECKSUM_F, " Checksum,"},
240 {NIX_RX_OFFLOAD_VLAN_STRIP_F, " VLAN Strip,"},
241 {NIX_RX_OFFLOAD_MARK_UPDATE_F, " Mark Update,"},
242 {NIX_RX_OFFLOAD_TSTAMP_F, " Timestamp,"},
243 {NIX_RX_MULTI_SEG_F, " Scattered,"}
245 static const char *const burst_mode[] = {"Vector Neon, Rx Offloads:",
246 "Scalar, Rx Offloads:"
250 /* Update burst mode info */
251 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
258 /* Update Rx offload info */
259 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
260 if (dev->rx_offload_flags & rx_offload_map[i].flags) {
261 rc = rte_strscpy(mode->info + bytes,
262 rx_offload_map[i].output,
276 otx2_tx_burst_mode_get(struct rte_eth_dev *eth_dev,
277 __rte_unused uint16_t queue_id,
278 struct rte_eth_burst_mode *mode)
280 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
281 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
282 const struct burst_info {
285 } tx_offload_map[] = {
286 {NIX_TX_OFFLOAD_L3_L4_CSUM_F, " Inner L3/L4 csum,"},
287 {NIX_TX_OFFLOAD_OL3_OL4_CSUM_F, " Outer L3/L4 csum,"},
288 {NIX_TX_OFFLOAD_VLAN_QINQ_F, " VLAN Insertion,"},
289 {NIX_TX_OFFLOAD_MBUF_NOFF_F, " MBUF free disable,"},
290 {NIX_TX_OFFLOAD_TSTAMP_F, " Timestamp,"},
291 {NIX_TX_OFFLOAD_TSO_F, " TSO,"},
292 {NIX_TX_MULTI_SEG_F, " Scattered,"}
294 static const char *const burst_mode[] = {"Vector Neon, Tx Offloads:",
295 "Scalar, Tx Offloads:"
299 /* Update burst mode info */
300 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
307 /* Update Tx offload info */
308 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
309 if (dev->tx_offload_flags & tx_offload_map[i].flags) {
310 rc = rte_strscpy(mode->info + bytes,
311 tx_offload_map[i].output,
325 nix_rx_head_tail_get(struct otx2_eth_dev *dev,
326 uint32_t *head, uint32_t *tail, uint16_t queue_idx)
330 if (head == NULL || tail == NULL)
333 reg = (((uint64_t)queue_idx) << 32);
334 val = otx2_atomic64_add_nosync(reg, (int64_t *)
335 (dev->base + NIX_LF_CQ_OP_STATUS));
336 if (val & (OP_ERR | CQ_ERR))
339 *tail = (uint32_t)(val & 0xFFFFF);
340 *head = (uint32_t)((val >> 20) & 0xFFFFF);
344 otx2_nix_rx_queue_count(struct rte_eth_dev *eth_dev, uint16_t queue_idx)
346 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[queue_idx];
347 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
350 nix_rx_head_tail_get(dev, &head, &tail, queue_idx);
351 return (tail - head) % rxq->qlen;
355 nix_offset_has_packet(uint32_t head, uint32_t tail, uint16_t offset)
357 /* Check given offset(queue index) has packet filled by HW */
358 if (tail > head && offset <= tail && offset >= head)
360 /* Wrap around case */
361 if (head > tail && (offset >= head || offset <= tail))
368 otx2_nix_rx_descriptor_done(void *rx_queue, uint16_t offset)
370 struct otx2_eth_rxq *rxq = rx_queue;
373 nix_rx_head_tail_get(otx2_eth_pmd_priv(rxq->eth_dev),
374 &head, &tail, rxq->rq);
376 return nix_offset_has_packet(head, tail, offset);
380 otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset)
382 struct otx2_eth_rxq *rxq = rx_queue;
385 if (rxq->qlen <= offset)
388 nix_rx_head_tail_get(otx2_eth_pmd_priv(rxq->eth_dev),
389 &head, &tail, rxq->rq);
391 if (nix_offset_has_packet(head, tail, offset))
392 return RTE_ETH_RX_DESC_DONE;
394 return RTE_ETH_RX_DESC_AVAIL;
398 nix_tx_head_tail_get(struct otx2_eth_dev *dev,
399 uint32_t *head, uint32_t *tail, uint16_t queue_idx)
403 if (head == NULL || tail == NULL)
406 reg = (((uint64_t)queue_idx) << 32);
407 val = otx2_atomic64_add_nosync(reg, (int64_t *)
408 (dev->base + NIX_LF_SQ_OP_STATUS));
412 *tail = (uint32_t)((val >> 28) & 0x3F);
413 *head = (uint32_t)((val >> 20) & 0x3F);
417 otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset)
419 struct otx2_eth_txq *txq = tx_queue;
422 if (txq->qconf.nb_desc <= offset)
425 nix_tx_head_tail_get(txq->dev, &head, &tail, txq->sq);
427 if (nix_offset_has_packet(head, tail, offset))
428 return RTE_ETH_TX_DESC_DONE;
430 return RTE_ETH_TX_DESC_FULL;
433 /* It is a NOP for octeontx2 as HW frees the buffer on xmit */
435 otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt)
438 RTE_SET_USED(free_cnt);
444 otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
447 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
448 int rc = (int)fw_size;
450 if (fw_size > sizeof(dev->mkex_pfl_name))
451 rc = sizeof(dev->mkex_pfl_name);
453 rc = strlcpy(fw_version, (char *)dev->mkex_pfl_name, rc);
455 rc += 1; /* Add the size of '\0' */
456 if (fw_size < (uint32_t)rc)
463 otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool)
465 RTE_SET_USED(eth_dev);
467 if (!strcmp(pool, rte_mbuf_platform_mempool_ops()))
474 otx2_nix_dev_flow_ops_get(struct rte_eth_dev *eth_dev __rte_unused,
475 const struct rte_flow_ops **ops)
477 *ops = &otx2_flow_ops;
481 static struct cgx_fw_data *
482 nix_get_fwdata(struct otx2_eth_dev *dev)
484 struct otx2_mbox *mbox = dev->mbox;
485 struct cgx_fw_data *rsp = NULL;
488 otx2_mbox_alloc_msg_cgx_get_aux_link_info(mbox);
490 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
492 otx2_err("Failed to get fw data: %d", rc);
500 otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
501 struct rte_eth_dev_module_info *modinfo)
503 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
504 struct cgx_fw_data *rsp;
506 rsp = nix_get_fwdata(dev);
510 modinfo->type = rsp->fwdata.sfp_eeprom.sff_id;
511 modinfo->eeprom_len = SFP_EEPROM_SIZE;
517 otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
518 struct rte_dev_eeprom_info *info)
520 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
521 struct cgx_fw_data *rsp;
523 if (!info->data || !info->length ||
524 (info->offset + info->length > SFP_EEPROM_SIZE))
527 rsp = nix_get_fwdata(dev);
531 otx2_mbox_memcpy(info->data, rsp->fwdata.sfp_eeprom.buf + info->offset,
538 otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
540 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
541 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
543 devinfo->min_rx_bufsize = NIX_MIN_FRS;
544 devinfo->max_rx_pktlen = NIX_MAX_FRS;
545 devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;
546 devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
547 devinfo->max_mac_addrs = dev->max_mac_entries;
548 devinfo->max_vfs = pci_dev->max_vfs;
549 devinfo->max_mtu = devinfo->max_rx_pktlen - NIX_L2_OVERHEAD;
550 devinfo->min_mtu = devinfo->min_rx_bufsize - NIX_L2_OVERHEAD;
552 devinfo->rx_offload_capa = dev->rx_offload_capa;
553 devinfo->tx_offload_capa = dev->tx_offload_capa;
554 devinfo->rx_queue_offload_capa = 0;
555 devinfo->tx_queue_offload_capa = 0;
557 devinfo->reta_size = dev->rss_info.rss_size;
558 devinfo->hash_key_size = NIX_HASH_KEY_SIZE;
559 devinfo->flow_type_rss_offloads = NIX_RSS_OFFLOAD;
561 devinfo->default_rxconf = (struct rte_eth_rxconf) {
566 devinfo->default_txconf = (struct rte_eth_txconf) {
570 devinfo->default_rxportconf = (struct rte_eth_dev_portconf) {
571 .ring_size = NIX_RX_DEFAULT_RING_SZ,
574 devinfo->rx_desc_lim = (struct rte_eth_desc_lim) {
575 .nb_max = UINT16_MAX,
576 .nb_min = NIX_RX_MIN_DESC,
577 .nb_align = NIX_RX_MIN_DESC_ALIGN,
578 .nb_seg_max = NIX_RX_NB_SEG_MAX,
579 .nb_mtu_seg_max = NIX_RX_NB_SEG_MAX,
581 devinfo->rx_desc_lim.nb_max =
582 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,
583 NIX_RX_MIN_DESC_ALIGN);
585 devinfo->tx_desc_lim = (struct rte_eth_desc_lim) {
586 .nb_max = UINT16_MAX,
589 .nb_seg_max = NIX_TX_NB_SEG_MAX,
590 .nb_mtu_seg_max = NIX_TX_NB_SEG_MAX,
593 /* Auto negotiation disabled */
594 devinfo->speed_capa = ETH_LINK_SPEED_FIXED;
595 if (!otx2_dev_is_vf_or_sdp(dev) && !otx2_dev_is_lbk(dev)) {
596 devinfo->speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
597 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G;
599 /* 50G and 100G to be supported for board version C0
602 if (!otx2_dev_is_Ax(dev))
603 devinfo->speed_capa |= ETH_LINK_SPEED_50G |
607 devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
608 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;