1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_ethdev.h>
6 #include <rte_mbuf_pool_ops.h>
8 #include "otx2_ethdev.h"
11 otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
13 uint32_t buffsz, frame_size = mtu + NIX_L2_OVERHEAD;
14 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
15 struct rte_eth_dev_data *data = eth_dev->data;
16 struct otx2_mbox *mbox = dev->mbox;
17 struct nix_frs_cfg *req;
20 /* Check if MTU is within the allowed range */
21 if (frame_size < NIX_MIN_FRS || frame_size > NIX_MAX_FRS)
24 buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
26 /* Refuse MTU that requires the support of scattered packets
27 * when this feature has not been enabled before.
29 if (data->dev_started && frame_size > buffsz &&
30 !(dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER))
33 /* Check <seg size> * <max_seg> >= max_frame */
34 if ((dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER) &&
35 (frame_size > buffsz * NIX_RX_NB_SEG_MAX))
38 req = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);
39 req->update_smq = true;
40 if (otx2_dev_is_sdp(dev))
42 /* FRS HW config should exclude FCS but include NPC VTAG insert size */
43 req->maxlen = frame_size - RTE_ETHER_CRC_LEN + NIX_MAX_VTAG_ACT_SIZE;
45 rc = otx2_mbox_process(mbox);
49 /* Now just update Rx MAXLEN */
50 req = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);
51 req->maxlen = frame_size - RTE_ETHER_CRC_LEN;
52 if (otx2_dev_is_sdp(dev))
55 rc = otx2_mbox_process(mbox);
59 if (frame_size > RTE_ETHER_MAX_LEN)
60 dev->rx_offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
62 dev->rx_offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
64 /* Update max_rx_pkt_len */
65 data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
71 otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev)
73 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
74 struct rte_eth_dev_data *data = eth_dev->data;
75 struct rte_pktmbuf_pool_private *mbp_priv;
76 struct otx2_eth_rxq *rxq;
81 /* Get rx buffer size */
82 rxq = data->rx_queues[0];
83 mbp_priv = rte_mempool_get_priv(rxq->pool);
84 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
86 /* Setup scatter mode if needed by jumbo */
87 if (data->dev_conf.rxmode.max_rx_pkt_len > buffsz)
88 dev->rx_offloads |= DEV_RX_OFFLOAD_SCATTER;
90 /* Setup MTU based on max_rx_pkt_len */
91 mtu = data->dev_conf.rxmode.max_rx_pkt_len - NIX_L2_OVERHEAD;
93 rc = otx2_nix_mtu_set(eth_dev, mtu);
95 otx2_err("Failed to set default MTU size %d", rc);
101 nix_cgx_promisc_config(struct rte_eth_dev *eth_dev, int en)
103 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
104 struct otx2_mbox *mbox = dev->mbox;
106 if (otx2_dev_is_vf_or_sdp(dev))
110 otx2_mbox_alloc_msg_cgx_promisc_enable(mbox);
112 otx2_mbox_alloc_msg_cgx_promisc_disable(mbox);
114 otx2_mbox_process(mbox);
118 otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en)
120 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
121 struct otx2_mbox *mbox = dev->mbox;
122 struct nix_rx_mode *req;
124 if (otx2_dev_is_vf(dev))
127 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
130 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
132 otx2_mbox_process(mbox);
133 eth_dev->data->promiscuous = en;
134 otx2_nix_vlan_update_promisc(eth_dev, en);
138 otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev)
140 otx2_nix_promisc_config(eth_dev, 1);
141 nix_cgx_promisc_config(eth_dev, 1);
147 otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev)
149 otx2_nix_promisc_config(eth_dev, 0);
150 nix_cgx_promisc_config(eth_dev, 0);
156 nix_allmulticast_config(struct rte_eth_dev *eth_dev, int en)
158 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
159 struct otx2_mbox *mbox = dev->mbox;
160 struct nix_rx_mode *req;
162 if (otx2_dev_is_vf(dev))
165 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
168 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_ALLMULTI;
169 else if (eth_dev->data->promiscuous)
170 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
172 otx2_mbox_process(mbox);
176 otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev)
178 nix_allmulticast_config(eth_dev, 1);
184 otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev)
186 nix_allmulticast_config(eth_dev, 0);
192 otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
193 struct rte_eth_rxq_info *qinfo)
195 struct otx2_eth_rxq *rxq;
197 rxq = eth_dev->data->rx_queues[queue_id];
199 qinfo->mp = rxq->pool;
200 qinfo->scattered_rx = eth_dev->data->scattered_rx;
201 qinfo->nb_desc = rxq->qconf.nb_desc;
203 qinfo->conf.rx_free_thresh = 0;
204 qinfo->conf.rx_drop_en = 0;
205 qinfo->conf.rx_deferred_start = 0;
206 qinfo->conf.offloads = rxq->offloads;
210 otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
211 struct rte_eth_txq_info *qinfo)
213 struct otx2_eth_txq *txq;
215 txq = eth_dev->data->tx_queues[queue_id];
217 qinfo->nb_desc = txq->qconf.nb_desc;
219 qinfo->conf.tx_thresh.pthresh = 0;
220 qinfo->conf.tx_thresh.hthresh = 0;
221 qinfo->conf.tx_thresh.wthresh = 0;
223 qinfo->conf.tx_free_thresh = 0;
224 qinfo->conf.tx_rs_thresh = 0;
225 qinfo->conf.offloads = txq->offloads;
226 qinfo->conf.tx_deferred_start = 0;
230 otx2_rx_burst_mode_get(struct rte_eth_dev *eth_dev,
231 __rte_unused uint16_t queue_id,
232 struct rte_eth_burst_mode *mode)
234 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
235 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
236 const struct burst_info {
239 } rx_offload_map[] = {
240 {NIX_RX_OFFLOAD_RSS_F, "RSS,"},
241 {NIX_RX_OFFLOAD_PTYPE_F, " Ptype,"},
242 {NIX_RX_OFFLOAD_CHECKSUM_F, " Checksum,"},
243 {NIX_RX_OFFLOAD_VLAN_STRIP_F, " VLAN Strip,"},
244 {NIX_RX_OFFLOAD_MARK_UPDATE_F, " Mark Update,"},
245 {NIX_RX_OFFLOAD_TSTAMP_F, " Timestamp,"},
246 {NIX_RX_MULTI_SEG_F, " Scattered,"}
248 static const char *const burst_mode[] = {"Vector Neon, Rx Offloads:",
249 "Scalar, Rx Offloads:"
253 /* Update burst mode info */
254 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
261 /* Update Rx offload info */
262 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
263 if (dev->rx_offload_flags & rx_offload_map[i].flags) {
264 rc = rte_strscpy(mode->info + bytes,
265 rx_offload_map[i].output,
279 otx2_tx_burst_mode_get(struct rte_eth_dev *eth_dev,
280 __rte_unused uint16_t queue_id,
281 struct rte_eth_burst_mode *mode)
283 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
284 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
285 const struct burst_info {
288 } tx_offload_map[] = {
289 {NIX_TX_OFFLOAD_L3_L4_CSUM_F, " Inner L3/L4 csum,"},
290 {NIX_TX_OFFLOAD_OL3_OL4_CSUM_F, " Outer L3/L4 csum,"},
291 {NIX_TX_OFFLOAD_VLAN_QINQ_F, " VLAN Insertion,"},
292 {NIX_TX_OFFLOAD_MBUF_NOFF_F, " MBUF free disable,"},
293 {NIX_TX_OFFLOAD_TSTAMP_F, " Timestamp,"},
294 {NIX_TX_OFFLOAD_TSO_F, " TSO,"},
295 {NIX_TX_MULTI_SEG_F, " Scattered,"}
297 static const char *const burst_mode[] = {"Vector Neon, Tx Offloads:",
298 "Scalar, Tx Offloads:"
302 /* Update burst mode info */
303 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
310 /* Update Tx offload info */
311 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
312 if (dev->tx_offload_flags & tx_offload_map[i].flags) {
313 rc = rte_strscpy(mode->info + bytes,
314 tx_offload_map[i].output,
328 nix_rx_head_tail_get(struct otx2_eth_dev *dev,
329 uint32_t *head, uint32_t *tail, uint16_t queue_idx)
333 if (head == NULL || tail == NULL)
336 reg = (((uint64_t)queue_idx) << 32);
337 val = otx2_atomic64_add_nosync(reg, (int64_t *)
338 (dev->base + NIX_LF_CQ_OP_STATUS));
339 if (val & (OP_ERR | CQ_ERR))
342 *tail = (uint32_t)(val & 0xFFFFF);
343 *head = (uint32_t)((val >> 20) & 0xFFFFF);
347 otx2_nix_rx_queue_count(struct rte_eth_dev *eth_dev, uint16_t queue_idx)
349 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[queue_idx];
350 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
353 nix_rx_head_tail_get(dev, &head, &tail, queue_idx);
354 return (tail - head) % rxq->qlen;
358 nix_offset_has_packet(uint32_t head, uint32_t tail, uint16_t offset)
360 /* Check given offset(queue index) has packet filled by HW */
361 if (tail > head && offset <= tail && offset >= head)
363 /* Wrap around case */
364 if (head > tail && (offset >= head || offset <= tail))
371 otx2_nix_rx_descriptor_done(void *rx_queue, uint16_t offset)
373 struct otx2_eth_rxq *rxq = rx_queue;
376 nix_rx_head_tail_get(otx2_eth_pmd_priv(rxq->eth_dev),
377 &head, &tail, rxq->rq);
379 return nix_offset_has_packet(head, tail, offset);
383 otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset)
385 struct otx2_eth_rxq *rxq = rx_queue;
388 if (rxq->qlen <= offset)
391 nix_rx_head_tail_get(otx2_eth_pmd_priv(rxq->eth_dev),
392 &head, &tail, rxq->rq);
394 if (nix_offset_has_packet(head, tail, offset))
395 return RTE_ETH_RX_DESC_DONE;
397 return RTE_ETH_RX_DESC_AVAIL;
401 nix_tx_head_tail_get(struct otx2_eth_dev *dev,
402 uint32_t *head, uint32_t *tail, uint16_t queue_idx)
406 if (head == NULL || tail == NULL)
409 reg = (((uint64_t)queue_idx) << 32);
410 val = otx2_atomic64_add_nosync(reg, (int64_t *)
411 (dev->base + NIX_LF_SQ_OP_STATUS));
415 *tail = (uint32_t)((val >> 28) & 0x3F);
416 *head = (uint32_t)((val >> 20) & 0x3F);
420 otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset)
422 struct otx2_eth_txq *txq = tx_queue;
425 if (txq->qconf.nb_desc <= offset)
428 nix_tx_head_tail_get(txq->dev, &head, &tail, txq->sq);
430 if (nix_offset_has_packet(head, tail, offset))
431 return RTE_ETH_TX_DESC_DONE;
433 return RTE_ETH_TX_DESC_FULL;
436 /* It is a NOP for octeontx2 as HW frees the buffer on xmit */
438 otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt)
441 RTE_SET_USED(free_cnt);
447 otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
450 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
451 int rc = (int)fw_size;
453 if (fw_size > sizeof(dev->mkex_pfl_name))
454 rc = sizeof(dev->mkex_pfl_name);
456 rc = strlcpy(fw_version, (char *)dev->mkex_pfl_name, rc);
458 rc += 1; /* Add the size of '\0' */
459 if (fw_size < (uint32_t)rc)
466 otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool)
468 RTE_SET_USED(eth_dev);
470 if (!strcmp(pool, rte_mbuf_platform_mempool_ops()))
477 otx2_nix_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
478 enum rte_filter_type filter_type,
479 enum rte_filter_op filter_op, void *arg)
481 RTE_SET_USED(eth_dev);
483 if (filter_type != RTE_ETH_FILTER_GENERIC) {
484 otx2_err("Unsupported filter type %d", filter_type);
488 if (filter_op == RTE_ETH_FILTER_GET) {
489 *(const void **)arg = &otx2_flow_ops;
493 otx2_err("Invalid filter_op %d", filter_op);
497 static struct cgx_fw_data *
498 nix_get_fwdata(struct otx2_eth_dev *dev)
500 struct otx2_mbox *mbox = dev->mbox;
501 struct cgx_fw_data *rsp = NULL;
504 otx2_mbox_alloc_msg_cgx_get_aux_link_info(mbox);
506 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
508 otx2_err("Failed to get fw data: %d", rc);
516 otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
517 struct rte_eth_dev_module_info *modinfo)
519 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
520 struct cgx_fw_data *rsp;
522 rsp = nix_get_fwdata(dev);
526 modinfo->type = rsp->fwdata.sfp_eeprom.sff_id;
527 modinfo->eeprom_len = SFP_EEPROM_SIZE;
533 otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
534 struct rte_dev_eeprom_info *info)
536 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
537 struct cgx_fw_data *rsp;
539 if (!info->data || !info->length ||
540 (info->offset + info->length > SFP_EEPROM_SIZE))
543 rsp = nix_get_fwdata(dev);
547 otx2_mbox_memcpy(info->data, rsp->fwdata.sfp_eeprom.buf + info->offset,
554 otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
556 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
557 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
559 devinfo->min_rx_bufsize = NIX_MIN_FRS;
560 devinfo->max_rx_pktlen = NIX_MAX_FRS;
561 devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;
562 devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
563 devinfo->max_mac_addrs = dev->max_mac_entries;
564 devinfo->max_vfs = pci_dev->max_vfs;
565 devinfo->max_mtu = devinfo->max_rx_pktlen - NIX_L2_OVERHEAD;
566 devinfo->min_mtu = devinfo->min_rx_bufsize - NIX_L2_OVERHEAD;
568 devinfo->rx_offload_capa = dev->rx_offload_capa;
569 devinfo->tx_offload_capa = dev->tx_offload_capa;
570 devinfo->rx_queue_offload_capa = 0;
571 devinfo->tx_queue_offload_capa = 0;
573 devinfo->reta_size = dev->rss_info.rss_size;
574 devinfo->hash_key_size = NIX_HASH_KEY_SIZE;
575 devinfo->flow_type_rss_offloads = NIX_RSS_OFFLOAD;
577 devinfo->default_rxconf = (struct rte_eth_rxconf) {
582 devinfo->default_txconf = (struct rte_eth_txconf) {
586 devinfo->default_rxportconf = (struct rte_eth_dev_portconf) {
587 .ring_size = NIX_RX_DEFAULT_RING_SZ,
590 devinfo->rx_desc_lim = (struct rte_eth_desc_lim) {
591 .nb_max = UINT16_MAX,
592 .nb_min = NIX_RX_MIN_DESC,
593 .nb_align = NIX_RX_MIN_DESC_ALIGN,
594 .nb_seg_max = NIX_RX_NB_SEG_MAX,
595 .nb_mtu_seg_max = NIX_RX_NB_SEG_MAX,
597 devinfo->rx_desc_lim.nb_max =
598 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,
599 NIX_RX_MIN_DESC_ALIGN);
601 devinfo->tx_desc_lim = (struct rte_eth_desc_lim) {
602 .nb_max = UINT16_MAX,
605 .nb_seg_max = NIX_TX_NB_SEG_MAX,
606 .nb_mtu_seg_max = NIX_TX_NB_SEG_MAX,
609 /* Auto negotiation disabled */
610 devinfo->speed_capa = ETH_LINK_SPEED_FIXED;
611 devinfo->speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
612 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
613 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
615 devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
616 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;