1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_mbuf_pool_ops.h>
7 #include "otx2_ethdev.h"
10 nix_cgx_promisc_config(struct rte_eth_dev *eth_dev, int en)
12 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
13 struct otx2_mbox *mbox = dev->mbox;
15 if (otx2_dev_is_vf(dev))
19 otx2_mbox_alloc_msg_cgx_promisc_enable(mbox);
21 otx2_mbox_alloc_msg_cgx_promisc_disable(mbox);
23 otx2_mbox_process(mbox);
27 otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en)
29 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
30 struct otx2_mbox *mbox = dev->mbox;
31 struct nix_rx_mode *req;
33 if (otx2_dev_is_vf(dev))
36 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
39 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
41 otx2_mbox_process(mbox);
42 eth_dev->data->promiscuous = en;
46 otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev)
48 otx2_nix_promisc_config(eth_dev, 1);
49 nix_cgx_promisc_config(eth_dev, 1);
53 otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev)
55 otx2_nix_promisc_config(eth_dev, 0);
56 nix_cgx_promisc_config(eth_dev, 0);
60 nix_allmulticast_config(struct rte_eth_dev *eth_dev, int en)
62 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
63 struct otx2_mbox *mbox = dev->mbox;
64 struct nix_rx_mode *req;
66 if (otx2_dev_is_vf(dev))
69 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
72 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_ALLMULTI;
73 else if (eth_dev->data->promiscuous)
74 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
76 otx2_mbox_process(mbox);
80 otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev)
82 nix_allmulticast_config(eth_dev, 1);
86 otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev)
88 nix_allmulticast_config(eth_dev, 0);
92 otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
93 struct rte_eth_rxq_info *qinfo)
95 struct otx2_eth_rxq *rxq;
97 rxq = eth_dev->data->rx_queues[queue_id];
99 qinfo->mp = rxq->pool;
100 qinfo->scattered_rx = eth_dev->data->scattered_rx;
101 qinfo->nb_desc = rxq->qconf.nb_desc;
103 qinfo->conf.rx_free_thresh = 0;
104 qinfo->conf.rx_drop_en = 0;
105 qinfo->conf.rx_deferred_start = 0;
106 qinfo->conf.offloads = rxq->offloads;
110 otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
111 struct rte_eth_txq_info *qinfo)
113 struct otx2_eth_txq *txq;
115 txq = eth_dev->data->tx_queues[queue_id];
117 qinfo->nb_desc = txq->qconf.nb_desc;
119 qinfo->conf.tx_thresh.pthresh = 0;
120 qinfo->conf.tx_thresh.hthresh = 0;
121 qinfo->conf.tx_thresh.wthresh = 0;
123 qinfo->conf.tx_free_thresh = 0;
124 qinfo->conf.tx_rs_thresh = 0;
125 qinfo->conf.offloads = txq->offloads;
126 qinfo->conf.tx_deferred_start = 0;
130 otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool)
132 RTE_SET_USED(eth_dev);
134 if (!strcmp(pool, rte_mbuf_platform_mempool_ops()))
141 otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
143 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
144 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
146 devinfo->min_rx_bufsize = NIX_MIN_FRS;
147 devinfo->max_rx_pktlen = NIX_MAX_FRS;
148 devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;
149 devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
150 devinfo->max_mac_addrs = dev->max_mac_entries;
151 devinfo->max_vfs = pci_dev->max_vfs;
152 devinfo->max_mtu = devinfo->max_rx_pktlen - NIX_L2_OVERHEAD;
153 devinfo->min_mtu = devinfo->min_rx_bufsize - NIX_L2_OVERHEAD;
155 devinfo->rx_offload_capa = dev->rx_offload_capa;
156 devinfo->tx_offload_capa = dev->tx_offload_capa;
157 devinfo->rx_queue_offload_capa = 0;
158 devinfo->tx_queue_offload_capa = 0;
160 devinfo->reta_size = dev->rss_info.rss_size;
161 devinfo->hash_key_size = NIX_HASH_KEY_SIZE;
162 devinfo->flow_type_rss_offloads = NIX_RSS_OFFLOAD;
164 devinfo->default_rxconf = (struct rte_eth_rxconf) {
169 devinfo->default_txconf = (struct rte_eth_txconf) {
173 devinfo->rx_desc_lim = (struct rte_eth_desc_lim) {
174 .nb_max = UINT16_MAX,
175 .nb_min = NIX_RX_MIN_DESC,
176 .nb_align = NIX_RX_MIN_DESC_ALIGN,
177 .nb_seg_max = NIX_RX_NB_SEG_MAX,
178 .nb_mtu_seg_max = NIX_RX_NB_SEG_MAX,
180 devinfo->rx_desc_lim.nb_max =
181 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,
182 NIX_RX_MIN_DESC_ALIGN);
184 devinfo->tx_desc_lim = (struct rte_eth_desc_lim) {
185 .nb_max = UINT16_MAX,
188 .nb_seg_max = NIX_TX_NB_SEG_MAX,
189 .nb_mtu_seg_max = NIX_TX_NB_SEG_MAX,
192 /* Auto negotiation disabled */
193 devinfo->speed_capa = ETH_LINK_SPEED_FIXED;
194 devinfo->speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
195 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
196 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
198 devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
199 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;