1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_ethdev.h>
6 #include <rte_mbuf_pool_ops.h>
8 #include "otx2_ethdev.h"
11 otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
13 uint32_t buffsz, frame_size = mtu + NIX_L2_OVERHEAD;
14 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
15 struct rte_eth_dev_data *data = eth_dev->data;
16 struct otx2_mbox *mbox = dev->mbox;
17 struct nix_frs_cfg *req;
20 if (dev->configured && otx2_ethdev_is_ptp_en(dev))
21 frame_size += NIX_TIMESYNC_RX_OFFSET;
23 /* Check if MTU is within the allowed range */
24 if (frame_size < NIX_MIN_FRS || frame_size > NIX_MAX_FRS)
27 buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
29 /* Refuse MTU that requires the support of scattered packets
30 * when this feature has not been enabled before.
32 if (data->dev_started && frame_size > buffsz &&
33 !(dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER))
36 /* Check <seg size> * <max_seg> >= max_frame */
37 if ((dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER) &&
38 (frame_size > buffsz * NIX_RX_NB_SEG_MAX))
41 req = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);
42 req->update_smq = true;
43 if (otx2_dev_is_sdp(dev))
45 /* FRS HW config should exclude FCS but include NPC VTAG insert size */
46 req->maxlen = frame_size - RTE_ETHER_CRC_LEN + NIX_MAX_VTAG_ACT_SIZE;
48 rc = otx2_mbox_process(mbox);
52 /* Now just update Rx MAXLEN */
53 req = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);
54 req->maxlen = frame_size - RTE_ETHER_CRC_LEN;
55 if (otx2_dev_is_sdp(dev))
58 rc = otx2_mbox_process(mbox);
62 if (mtu > RTE_ETHER_MTU)
63 dev->rx_offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
65 dev->rx_offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
71 otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev)
73 struct rte_eth_dev_data *data = eth_dev->data;
74 struct otx2_eth_rxq *rxq;
77 rxq = data->rx_queues[0];
79 /* Setup scatter mode if needed by jumbo */
80 otx2_nix_enable_mseg_on_jumbo(rxq);
82 rc = otx2_nix_mtu_set(eth_dev, data->mtu);
84 otx2_err("Failed to set default MTU size %d", rc);
90 nix_cgx_promisc_config(struct rte_eth_dev *eth_dev, int en)
92 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
93 struct otx2_mbox *mbox = dev->mbox;
95 if (otx2_dev_is_vf_or_sdp(dev))
99 otx2_mbox_alloc_msg_cgx_promisc_enable(mbox);
101 otx2_mbox_alloc_msg_cgx_promisc_disable(mbox);
103 otx2_mbox_process(mbox);
107 otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en)
109 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
110 struct otx2_mbox *mbox = dev->mbox;
111 struct nix_rx_mode *req;
113 if (otx2_dev_is_vf(dev))
116 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
119 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
121 otx2_mbox_process(mbox);
122 eth_dev->data->promiscuous = en;
123 otx2_nix_vlan_update_promisc(eth_dev, en);
127 otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev)
129 otx2_nix_promisc_config(eth_dev, 1);
130 nix_cgx_promisc_config(eth_dev, 1);
136 otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev)
138 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
139 otx2_nix_promisc_config(eth_dev, dev->dmac_filter_enable);
140 nix_cgx_promisc_config(eth_dev, 0);
141 dev->dmac_filter_enable = false;
147 nix_allmulticast_config(struct rte_eth_dev *eth_dev, int en)
149 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
150 struct otx2_mbox *mbox = dev->mbox;
151 struct nix_rx_mode *req;
153 if (otx2_dev_is_vf(dev))
156 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
159 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_ALLMULTI;
160 else if (eth_dev->data->promiscuous)
161 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
163 otx2_mbox_process(mbox);
167 otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev)
169 nix_allmulticast_config(eth_dev, 1);
175 otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev)
177 nix_allmulticast_config(eth_dev, 0);
183 otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
184 struct rte_eth_rxq_info *qinfo)
186 struct otx2_eth_rxq *rxq;
188 rxq = eth_dev->data->rx_queues[queue_id];
190 qinfo->mp = rxq->pool;
191 qinfo->scattered_rx = eth_dev->data->scattered_rx;
192 qinfo->nb_desc = rxq->qconf.nb_desc;
194 qinfo->conf.rx_free_thresh = 0;
195 qinfo->conf.rx_drop_en = 0;
196 qinfo->conf.rx_deferred_start = 0;
197 qinfo->conf.offloads = rxq->offloads;
201 otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
202 struct rte_eth_txq_info *qinfo)
204 struct otx2_eth_txq *txq;
206 txq = eth_dev->data->tx_queues[queue_id];
208 qinfo->nb_desc = txq->qconf.nb_desc;
210 qinfo->conf.tx_thresh.pthresh = 0;
211 qinfo->conf.tx_thresh.hthresh = 0;
212 qinfo->conf.tx_thresh.wthresh = 0;
214 qinfo->conf.tx_free_thresh = 0;
215 qinfo->conf.tx_rs_thresh = 0;
216 qinfo->conf.offloads = txq->offloads;
217 qinfo->conf.tx_deferred_start = 0;
221 otx2_rx_burst_mode_get(struct rte_eth_dev *eth_dev,
222 __rte_unused uint16_t queue_id,
223 struct rte_eth_burst_mode *mode)
225 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
226 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
227 const struct burst_info {
230 } rx_offload_map[] = {
231 {NIX_RX_OFFLOAD_RSS_F, "RSS,"},
232 {NIX_RX_OFFLOAD_PTYPE_F, " Ptype,"},
233 {NIX_RX_OFFLOAD_CHECKSUM_F, " Checksum,"},
234 {NIX_RX_OFFLOAD_VLAN_STRIP_F, " VLAN Strip,"},
235 {NIX_RX_OFFLOAD_MARK_UPDATE_F, " Mark Update,"},
236 {NIX_RX_OFFLOAD_TSTAMP_F, " Timestamp,"},
237 {NIX_RX_MULTI_SEG_F, " Scattered,"}
239 static const char *const burst_mode[] = {"Vector Neon, Rx Offloads:",
240 "Scalar, Rx Offloads:"
244 /* Update burst mode info */
245 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
252 /* Update Rx offload info */
253 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
254 if (dev->rx_offload_flags & rx_offload_map[i].flags) {
255 rc = rte_strscpy(mode->info + bytes,
256 rx_offload_map[i].output,
270 otx2_tx_burst_mode_get(struct rte_eth_dev *eth_dev,
271 __rte_unused uint16_t queue_id,
272 struct rte_eth_burst_mode *mode)
274 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
275 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
276 const struct burst_info {
279 } tx_offload_map[] = {
280 {NIX_TX_OFFLOAD_L3_L4_CSUM_F, " Inner L3/L4 csum,"},
281 {NIX_TX_OFFLOAD_OL3_OL4_CSUM_F, " Outer L3/L4 csum,"},
282 {NIX_TX_OFFLOAD_VLAN_QINQ_F, " VLAN Insertion,"},
283 {NIX_TX_OFFLOAD_MBUF_NOFF_F, " MBUF free disable,"},
284 {NIX_TX_OFFLOAD_TSTAMP_F, " Timestamp,"},
285 {NIX_TX_OFFLOAD_TSO_F, " TSO,"},
286 {NIX_TX_MULTI_SEG_F, " Scattered,"}
288 static const char *const burst_mode[] = {"Vector Neon, Tx Offloads:",
289 "Scalar, Tx Offloads:"
293 /* Update burst mode info */
294 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
301 /* Update Tx offload info */
302 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
303 if (dev->tx_offload_flags & tx_offload_map[i].flags) {
304 rc = rte_strscpy(mode->info + bytes,
305 tx_offload_map[i].output,
319 nix_rx_head_tail_get(struct otx2_eth_dev *dev,
320 uint32_t *head, uint32_t *tail, uint16_t queue_idx)
324 if (head == NULL || tail == NULL)
327 reg = (((uint64_t)queue_idx) << 32);
328 val = otx2_atomic64_add_nosync(reg, (int64_t *)
329 (dev->base + NIX_LF_CQ_OP_STATUS));
330 if (val & (OP_ERR | CQ_ERR))
333 *tail = (uint32_t)(val & 0xFFFFF);
334 *head = (uint32_t)((val >> 20) & 0xFFFFF);
338 otx2_nix_rx_queue_count(void *rx_queue)
340 struct otx2_eth_rxq *rxq = rx_queue;
341 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(rxq->eth_dev);
344 nix_rx_head_tail_get(dev, &head, &tail, rxq->rq);
345 return (tail - head) % rxq->qlen;
349 nix_offset_has_packet(uint32_t head, uint32_t tail, uint16_t offset)
351 /* Check given offset(queue index) has packet filled by HW */
352 if (tail > head && offset <= tail && offset >= head)
354 /* Wrap around case */
355 if (head > tail && (offset >= head || offset <= tail))
362 otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset)
364 struct otx2_eth_rxq *rxq = rx_queue;
367 if (rxq->qlen <= offset)
370 nix_rx_head_tail_get(otx2_eth_pmd_priv(rxq->eth_dev),
371 &head, &tail, rxq->rq);
373 if (nix_offset_has_packet(head, tail, offset))
374 return RTE_ETH_RX_DESC_DONE;
376 return RTE_ETH_RX_DESC_AVAIL;
380 nix_tx_head_tail_get(struct otx2_eth_dev *dev,
381 uint32_t *head, uint32_t *tail, uint16_t queue_idx)
385 if (head == NULL || tail == NULL)
388 reg = (((uint64_t)queue_idx) << 32);
389 val = otx2_atomic64_add_nosync(reg, (int64_t *)
390 (dev->base + NIX_LF_SQ_OP_STATUS));
394 *tail = (uint32_t)((val >> 28) & 0x3F);
395 *head = (uint32_t)((val >> 20) & 0x3F);
399 otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset)
401 struct otx2_eth_txq *txq = tx_queue;
404 if (txq->qconf.nb_desc <= offset)
407 nix_tx_head_tail_get(txq->dev, &head, &tail, txq->sq);
409 if (nix_offset_has_packet(head, tail, offset))
410 return RTE_ETH_TX_DESC_DONE;
412 return RTE_ETH_TX_DESC_FULL;
415 /* It is a NOP for octeontx2 as HW frees the buffer on xmit */
417 otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt)
420 RTE_SET_USED(free_cnt);
426 otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
429 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
430 int rc = (int)fw_size;
432 if (fw_size > sizeof(dev->mkex_pfl_name))
433 rc = sizeof(dev->mkex_pfl_name);
435 rc = strlcpy(fw_version, (char *)dev->mkex_pfl_name, rc);
437 rc += 1; /* Add the size of '\0' */
438 if (fw_size < (size_t)rc)
445 otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool)
447 RTE_SET_USED(eth_dev);
449 if (!strcmp(pool, rte_mbuf_platform_mempool_ops()))
456 otx2_nix_dev_flow_ops_get(struct rte_eth_dev *eth_dev __rte_unused,
457 const struct rte_flow_ops **ops)
459 *ops = &otx2_flow_ops;
463 static struct cgx_fw_data *
464 nix_get_fwdata(struct otx2_eth_dev *dev)
466 struct otx2_mbox *mbox = dev->mbox;
467 struct cgx_fw_data *rsp = NULL;
470 otx2_mbox_alloc_msg_cgx_get_aux_link_info(mbox);
472 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
474 otx2_err("Failed to get fw data: %d", rc);
482 otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
483 struct rte_eth_dev_module_info *modinfo)
485 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
486 struct cgx_fw_data *rsp;
488 rsp = nix_get_fwdata(dev);
492 modinfo->type = rsp->fwdata.sfp_eeprom.sff_id;
493 modinfo->eeprom_len = SFP_EEPROM_SIZE;
499 otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
500 struct rte_dev_eeprom_info *info)
502 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
503 struct cgx_fw_data *rsp;
505 if (info->offset + info->length > SFP_EEPROM_SIZE)
508 rsp = nix_get_fwdata(dev);
512 otx2_mbox_memcpy(info->data, rsp->fwdata.sfp_eeprom.buf + info->offset,
519 otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
521 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
522 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
524 devinfo->min_rx_bufsize = NIX_MIN_FRS;
525 devinfo->max_rx_pktlen = NIX_MAX_FRS;
526 devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;
527 devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
528 devinfo->max_mac_addrs = dev->max_mac_entries;
529 devinfo->max_vfs = pci_dev->max_vfs;
530 devinfo->max_mtu = devinfo->max_rx_pktlen - NIX_L2_OVERHEAD;
531 devinfo->min_mtu = devinfo->min_rx_bufsize - NIX_L2_OVERHEAD;
532 if (dev->configured && otx2_ethdev_is_ptp_en(dev)) {
533 devinfo->max_mtu -= NIX_TIMESYNC_RX_OFFSET;
534 devinfo->min_mtu -= NIX_TIMESYNC_RX_OFFSET;
535 devinfo->max_rx_pktlen -= NIX_TIMESYNC_RX_OFFSET;
538 devinfo->rx_offload_capa = dev->rx_offload_capa;
539 devinfo->tx_offload_capa = dev->tx_offload_capa;
540 devinfo->rx_queue_offload_capa = 0;
541 devinfo->tx_queue_offload_capa = 0;
543 devinfo->reta_size = dev->rss_info.rss_size;
544 devinfo->hash_key_size = NIX_HASH_KEY_SIZE;
545 devinfo->flow_type_rss_offloads = NIX_RSS_OFFLOAD;
547 devinfo->default_rxconf = (struct rte_eth_rxconf) {
552 devinfo->default_txconf = (struct rte_eth_txconf) {
556 devinfo->default_rxportconf = (struct rte_eth_dev_portconf) {
557 .ring_size = NIX_RX_DEFAULT_RING_SZ,
560 devinfo->rx_desc_lim = (struct rte_eth_desc_lim) {
561 .nb_max = UINT16_MAX,
562 .nb_min = NIX_RX_MIN_DESC,
563 .nb_align = NIX_RX_MIN_DESC_ALIGN,
564 .nb_seg_max = NIX_RX_NB_SEG_MAX,
565 .nb_mtu_seg_max = NIX_RX_NB_SEG_MAX,
567 devinfo->rx_desc_lim.nb_max =
568 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,
569 NIX_RX_MIN_DESC_ALIGN);
571 devinfo->tx_desc_lim = (struct rte_eth_desc_lim) {
572 .nb_max = UINT16_MAX,
575 .nb_seg_max = NIX_TX_NB_SEG_MAX,
576 .nb_mtu_seg_max = NIX_TX_NB_SEG_MAX,
579 /* Auto negotiation disabled */
580 devinfo->speed_capa = ETH_LINK_SPEED_FIXED;
581 if (!otx2_dev_is_vf_or_sdp(dev) && !otx2_dev_is_lbk(dev)) {
582 devinfo->speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
583 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G;
585 /* 50G and 100G to be supported for board version C0
588 if (!otx2_dev_is_Ax(dev))
589 devinfo->speed_capa |= ETH_LINK_SPEED_50G |
593 devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
594 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;