1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_mbuf_pool_ops.h>
7 #include "otx2_ethdev.h"
10 otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
12 uint32_t buffsz, frame_size = mtu + NIX_L2_OVERHEAD;
13 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
14 struct rte_eth_dev_data *data = eth_dev->data;
15 struct otx2_mbox *mbox = dev->mbox;
16 struct nix_frs_cfg *req;
19 /* Check if MTU is within the allowed range */
20 if (frame_size < NIX_MIN_FRS || frame_size > NIX_MAX_FRS)
23 buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
25 /* Refuse MTU that requires the support of scattered packets
26 * when this feature has not been enabled before.
28 if (data->dev_started && frame_size > buffsz &&
29 !(dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER))
32 /* Check <seg size> * <max_seg> >= max_frame */
33 if ((dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER) &&
34 (frame_size > buffsz * NIX_RX_NB_SEG_MAX))
37 req = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);
38 req->update_smq = true;
39 /* FRS HW config should exclude FCS but include NPC VTAG insert size */
40 req->maxlen = frame_size - RTE_ETHER_CRC_LEN + NIX_MAX_VTAG_ACT_SIZE;
42 rc = otx2_mbox_process(mbox);
46 /* Now just update Rx MAXLEN */
47 req = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);
48 req->maxlen = frame_size - RTE_ETHER_CRC_LEN;
50 rc = otx2_mbox_process(mbox);
54 if (frame_size > RTE_ETHER_MAX_LEN)
55 dev->rx_offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
57 dev->rx_offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
59 /* Update max_rx_pkt_len */
60 data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
66 otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev)
68 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
69 struct rte_eth_dev_data *data = eth_dev->data;
70 struct rte_pktmbuf_pool_private *mbp_priv;
71 struct otx2_eth_rxq *rxq;
76 /* Get rx buffer size */
77 rxq = data->rx_queues[0];
78 mbp_priv = rte_mempool_get_priv(rxq->pool);
79 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
81 /* Setup scatter mode if needed by jumbo */
82 if (data->dev_conf.rxmode.max_rx_pkt_len > buffsz)
83 dev->rx_offloads |= DEV_RX_OFFLOAD_SCATTER;
85 /* Setup MTU based on max_rx_pkt_len */
86 mtu = data->dev_conf.rxmode.max_rx_pkt_len - NIX_L2_OVERHEAD;
88 rc = otx2_nix_mtu_set(eth_dev, mtu);
90 otx2_err("Failed to set default MTU size %d", rc);
96 nix_cgx_promisc_config(struct rte_eth_dev *eth_dev, int en)
98 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
99 struct otx2_mbox *mbox = dev->mbox;
101 if (otx2_dev_is_vf(dev))
105 otx2_mbox_alloc_msg_cgx_promisc_enable(mbox);
107 otx2_mbox_alloc_msg_cgx_promisc_disable(mbox);
109 otx2_mbox_process(mbox);
113 otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en)
115 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
116 struct otx2_mbox *mbox = dev->mbox;
117 struct nix_rx_mode *req;
119 if (otx2_dev_is_vf(dev))
122 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
125 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
127 otx2_mbox_process(mbox);
128 eth_dev->data->promiscuous = en;
129 otx2_nix_vlan_update_promisc(eth_dev, en);
133 otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev)
135 otx2_nix_promisc_config(eth_dev, 1);
136 nix_cgx_promisc_config(eth_dev, 1);
142 otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev)
144 otx2_nix_promisc_config(eth_dev, 0);
145 nix_cgx_promisc_config(eth_dev, 0);
151 nix_allmulticast_config(struct rte_eth_dev *eth_dev, int en)
153 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
154 struct otx2_mbox *mbox = dev->mbox;
155 struct nix_rx_mode *req;
157 if (otx2_dev_is_vf(dev))
160 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
163 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_ALLMULTI;
164 else if (eth_dev->data->promiscuous)
165 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
167 otx2_mbox_process(mbox);
171 otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev)
173 nix_allmulticast_config(eth_dev, 1);
177 otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev)
179 nix_allmulticast_config(eth_dev, 0);
183 otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
184 struct rte_eth_rxq_info *qinfo)
186 struct otx2_eth_rxq *rxq;
188 rxq = eth_dev->data->rx_queues[queue_id];
190 qinfo->mp = rxq->pool;
191 qinfo->scattered_rx = eth_dev->data->scattered_rx;
192 qinfo->nb_desc = rxq->qconf.nb_desc;
194 qinfo->conf.rx_free_thresh = 0;
195 qinfo->conf.rx_drop_en = 0;
196 qinfo->conf.rx_deferred_start = 0;
197 qinfo->conf.offloads = rxq->offloads;
201 otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
202 struct rte_eth_txq_info *qinfo)
204 struct otx2_eth_txq *txq;
206 txq = eth_dev->data->tx_queues[queue_id];
208 qinfo->nb_desc = txq->qconf.nb_desc;
210 qinfo->conf.tx_thresh.pthresh = 0;
211 qinfo->conf.tx_thresh.hthresh = 0;
212 qinfo->conf.tx_thresh.wthresh = 0;
214 qinfo->conf.tx_free_thresh = 0;
215 qinfo->conf.tx_rs_thresh = 0;
216 qinfo->conf.offloads = txq->offloads;
217 qinfo->conf.tx_deferred_start = 0;
221 nix_rx_head_tail_get(struct otx2_eth_dev *dev,
222 uint32_t *head, uint32_t *tail, uint16_t queue_idx)
226 if (head == NULL || tail == NULL)
229 reg = (((uint64_t)queue_idx) << 32);
230 val = otx2_atomic64_add_nosync(reg, (int64_t *)
231 (dev->base + NIX_LF_CQ_OP_STATUS));
232 if (val & (OP_ERR | CQ_ERR))
235 *tail = (uint32_t)(val & 0xFFFFF);
236 *head = (uint32_t)((val >> 20) & 0xFFFFF);
240 otx2_nix_rx_queue_count(struct rte_eth_dev *eth_dev, uint16_t queue_idx)
242 struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[queue_idx];
243 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
246 nix_rx_head_tail_get(dev, &head, &tail, queue_idx);
247 return (tail - head) % rxq->qlen;
251 nix_offset_has_packet(uint32_t head, uint32_t tail, uint16_t offset)
253 /* Check given offset(queue index) has packet filled by HW */
254 if (tail > head && offset <= tail && offset >= head)
256 /* Wrap around case */
257 if (head > tail && (offset >= head || offset <= tail))
264 otx2_nix_rx_descriptor_done(void *rx_queue, uint16_t offset)
266 struct otx2_eth_rxq *rxq = rx_queue;
269 nix_rx_head_tail_get(otx2_eth_pmd_priv(rxq->eth_dev),
270 &head, &tail, rxq->rq);
272 return nix_offset_has_packet(head, tail, offset);
276 otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset)
278 struct otx2_eth_rxq *rxq = rx_queue;
281 if (rxq->qlen >= offset)
284 nix_rx_head_tail_get(otx2_eth_pmd_priv(rxq->eth_dev),
285 &head, &tail, rxq->rq);
287 if (nix_offset_has_packet(head, tail, offset))
288 return RTE_ETH_RX_DESC_DONE;
290 return RTE_ETH_RX_DESC_AVAIL;
293 /* It is a NOP for octeontx2 as HW frees the buffer on xmit */
295 otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt)
298 RTE_SET_USED(free_cnt);
304 otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
307 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
308 int rc = (int)fw_size;
310 if (fw_size > sizeof(dev->mkex_pfl_name))
311 rc = sizeof(dev->mkex_pfl_name);
313 rc = strlcpy(fw_version, (char *)dev->mkex_pfl_name, rc);
315 rc += 1; /* Add the size of '\0' */
316 if (fw_size < (uint32_t)rc)
323 otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool)
325 RTE_SET_USED(eth_dev);
327 if (!strcmp(pool, rte_mbuf_platform_mempool_ops()))
334 otx2_nix_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
335 enum rte_filter_type filter_type,
336 enum rte_filter_op filter_op, void *arg)
338 RTE_SET_USED(eth_dev);
340 if (filter_type != RTE_ETH_FILTER_GENERIC) {
341 otx2_err("Unsupported filter type %d", filter_type);
345 if (filter_op == RTE_ETH_FILTER_GET) {
346 *(const void **)arg = &otx2_flow_ops;
350 otx2_err("Invalid filter_op %d", filter_op);
354 static struct cgx_fw_data *
355 nix_get_fwdata(struct otx2_eth_dev *dev)
357 struct otx2_mbox *mbox = dev->mbox;
358 struct cgx_fw_data *rsp = NULL;
361 otx2_mbox_alloc_msg_cgx_get_aux_link_info(mbox);
363 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
365 otx2_err("Failed to get fw data: %d", rc);
373 otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
374 struct rte_eth_dev_module_info *modinfo)
376 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
377 struct cgx_fw_data *rsp;
379 rsp = nix_get_fwdata(dev);
383 modinfo->type = rsp->fwdata.sfp_eeprom.sff_id;
384 modinfo->eeprom_len = SFP_EEPROM_SIZE;
390 otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
391 struct rte_dev_eeprom_info *info)
393 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
394 struct cgx_fw_data *rsp;
396 if (!info->data || !info->length ||
397 (info->offset + info->length > SFP_EEPROM_SIZE))
400 rsp = nix_get_fwdata(dev);
404 otx2_mbox_memcpy(info->data, rsp->fwdata.sfp_eeprom.buf + info->offset,
411 otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
413 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
414 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
416 devinfo->min_rx_bufsize = NIX_MIN_FRS;
417 devinfo->max_rx_pktlen = NIX_MAX_FRS;
418 devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;
419 devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
420 devinfo->max_mac_addrs = dev->max_mac_entries;
421 devinfo->max_vfs = pci_dev->max_vfs;
422 devinfo->max_mtu = devinfo->max_rx_pktlen - NIX_L2_OVERHEAD;
423 devinfo->min_mtu = devinfo->min_rx_bufsize - NIX_L2_OVERHEAD;
425 devinfo->rx_offload_capa = dev->rx_offload_capa;
426 devinfo->tx_offload_capa = dev->tx_offload_capa;
427 devinfo->rx_queue_offload_capa = 0;
428 devinfo->tx_queue_offload_capa = 0;
430 devinfo->reta_size = dev->rss_info.rss_size;
431 devinfo->hash_key_size = NIX_HASH_KEY_SIZE;
432 devinfo->flow_type_rss_offloads = NIX_RSS_OFFLOAD;
434 devinfo->default_rxconf = (struct rte_eth_rxconf) {
439 devinfo->default_txconf = (struct rte_eth_txconf) {
443 devinfo->default_rxportconf = (struct rte_eth_dev_portconf) {
444 .ring_size = NIX_RX_DEFAULT_RING_SZ,
447 devinfo->rx_desc_lim = (struct rte_eth_desc_lim) {
448 .nb_max = UINT16_MAX,
449 .nb_min = NIX_RX_MIN_DESC,
450 .nb_align = NIX_RX_MIN_DESC_ALIGN,
451 .nb_seg_max = NIX_RX_NB_SEG_MAX,
452 .nb_mtu_seg_max = NIX_RX_NB_SEG_MAX,
454 devinfo->rx_desc_lim.nb_max =
455 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,
456 NIX_RX_MIN_DESC_ALIGN);
458 devinfo->tx_desc_lim = (struct rte_eth_desc_lim) {
459 .nb_max = UINT16_MAX,
462 .nb_seg_max = NIX_TX_NB_SEG_MAX,
463 .nb_mtu_seg_max = NIX_TX_NB_SEG_MAX,
466 /* Auto negotiation disabled */
467 devinfo->speed_capa = ETH_LINK_SPEED_FIXED;
468 devinfo->speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
469 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
470 ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
472 devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
473 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;