1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_ethdev.h>
6 #include <rte_mbuf_pool_ops.h>
8 #include "otx2_ethdev.h"
11 otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
13 uint32_t buffsz, frame_size = mtu + NIX_L2_OVERHEAD;
14 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
15 struct rte_eth_dev_data *data = eth_dev->data;
16 struct otx2_mbox *mbox = dev->mbox;
17 struct nix_frs_cfg *req;
20 if (dev->configured && otx2_ethdev_is_ptp_en(dev))
21 frame_size += NIX_TIMESYNC_RX_OFFSET;
23 /* Check if MTU is within the allowed range */
24 if (frame_size < NIX_MIN_FRS || frame_size > NIX_MAX_FRS)
27 buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
29 /* Refuse MTU that requires the support of scattered packets
30 * when this feature has not been enabled before.
32 if (data->dev_started && frame_size > buffsz &&
33 !(dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER))
36 /* Check <seg size> * <max_seg> >= max_frame */
37 if ((dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER) &&
38 (frame_size > buffsz * NIX_RX_NB_SEG_MAX))
41 req = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);
42 req->update_smq = true;
43 if (otx2_dev_is_sdp(dev))
45 /* FRS HW config should exclude FCS but include NPC VTAG insert size */
46 req->maxlen = frame_size - RTE_ETHER_CRC_LEN + NIX_MAX_VTAG_ACT_SIZE;
48 rc = otx2_mbox_process(mbox);
52 /* Now just update Rx MAXLEN */
53 req = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);
54 req->maxlen = frame_size - RTE_ETHER_CRC_LEN;
55 if (otx2_dev_is_sdp(dev))
58 rc = otx2_mbox_process(mbox);
66 otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev)
68 struct rte_eth_dev_data *data = eth_dev->data;
69 struct otx2_eth_rxq *rxq;
72 rxq = data->rx_queues[0];
74 /* Setup scatter mode if needed by jumbo */
75 otx2_nix_enable_mseg_on_jumbo(rxq);
77 rc = otx2_nix_mtu_set(eth_dev, data->mtu);
79 otx2_err("Failed to set default MTU size %d", rc);
85 nix_cgx_promisc_config(struct rte_eth_dev *eth_dev, int en)
87 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
88 struct otx2_mbox *mbox = dev->mbox;
90 if (otx2_dev_is_vf_or_sdp(dev))
94 otx2_mbox_alloc_msg_cgx_promisc_enable(mbox);
96 otx2_mbox_alloc_msg_cgx_promisc_disable(mbox);
98 otx2_mbox_process(mbox);
102 otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en)
104 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
105 struct otx2_mbox *mbox = dev->mbox;
106 struct nix_rx_mode *req;
108 if (otx2_dev_is_vf(dev))
111 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
114 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
116 otx2_mbox_process(mbox);
117 eth_dev->data->promiscuous = en;
118 otx2_nix_vlan_update_promisc(eth_dev, en);
122 otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev)
124 otx2_nix_promisc_config(eth_dev, 1);
125 nix_cgx_promisc_config(eth_dev, 1);
131 otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev)
133 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
134 otx2_nix_promisc_config(eth_dev, dev->dmac_filter_enable);
135 nix_cgx_promisc_config(eth_dev, 0);
136 dev->dmac_filter_enable = false;
142 nix_allmulticast_config(struct rte_eth_dev *eth_dev, int en)
144 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
145 struct otx2_mbox *mbox = dev->mbox;
146 struct nix_rx_mode *req;
148 if (otx2_dev_is_vf(dev))
151 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
154 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_ALLMULTI;
155 else if (eth_dev->data->promiscuous)
156 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
158 otx2_mbox_process(mbox);
162 otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev)
164 nix_allmulticast_config(eth_dev, 1);
170 otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev)
172 nix_allmulticast_config(eth_dev, 0);
178 otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
179 struct rte_eth_rxq_info *qinfo)
181 struct otx2_eth_rxq *rxq;
183 rxq = eth_dev->data->rx_queues[queue_id];
185 qinfo->mp = rxq->pool;
186 qinfo->scattered_rx = eth_dev->data->scattered_rx;
187 qinfo->nb_desc = rxq->qconf.nb_desc;
189 qinfo->conf.rx_free_thresh = 0;
190 qinfo->conf.rx_drop_en = 0;
191 qinfo->conf.rx_deferred_start = 0;
192 qinfo->conf.offloads = rxq->offloads;
196 otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
197 struct rte_eth_txq_info *qinfo)
199 struct otx2_eth_txq *txq;
201 txq = eth_dev->data->tx_queues[queue_id];
203 qinfo->nb_desc = txq->qconf.nb_desc;
205 qinfo->conf.tx_thresh.pthresh = 0;
206 qinfo->conf.tx_thresh.hthresh = 0;
207 qinfo->conf.tx_thresh.wthresh = 0;
209 qinfo->conf.tx_free_thresh = 0;
210 qinfo->conf.tx_rs_thresh = 0;
211 qinfo->conf.offloads = txq->offloads;
212 qinfo->conf.tx_deferred_start = 0;
216 otx2_rx_burst_mode_get(struct rte_eth_dev *eth_dev,
217 __rte_unused uint16_t queue_id,
218 struct rte_eth_burst_mode *mode)
220 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
221 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
222 const struct burst_info {
225 } rx_offload_map[] = {
226 {NIX_RX_OFFLOAD_RSS_F, "RSS,"},
227 {NIX_RX_OFFLOAD_PTYPE_F, " Ptype,"},
228 {NIX_RX_OFFLOAD_CHECKSUM_F, " Checksum,"},
229 {NIX_RX_OFFLOAD_VLAN_STRIP_F, " VLAN Strip,"},
230 {NIX_RX_OFFLOAD_MARK_UPDATE_F, " Mark Update,"},
231 {NIX_RX_OFFLOAD_TSTAMP_F, " Timestamp,"},
232 {NIX_RX_MULTI_SEG_F, " Scattered,"}
234 static const char *const burst_mode[] = {"Vector Neon, Rx Offloads:",
235 "Scalar, Rx Offloads:"
239 /* Update burst mode info */
240 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
247 /* Update Rx offload info */
248 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
249 if (dev->rx_offload_flags & rx_offload_map[i].flags) {
250 rc = rte_strscpy(mode->info + bytes,
251 rx_offload_map[i].output,
265 otx2_tx_burst_mode_get(struct rte_eth_dev *eth_dev,
266 __rte_unused uint16_t queue_id,
267 struct rte_eth_burst_mode *mode)
269 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
270 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
271 const struct burst_info {
274 } tx_offload_map[] = {
275 {NIX_TX_OFFLOAD_L3_L4_CSUM_F, " Inner L3/L4 csum,"},
276 {NIX_TX_OFFLOAD_OL3_OL4_CSUM_F, " Outer L3/L4 csum,"},
277 {NIX_TX_OFFLOAD_VLAN_QINQ_F, " VLAN Insertion,"},
278 {NIX_TX_OFFLOAD_MBUF_NOFF_F, " MBUF free disable,"},
279 {NIX_TX_OFFLOAD_TSTAMP_F, " Timestamp,"},
280 {NIX_TX_OFFLOAD_TSO_F, " TSO,"},
281 {NIX_TX_MULTI_SEG_F, " Scattered,"}
283 static const char *const burst_mode[] = {"Vector Neon, Tx Offloads:",
284 "Scalar, Tx Offloads:"
288 /* Update burst mode info */
289 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
296 /* Update Tx offload info */
297 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
298 if (dev->tx_offload_flags & tx_offload_map[i].flags) {
299 rc = rte_strscpy(mode->info + bytes,
300 tx_offload_map[i].output,
314 nix_rx_head_tail_get(struct otx2_eth_dev *dev,
315 uint32_t *head, uint32_t *tail, uint16_t queue_idx)
319 if (head == NULL || tail == NULL)
322 reg = (((uint64_t)queue_idx) << 32);
323 val = otx2_atomic64_add_nosync(reg, (int64_t *)
324 (dev->base + NIX_LF_CQ_OP_STATUS));
325 if (val & (OP_ERR | CQ_ERR))
328 *tail = (uint32_t)(val & 0xFFFFF);
329 *head = (uint32_t)((val >> 20) & 0xFFFFF);
333 otx2_nix_rx_queue_count(void *rx_queue)
335 struct otx2_eth_rxq *rxq = rx_queue;
336 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(rxq->eth_dev);
339 nix_rx_head_tail_get(dev, &head, &tail, rxq->rq);
340 return (tail - head) % rxq->qlen;
344 nix_offset_has_packet(uint32_t head, uint32_t tail, uint16_t offset)
346 /* Check given offset(queue index) has packet filled by HW */
347 if (tail > head && offset <= tail && offset >= head)
349 /* Wrap around case */
350 if (head > tail && (offset >= head || offset <= tail))
357 otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset)
359 struct otx2_eth_rxq *rxq = rx_queue;
362 if (rxq->qlen <= offset)
365 nix_rx_head_tail_get(otx2_eth_pmd_priv(rxq->eth_dev),
366 &head, &tail, rxq->rq);
368 if (nix_offset_has_packet(head, tail, offset))
369 return RTE_ETH_RX_DESC_DONE;
371 return RTE_ETH_RX_DESC_AVAIL;
375 nix_tx_head_tail_get(struct otx2_eth_dev *dev,
376 uint32_t *head, uint32_t *tail, uint16_t queue_idx)
380 if (head == NULL || tail == NULL)
383 reg = (((uint64_t)queue_idx) << 32);
384 val = otx2_atomic64_add_nosync(reg, (int64_t *)
385 (dev->base + NIX_LF_SQ_OP_STATUS));
389 *tail = (uint32_t)((val >> 28) & 0x3F);
390 *head = (uint32_t)((val >> 20) & 0x3F);
394 otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset)
396 struct otx2_eth_txq *txq = tx_queue;
399 if (txq->qconf.nb_desc <= offset)
402 nix_tx_head_tail_get(txq->dev, &head, &tail, txq->sq);
404 if (nix_offset_has_packet(head, tail, offset))
405 return RTE_ETH_TX_DESC_DONE;
407 return RTE_ETH_TX_DESC_FULL;
410 /* It is a NOP for octeontx2 as HW frees the buffer on xmit */
412 otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt)
415 RTE_SET_USED(free_cnt);
421 otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
424 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
425 int rc = (int)fw_size;
427 if (fw_size > sizeof(dev->mkex_pfl_name))
428 rc = sizeof(dev->mkex_pfl_name);
430 rc = strlcpy(fw_version, (char *)dev->mkex_pfl_name, rc);
432 rc += 1; /* Add the size of '\0' */
433 if (fw_size < (size_t)rc)
440 otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool)
442 RTE_SET_USED(eth_dev);
444 if (!strcmp(pool, rte_mbuf_platform_mempool_ops()))
451 otx2_nix_dev_flow_ops_get(struct rte_eth_dev *eth_dev __rte_unused,
452 const struct rte_flow_ops **ops)
454 *ops = &otx2_flow_ops;
458 static struct cgx_fw_data *
459 nix_get_fwdata(struct otx2_eth_dev *dev)
461 struct otx2_mbox *mbox = dev->mbox;
462 struct cgx_fw_data *rsp = NULL;
465 otx2_mbox_alloc_msg_cgx_get_aux_link_info(mbox);
467 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
469 otx2_err("Failed to get fw data: %d", rc);
477 otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
478 struct rte_eth_dev_module_info *modinfo)
480 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
481 struct cgx_fw_data *rsp;
483 rsp = nix_get_fwdata(dev);
487 modinfo->type = rsp->fwdata.sfp_eeprom.sff_id;
488 modinfo->eeprom_len = SFP_EEPROM_SIZE;
494 otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
495 struct rte_dev_eeprom_info *info)
497 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
498 struct cgx_fw_data *rsp;
500 if (info->offset + info->length > SFP_EEPROM_SIZE)
503 rsp = nix_get_fwdata(dev);
507 otx2_mbox_memcpy(info->data, rsp->fwdata.sfp_eeprom.buf + info->offset,
514 otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
516 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
517 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
519 devinfo->min_rx_bufsize = NIX_MIN_FRS;
520 devinfo->max_rx_pktlen = NIX_MAX_FRS;
521 devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;
522 devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
523 devinfo->max_mac_addrs = dev->max_mac_entries;
524 devinfo->max_vfs = pci_dev->max_vfs;
525 devinfo->max_mtu = devinfo->max_rx_pktlen - NIX_L2_OVERHEAD;
526 devinfo->min_mtu = devinfo->min_rx_bufsize - NIX_L2_OVERHEAD;
527 if (dev->configured && otx2_ethdev_is_ptp_en(dev)) {
528 devinfo->max_mtu -= NIX_TIMESYNC_RX_OFFSET;
529 devinfo->min_mtu -= NIX_TIMESYNC_RX_OFFSET;
530 devinfo->max_rx_pktlen -= NIX_TIMESYNC_RX_OFFSET;
533 devinfo->rx_offload_capa = dev->rx_offload_capa;
534 devinfo->tx_offload_capa = dev->tx_offload_capa;
535 devinfo->rx_queue_offload_capa = 0;
536 devinfo->tx_queue_offload_capa = 0;
538 devinfo->reta_size = dev->rss_info.rss_size;
539 devinfo->hash_key_size = NIX_HASH_KEY_SIZE;
540 devinfo->flow_type_rss_offloads = NIX_RSS_OFFLOAD;
542 devinfo->default_rxconf = (struct rte_eth_rxconf) {
547 devinfo->default_txconf = (struct rte_eth_txconf) {
551 devinfo->default_rxportconf = (struct rte_eth_dev_portconf) {
552 .ring_size = NIX_RX_DEFAULT_RING_SZ,
555 devinfo->rx_desc_lim = (struct rte_eth_desc_lim) {
556 .nb_max = UINT16_MAX,
557 .nb_min = NIX_RX_MIN_DESC,
558 .nb_align = NIX_RX_MIN_DESC_ALIGN,
559 .nb_seg_max = NIX_RX_NB_SEG_MAX,
560 .nb_mtu_seg_max = NIX_RX_NB_SEG_MAX,
562 devinfo->rx_desc_lim.nb_max =
563 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,
564 NIX_RX_MIN_DESC_ALIGN);
566 devinfo->tx_desc_lim = (struct rte_eth_desc_lim) {
567 .nb_max = UINT16_MAX,
570 .nb_seg_max = NIX_TX_NB_SEG_MAX,
571 .nb_mtu_seg_max = NIX_TX_NB_SEG_MAX,
574 /* Auto negotiation disabled */
575 devinfo->speed_capa = ETH_LINK_SPEED_FIXED;
576 if (!otx2_dev_is_vf_or_sdp(dev) && !otx2_dev_is_lbk(dev)) {
577 devinfo->speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
578 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G;
580 /* 50G and 100G to be supported for board version C0
583 if (!otx2_dev_is_Ax(dev))
584 devinfo->speed_capa |= ETH_LINK_SPEED_50G |
588 devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
589 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;