1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_ethdev.h>
6 #include <rte_mbuf_pool_ops.h>
8 #include "otx2_ethdev.h"
11 otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
13 uint32_t buffsz, frame_size = mtu + NIX_L2_OVERHEAD;
14 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
15 struct rte_eth_dev_data *data = eth_dev->data;
16 struct otx2_mbox *mbox = dev->mbox;
17 struct nix_frs_cfg *req;
20 if (dev->configured && otx2_ethdev_is_ptp_en(dev))
21 frame_size += NIX_TIMESYNC_RX_OFFSET;
23 buffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
25 /* Refuse MTU that requires the support of scattered packets
26 * when this feature has not been enabled before.
28 if (data->dev_started && frame_size > buffsz &&
29 !(dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER))
32 /* Check <seg size> * <max_seg> >= max_frame */
33 if ((dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER) &&
34 (frame_size > buffsz * NIX_RX_NB_SEG_MAX))
37 req = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);
38 req->update_smq = true;
39 if (otx2_dev_is_sdp(dev))
41 /* FRS HW config should exclude FCS but include NPC VTAG insert size */
42 req->maxlen = frame_size - RTE_ETHER_CRC_LEN + NIX_MAX_VTAG_ACT_SIZE;
44 rc = otx2_mbox_process(mbox);
48 /* Now just update Rx MAXLEN */
49 req = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);
50 req->maxlen = frame_size - RTE_ETHER_CRC_LEN;
51 if (otx2_dev_is_sdp(dev))
54 rc = otx2_mbox_process(mbox);
62 otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev)
64 struct rte_eth_dev_data *data = eth_dev->data;
65 struct otx2_eth_rxq *rxq;
68 rxq = data->rx_queues[0];
70 /* Setup scatter mode if needed by jumbo */
71 otx2_nix_enable_mseg_on_jumbo(rxq);
73 rc = otx2_nix_mtu_set(eth_dev, data->mtu);
75 otx2_err("Failed to set default MTU size %d", rc);
81 nix_cgx_promisc_config(struct rte_eth_dev *eth_dev, int en)
83 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
84 struct otx2_mbox *mbox = dev->mbox;
86 if (otx2_dev_is_vf_or_sdp(dev))
90 otx2_mbox_alloc_msg_cgx_promisc_enable(mbox);
92 otx2_mbox_alloc_msg_cgx_promisc_disable(mbox);
94 otx2_mbox_process(mbox);
98 otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en)
100 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
101 struct otx2_mbox *mbox = dev->mbox;
102 struct nix_rx_mode *req;
104 if (otx2_dev_is_vf(dev))
107 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
110 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
112 otx2_mbox_process(mbox);
113 eth_dev->data->promiscuous = en;
114 otx2_nix_vlan_update_promisc(eth_dev, en);
118 otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev)
120 otx2_nix_promisc_config(eth_dev, 1);
121 nix_cgx_promisc_config(eth_dev, 1);
127 otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev)
129 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
130 otx2_nix_promisc_config(eth_dev, dev->dmac_filter_enable);
131 nix_cgx_promisc_config(eth_dev, 0);
132 dev->dmac_filter_enable = false;
138 nix_allmulticast_config(struct rte_eth_dev *eth_dev, int en)
140 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
141 struct otx2_mbox *mbox = dev->mbox;
142 struct nix_rx_mode *req;
144 if (otx2_dev_is_vf(dev))
147 req = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);
150 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_ALLMULTI;
151 else if (eth_dev->data->promiscuous)
152 req->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;
154 otx2_mbox_process(mbox);
158 otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev)
160 nix_allmulticast_config(eth_dev, 1);
166 otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev)
168 nix_allmulticast_config(eth_dev, 0);
174 otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
175 struct rte_eth_rxq_info *qinfo)
177 struct otx2_eth_rxq *rxq;
179 rxq = eth_dev->data->rx_queues[queue_id];
181 qinfo->mp = rxq->pool;
182 qinfo->scattered_rx = eth_dev->data->scattered_rx;
183 qinfo->nb_desc = rxq->qconf.nb_desc;
185 qinfo->conf.rx_free_thresh = 0;
186 qinfo->conf.rx_drop_en = 0;
187 qinfo->conf.rx_deferred_start = 0;
188 qinfo->conf.offloads = rxq->offloads;
192 otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,
193 struct rte_eth_txq_info *qinfo)
195 struct otx2_eth_txq *txq;
197 txq = eth_dev->data->tx_queues[queue_id];
199 qinfo->nb_desc = txq->qconf.nb_desc;
201 qinfo->conf.tx_thresh.pthresh = 0;
202 qinfo->conf.tx_thresh.hthresh = 0;
203 qinfo->conf.tx_thresh.wthresh = 0;
205 qinfo->conf.tx_free_thresh = 0;
206 qinfo->conf.tx_rs_thresh = 0;
207 qinfo->conf.offloads = txq->offloads;
208 qinfo->conf.tx_deferred_start = 0;
212 otx2_rx_burst_mode_get(struct rte_eth_dev *eth_dev,
213 __rte_unused uint16_t queue_id,
214 struct rte_eth_burst_mode *mode)
216 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
217 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
218 const struct burst_info {
221 } rx_offload_map[] = {
222 {NIX_RX_OFFLOAD_RSS_F, "RSS,"},
223 {NIX_RX_OFFLOAD_PTYPE_F, " Ptype,"},
224 {NIX_RX_OFFLOAD_CHECKSUM_F, " Checksum,"},
225 {NIX_RX_OFFLOAD_VLAN_STRIP_F, " VLAN Strip,"},
226 {NIX_RX_OFFLOAD_MARK_UPDATE_F, " Mark Update,"},
227 {NIX_RX_OFFLOAD_TSTAMP_F, " Timestamp,"},
228 {NIX_RX_MULTI_SEG_F, " Scattered,"}
230 static const char *const burst_mode[] = {"Vector Neon, Rx Offloads:",
231 "Scalar, Rx Offloads:"
235 /* Update burst mode info */
236 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
243 /* Update Rx offload info */
244 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
245 if (dev->rx_offload_flags & rx_offload_map[i].flags) {
246 rc = rte_strscpy(mode->info + bytes,
247 rx_offload_map[i].output,
261 otx2_tx_burst_mode_get(struct rte_eth_dev *eth_dev,
262 __rte_unused uint16_t queue_id,
263 struct rte_eth_burst_mode *mode)
265 ssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;
266 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
267 const struct burst_info {
270 } tx_offload_map[] = {
271 {NIX_TX_OFFLOAD_L3_L4_CSUM_F, " Inner L3/L4 csum,"},
272 {NIX_TX_OFFLOAD_OL3_OL4_CSUM_F, " Outer L3/L4 csum,"},
273 {NIX_TX_OFFLOAD_VLAN_QINQ_F, " VLAN Insertion,"},
274 {NIX_TX_OFFLOAD_MBUF_NOFF_F, " MBUF free disable,"},
275 {NIX_TX_OFFLOAD_TSTAMP_F, " Timestamp,"},
276 {NIX_TX_OFFLOAD_TSO_F, " TSO,"},
277 {NIX_TX_MULTI_SEG_F, " Scattered,"}
279 static const char *const burst_mode[] = {"Vector Neon, Tx Offloads:",
280 "Scalar, Tx Offloads:"
284 /* Update burst mode info */
285 rc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],
292 /* Update Tx offload info */
293 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
294 if (dev->tx_offload_flags & tx_offload_map[i].flags) {
295 rc = rte_strscpy(mode->info + bytes,
296 tx_offload_map[i].output,
310 nix_rx_head_tail_get(struct otx2_eth_dev *dev,
311 uint32_t *head, uint32_t *tail, uint16_t queue_idx)
315 if (head == NULL || tail == NULL)
318 reg = (((uint64_t)queue_idx) << 32);
319 val = otx2_atomic64_add_nosync(reg, (int64_t *)
320 (dev->base + NIX_LF_CQ_OP_STATUS));
321 if (val & (OP_ERR | CQ_ERR))
324 *tail = (uint32_t)(val & 0xFFFFF);
325 *head = (uint32_t)((val >> 20) & 0xFFFFF);
329 otx2_nix_rx_queue_count(void *rx_queue)
331 struct otx2_eth_rxq *rxq = rx_queue;
332 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(rxq->eth_dev);
335 nix_rx_head_tail_get(dev, &head, &tail, rxq->rq);
336 return (tail - head) % rxq->qlen;
340 nix_offset_has_packet(uint32_t head, uint32_t tail, uint16_t offset)
342 /* Check given offset(queue index) has packet filled by HW */
343 if (tail > head && offset <= tail && offset >= head)
345 /* Wrap around case */
346 if (head > tail && (offset >= head || offset <= tail))
353 otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset)
355 struct otx2_eth_rxq *rxq = rx_queue;
358 if (rxq->qlen <= offset)
361 nix_rx_head_tail_get(otx2_eth_pmd_priv(rxq->eth_dev),
362 &head, &tail, rxq->rq);
364 if (nix_offset_has_packet(head, tail, offset))
365 return RTE_ETH_RX_DESC_DONE;
367 return RTE_ETH_RX_DESC_AVAIL;
371 nix_tx_head_tail_get(struct otx2_eth_dev *dev,
372 uint32_t *head, uint32_t *tail, uint16_t queue_idx)
376 if (head == NULL || tail == NULL)
379 reg = (((uint64_t)queue_idx) << 32);
380 val = otx2_atomic64_add_nosync(reg, (int64_t *)
381 (dev->base + NIX_LF_SQ_OP_STATUS));
385 *tail = (uint32_t)((val >> 28) & 0x3F);
386 *head = (uint32_t)((val >> 20) & 0x3F);
390 otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset)
392 struct otx2_eth_txq *txq = tx_queue;
395 if (txq->qconf.nb_desc <= offset)
398 nix_tx_head_tail_get(txq->dev, &head, &tail, txq->sq);
400 if (nix_offset_has_packet(head, tail, offset))
401 return RTE_ETH_TX_DESC_DONE;
403 return RTE_ETH_TX_DESC_FULL;
406 /* It is a NOP for octeontx2 as HW frees the buffer on xmit */
408 otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt)
411 RTE_SET_USED(free_cnt);
417 otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
420 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
421 int rc = (int)fw_size;
423 if (fw_size > sizeof(dev->mkex_pfl_name))
424 rc = sizeof(dev->mkex_pfl_name);
426 rc = strlcpy(fw_version, (char *)dev->mkex_pfl_name, rc);
428 rc += 1; /* Add the size of '\0' */
429 if (fw_size < (size_t)rc)
436 otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool)
438 RTE_SET_USED(eth_dev);
440 if (!strcmp(pool, rte_mbuf_platform_mempool_ops()))
447 otx2_nix_dev_flow_ops_get(struct rte_eth_dev *eth_dev __rte_unused,
448 const struct rte_flow_ops **ops)
450 *ops = &otx2_flow_ops;
454 static struct cgx_fw_data *
455 nix_get_fwdata(struct otx2_eth_dev *dev)
457 struct otx2_mbox *mbox = dev->mbox;
458 struct cgx_fw_data *rsp = NULL;
461 otx2_mbox_alloc_msg_cgx_get_aux_link_info(mbox);
463 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
465 otx2_err("Failed to get fw data: %d", rc);
473 otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
474 struct rte_eth_dev_module_info *modinfo)
476 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
477 struct cgx_fw_data *rsp;
479 rsp = nix_get_fwdata(dev);
483 modinfo->type = rsp->fwdata.sfp_eeprom.sff_id;
484 modinfo->eeprom_len = SFP_EEPROM_SIZE;
490 otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,
491 struct rte_dev_eeprom_info *info)
493 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
494 struct cgx_fw_data *rsp;
496 if (info->offset + info->length > SFP_EEPROM_SIZE)
499 rsp = nix_get_fwdata(dev);
503 otx2_mbox_memcpy(info->data, rsp->fwdata.sfp_eeprom.buf + info->offset,
510 otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
512 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
513 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
515 devinfo->min_rx_bufsize = NIX_MIN_FRS;
516 devinfo->max_rx_pktlen = NIX_MAX_FRS;
517 devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;
518 devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;
519 devinfo->max_mac_addrs = dev->max_mac_entries;
520 devinfo->max_vfs = pci_dev->max_vfs;
521 devinfo->max_mtu = devinfo->max_rx_pktlen - NIX_L2_OVERHEAD;
522 devinfo->min_mtu = devinfo->min_rx_bufsize - NIX_L2_OVERHEAD;
523 if (dev->configured && otx2_ethdev_is_ptp_en(dev)) {
524 devinfo->max_mtu -= NIX_TIMESYNC_RX_OFFSET;
525 devinfo->min_mtu -= NIX_TIMESYNC_RX_OFFSET;
526 devinfo->max_rx_pktlen -= NIX_TIMESYNC_RX_OFFSET;
529 devinfo->rx_offload_capa = dev->rx_offload_capa;
530 devinfo->tx_offload_capa = dev->tx_offload_capa;
531 devinfo->rx_queue_offload_capa = 0;
532 devinfo->tx_queue_offload_capa = 0;
534 devinfo->reta_size = dev->rss_info.rss_size;
535 devinfo->hash_key_size = NIX_HASH_KEY_SIZE;
536 devinfo->flow_type_rss_offloads = NIX_RSS_OFFLOAD;
538 devinfo->default_rxconf = (struct rte_eth_rxconf) {
543 devinfo->default_txconf = (struct rte_eth_txconf) {
547 devinfo->default_rxportconf = (struct rte_eth_dev_portconf) {
548 .ring_size = NIX_RX_DEFAULT_RING_SZ,
551 devinfo->rx_desc_lim = (struct rte_eth_desc_lim) {
552 .nb_max = UINT16_MAX,
553 .nb_min = NIX_RX_MIN_DESC,
554 .nb_align = NIX_RX_MIN_DESC_ALIGN,
555 .nb_seg_max = NIX_RX_NB_SEG_MAX,
556 .nb_mtu_seg_max = NIX_RX_NB_SEG_MAX,
558 devinfo->rx_desc_lim.nb_max =
559 RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,
560 NIX_RX_MIN_DESC_ALIGN);
562 devinfo->tx_desc_lim = (struct rte_eth_desc_lim) {
563 .nb_max = UINT16_MAX,
566 .nb_seg_max = NIX_TX_NB_SEG_MAX,
567 .nb_mtu_seg_max = NIX_TX_NB_SEG_MAX,
570 /* Auto negotiation disabled */
571 devinfo->speed_capa = ETH_LINK_SPEED_FIXED;
572 if (!otx2_dev_is_vf_or_sdp(dev) && !otx2_dev_is_lbk(dev)) {
573 devinfo->speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
574 ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G;
576 /* 50G and 100G to be supported for board version C0
579 if (!otx2_dev_is_Ax(dev))
580 devinfo->speed_capa |= ETH_LINK_SPEED_50G |
584 devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
585 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;