1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
7 #include "otx2_ethdev.h"
10 #define NIX_DESCS_PER_LOOP 4
11 #define CQE_CAST(x) ((struct nix_cqe_hdr_s *)(x))
12 #define CQE_SZ(x) ((x) * NIX_CQ_ENTRY_SZ)
14 static inline uint16_t
15 nix_rx_nb_pkts(struct otx2_eth_rxq *rxq, const uint64_t wdata,
16 const uint16_t pkts, const uint32_t qmask)
18 uint32_t available = rxq->available;
20 /* Update the available count if cached value is not enough */
21 if (unlikely(available < pkts)) {
22 uint64_t reg, head, tail;
24 /* Use LDADDA version to avoid reorder */
25 reg = otx2_atomic64_add_sync(wdata, rxq->cq_status);
26 /* CQ_OP_STATUS operation error */
27 if (reg & BIT_ULL(CQ_OP_STAT_OP_ERR) ||
28 reg & BIT_ULL(CQ_OP_STAT_CQ_ERR))
32 head = (reg >> 20) & 0xFFFFF;
34 available = tail - head + qmask + 1;
36 available = tail - head;
38 rxq->available = available;
41 return RTE_MIN(pkts, available);
44 static __rte_always_inline uint16_t
45 nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
46 uint16_t pkts, const uint16_t flags)
48 struct otx2_eth_rxq *rxq = rx_queue;
49 const uint64_t mbuf_init = rxq->mbuf_initializer;
50 const void *lookup_mem = rxq->lookup_mem;
51 const uint64_t data_off = rxq->data_off;
52 const uintptr_t desc = rxq->desc;
53 const uint64_t wdata = rxq->wdata;
54 const uint32_t qmask = rxq->qmask;
55 uint16_t packets = 0, nb_pkts;
56 uint32_t head = rxq->head;
57 struct nix_cqe_hdr_s *cq;
58 struct rte_mbuf *mbuf;
60 nb_pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);
62 while (packets < nb_pkts) {
63 /* Prefetch N desc ahead */
64 rte_prefetch_non_temporal((void *)(desc + (CQE_SZ(head + 2))));
65 cq = (struct nix_cqe_hdr_s *)(desc + CQE_SZ(head));
67 mbuf = nix_get_mbuf_from_cqe(cq, data_off);
69 otx2_nix_cqe_to_mbuf(cq, cq->tag, mbuf, lookup_mem, mbuf_init,
71 otx2_nix_mbuf_to_tstamp(mbuf, rxq->tstamp, flags);
72 rx_pkts[packets++] = mbuf;
73 otx2_prefetch_store_keep(mbuf);
79 rxq->available -= nb_pkts;
81 /* Free all the CQs that we've processed */
82 otx2_write64((wdata | nb_pkts), rxq->cq_door);
87 #if defined(RTE_ARCH_ARM64)
89 static __rte_always_inline uint64_t
90 nix_vlan_update(const uint64_t w2, uint64_t ol_flags, uint8x16_t *f)
92 if (w2 & BIT_ULL(21) /* vtag0_gone */) {
93 ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
94 *f = vsetq_lane_u16((uint16_t)(w2 >> 32), *f, 5);
100 static __rte_always_inline uint64_t
101 nix_qinq_update(const uint64_t w2, uint64_t ol_flags, struct rte_mbuf *mbuf)
103 if (w2 & BIT_ULL(23) /* vtag1_gone */) {
104 ol_flags |= PKT_RX_QINQ | PKT_RX_QINQ_STRIPPED;
105 mbuf->vlan_tci_outer = (uint16_t)(w2 >> 48);
111 static __rte_always_inline uint16_t
112 nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,
113 uint16_t pkts, const uint16_t flags)
115 struct otx2_eth_rxq *rxq = rx_queue; uint16_t packets = 0;
116 uint64x2_t cq0_w8, cq1_w8, cq2_w8, cq3_w8, mbuf01, mbuf23;
117 const uint64_t mbuf_initializer = rxq->mbuf_initializer;
118 const uint64x2_t data_off = vdupq_n_u64(rxq->data_off);
119 uint64_t ol_flags0, ol_flags1, ol_flags2, ol_flags3;
120 uint64x2_t rearm0 = vdupq_n_u64(mbuf_initializer);
121 uint64x2_t rearm1 = vdupq_n_u64(mbuf_initializer);
122 uint64x2_t rearm2 = vdupq_n_u64(mbuf_initializer);
123 uint64x2_t rearm3 = vdupq_n_u64(mbuf_initializer);
124 struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3;
125 const uint16_t *lookup_mem = rxq->lookup_mem;
126 const uint32_t qmask = rxq->qmask;
127 const uint64_t wdata = rxq->wdata;
128 const uintptr_t desc = rxq->desc;
129 uint8x16_t f0, f1, f2, f3;
130 uint32_t head = rxq->head;
132 pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);
133 /* Packets has to be floor-aligned to NIX_DESCS_PER_LOOP */
134 pkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);
136 while (packets < pkts) {
137 /* Get the CQ pointers, since the ring size is multiple of
138 * 4, We can avoid checking the wrap around of head
139 * value after the each access unlike scalar version.
141 const uintptr_t cq0 = desc + CQE_SZ(head);
143 /* Prefetch N desc ahead */
144 rte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(8)));
145 rte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(9)));
146 rte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(10)));
147 rte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(11)));
149 /* Get NIX_RX_SG_S for size and buffer pointer */
150 cq0_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(0) + 64));
151 cq1_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(1) + 64));
152 cq2_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(2) + 64));
153 cq3_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(3) + 64));
155 /* Extract mbuf from NIX_RX_SG_S */
156 mbuf01 = vzip2q_u64(cq0_w8, cq1_w8);
157 mbuf23 = vzip2q_u64(cq2_w8, cq3_w8);
158 mbuf01 = vqsubq_u64(mbuf01, data_off);
159 mbuf23 = vqsubq_u64(mbuf23, data_off);
161 /* Move mbufs to scalar registers for future use */
162 mbuf0 = (struct rte_mbuf *)vgetq_lane_u64(mbuf01, 0);
163 mbuf1 = (struct rte_mbuf *)vgetq_lane_u64(mbuf01, 1);
164 mbuf2 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 0);
165 mbuf3 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 1);
167 /* Mask to get packet len from NIX_RX_SG_S */
168 const uint8x16_t shuf_msk = {
169 0xFF, 0xFF, /* pkt_type set as unknown */
170 0xFF, 0xFF, /* pkt_type set as unknown */
171 0, 1, /* octet 1~0, low 16 bits pkt_len */
172 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
173 0, 1, /* octet 1~0, 16 bits data_len */
175 0xFF, 0xFF, 0xFF, 0xFF
178 /* Form the rx_descriptor_fields1 with pkt_len and data_len */
179 f0 = vqtbl1q_u8(cq0_w8, shuf_msk);
180 f1 = vqtbl1q_u8(cq1_w8, shuf_msk);
181 f2 = vqtbl1q_u8(cq2_w8, shuf_msk);
182 f3 = vqtbl1q_u8(cq3_w8, shuf_msk);
184 /* Load CQE word0 and word 1 */
185 uint64x2_t cq0_w0 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(0)));
186 uint64x2_t cq1_w0 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(1)));
187 uint64x2_t cq2_w0 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(2)));
188 uint64x2_t cq3_w0 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(3)));
190 if (flags & NIX_RX_OFFLOAD_RSS_F) {
191 /* Fill rss in the rx_descriptor_fields1 */
192 f0 = vsetq_lane_u32(vgetq_lane_u32(cq0_w0, 0), f0, 3);
193 f1 = vsetq_lane_u32(vgetq_lane_u32(cq1_w0, 0), f1, 3);
194 f2 = vsetq_lane_u32(vgetq_lane_u32(cq2_w0, 0), f2, 3);
195 f3 = vsetq_lane_u32(vgetq_lane_u32(cq3_w0, 0), f3, 3);
196 ol_flags0 = PKT_RX_RSS_HASH;
197 ol_flags1 = PKT_RX_RSS_HASH;
198 ol_flags2 = PKT_RX_RSS_HASH;
199 ol_flags3 = PKT_RX_RSS_HASH;
201 ol_flags0 = 0; ol_flags1 = 0;
202 ol_flags2 = 0; ol_flags3 = 0;
205 if (flags & NIX_RX_OFFLOAD_PTYPE_F) {
206 /* Fill packet_type in the rx_descriptor_fields1 */
207 f0 = vsetq_lane_u32(nix_ptype_get(lookup_mem,
208 vgetq_lane_u64(cq0_w0, 1)), f0, 0);
209 f1 = vsetq_lane_u32(nix_ptype_get(lookup_mem,
210 vgetq_lane_u64(cq1_w0, 1)), f1, 0);
211 f2 = vsetq_lane_u32(nix_ptype_get(lookup_mem,
212 vgetq_lane_u64(cq2_w0, 1)), f2, 0);
213 f3 = vsetq_lane_u32(nix_ptype_get(lookup_mem,
214 vgetq_lane_u64(cq3_w0, 1)), f3, 0);
217 if (flags & NIX_RX_OFFLOAD_CHECKSUM_F) {
218 ol_flags0 |= nix_rx_olflags_get(lookup_mem,
219 vgetq_lane_u64(cq0_w0, 1));
220 ol_flags1 |= nix_rx_olflags_get(lookup_mem,
221 vgetq_lane_u64(cq1_w0, 1));
222 ol_flags2 |= nix_rx_olflags_get(lookup_mem,
223 vgetq_lane_u64(cq2_w0, 1));
224 ol_flags3 |= nix_rx_olflags_get(lookup_mem,
225 vgetq_lane_u64(cq3_w0, 1));
228 if (flags & NIX_RX_OFFLOAD_VLAN_STRIP_F) {
229 uint64_t cq0_w2 = *(uint64_t *)(cq0 + CQE_SZ(0) + 16);
230 uint64_t cq1_w2 = *(uint64_t *)(cq0 + CQE_SZ(1) + 16);
231 uint64_t cq2_w2 = *(uint64_t *)(cq0 + CQE_SZ(2) + 16);
232 uint64_t cq3_w2 = *(uint64_t *)(cq0 + CQE_SZ(3) + 16);
234 ol_flags0 = nix_vlan_update(cq0_w2, ol_flags0, &f0);
235 ol_flags1 = nix_vlan_update(cq1_w2, ol_flags1, &f1);
236 ol_flags2 = nix_vlan_update(cq2_w2, ol_flags2, &f2);
237 ol_flags3 = nix_vlan_update(cq3_w2, ol_flags3, &f3);
239 ol_flags0 = nix_qinq_update(cq0_w2, ol_flags0, mbuf0);
240 ol_flags1 = nix_qinq_update(cq1_w2, ol_flags1, mbuf1);
241 ol_flags2 = nix_qinq_update(cq2_w2, ol_flags2, mbuf2);
242 ol_flags3 = nix_qinq_update(cq3_w2, ol_flags3, mbuf3);
245 if (flags & NIX_RX_OFFLOAD_MARK_UPDATE_F) {
246 ol_flags0 = nix_update_match_id(*(uint16_t *)
247 (cq0 + CQE_SZ(0) + 38), ol_flags0, mbuf0);
248 ol_flags1 = nix_update_match_id(*(uint16_t *)
249 (cq0 + CQE_SZ(1) + 38), ol_flags1, mbuf1);
250 ol_flags2 = nix_update_match_id(*(uint16_t *)
251 (cq0 + CQE_SZ(2) + 38), ol_flags2, mbuf2);
252 ol_flags3 = nix_update_match_id(*(uint16_t *)
253 (cq0 + CQE_SZ(3) + 38), ol_flags3, mbuf3);
256 /* Form rearm_data with ol_flags */
257 rearm0 = vsetq_lane_u64(ol_flags0, rearm0, 1);
258 rearm1 = vsetq_lane_u64(ol_flags1, rearm1, 1);
259 rearm2 = vsetq_lane_u64(ol_flags2, rearm2, 1);
260 rearm3 = vsetq_lane_u64(ol_flags3, rearm3, 1);
262 /* Update rx_descriptor_fields1 */
263 vst1q_u64((uint64_t *)mbuf0->rx_descriptor_fields1, f0);
264 vst1q_u64((uint64_t *)mbuf1->rx_descriptor_fields1, f1);
265 vst1q_u64((uint64_t *)mbuf2->rx_descriptor_fields1, f2);
266 vst1q_u64((uint64_t *)mbuf3->rx_descriptor_fields1, f3);
268 /* Update rearm_data */
269 vst1q_u64((uint64_t *)mbuf0->rearm_data, rearm0);
270 vst1q_u64((uint64_t *)mbuf1->rearm_data, rearm1);
271 vst1q_u64((uint64_t *)mbuf2->rearm_data, rearm2);
272 vst1q_u64((uint64_t *)mbuf3->rearm_data, rearm3);
274 /* Store the mbufs to rx_pkts */
275 vst1q_u64((uint64_t *)&rx_pkts[packets], mbuf01);
276 vst1q_u64((uint64_t *)&rx_pkts[packets + 2], mbuf23);
279 otx2_prefetch_store_keep(mbuf0);
280 otx2_prefetch_store_keep(mbuf1);
281 otx2_prefetch_store_keep(mbuf2);
282 otx2_prefetch_store_keep(mbuf3);
284 /* Mark mempool obj as "get" as it is alloc'ed by NIX */
285 __mempool_check_cookies(mbuf0->pool, (void **)&mbuf0, 1, 1);
286 __mempool_check_cookies(mbuf1->pool, (void **)&mbuf1, 1, 1);
287 __mempool_check_cookies(mbuf2->pool, (void **)&mbuf2, 1, 1);
288 __mempool_check_cookies(mbuf3->pool, (void **)&mbuf3, 1, 1);
290 /* Advance head pointer and packets */
291 head += NIX_DESCS_PER_LOOP; head &= qmask;
292 packets += NIX_DESCS_PER_LOOP;
296 rxq->available -= packets;
299 /* Free all the CQs that we've processed */
300 otx2_write64((rxq->wdata | packets), rxq->cq_door);
307 static inline uint16_t
308 nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,
309 uint16_t pkts, const uint16_t flags)
311 RTE_SET_USED(rx_queue);
312 RTE_SET_USED(rx_pkts);
321 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
322 static uint16_t __rte_noinline __hot \
323 otx2_nix_recv_pkts_ ## name(void *rx_queue, \
324 struct rte_mbuf **rx_pkts, uint16_t pkts) \
326 return nix_recv_pkts(rx_queue, rx_pkts, pkts, (flags)); \
329 static uint16_t __rte_noinline __hot \
330 otx2_nix_recv_pkts_mseg_ ## name(void *rx_queue, \
331 struct rte_mbuf **rx_pkts, uint16_t pkts) \
333 return nix_recv_pkts(rx_queue, rx_pkts, pkts, \
334 (flags) | NIX_RX_MULTI_SEG_F); \
337 static uint16_t __rte_noinline __hot \
338 otx2_nix_recv_pkts_vec_ ## name(void *rx_queue, \
339 struct rte_mbuf **rx_pkts, uint16_t pkts) \
341 /* TSTMP is not supported by vector */ \
342 if ((flags) & NIX_RX_OFFLOAD_TSTAMP_F) \
344 return nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, (flags)); \
347 NIX_RX_FASTPATH_MODES
351 pick_rx_func(struct rte_eth_dev *eth_dev,
352 const eth_rx_burst_t rx_burst[2][2][2][2][2][2])
354 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
356 /* [TSTMP] [MARK] [VLAN] [CKSUM] [PTYPE] [RSS] */
357 eth_dev->rx_pkt_burst = rx_burst
358 [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F)]
359 [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_MARK_UPDATE_F)]
360 [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_VLAN_STRIP_F)]
361 [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_CHECKSUM_F)]
362 [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_PTYPE_F)]
363 [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_RSS_F)];
367 otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev)
369 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
371 const eth_rx_burst_t nix_eth_rx_burst[2][2][2][2][2][2] = {
372 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
373 [f5][f4][f3][f2][f1][f0] = otx2_nix_recv_pkts_ ## name,
375 NIX_RX_FASTPATH_MODES
379 const eth_rx_burst_t nix_eth_rx_burst_mseg[2][2][2][2][2][2] = {
380 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
381 [f5][f4][f3][f2][f1][f0] = otx2_nix_recv_pkts_mseg_ ## name,
383 NIX_RX_FASTPATH_MODES
387 const eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2][2][2] = {
388 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
389 [f5][f4][f3][f2][f1][f0] = otx2_nix_recv_pkts_vec_ ## name,
391 NIX_RX_FASTPATH_MODES
395 /* For PTP enabled, scalar rx function should be chosen as most of the
396 * PTP apps are implemented to rx burst 1 pkt.
398 if (dev->scalar_ena || dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
399 pick_rx_func(eth_dev, nix_eth_rx_burst);
401 pick_rx_func(eth_dev, nix_eth_rx_vec_burst);
403 if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
404 pick_rx_func(eth_dev, nix_eth_rx_burst_mseg);
406 /* Copy multi seg version with no offload for tear down sequence */
407 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
408 dev->rx_pkt_burst_no_offload =
409 nix_eth_rx_burst_mseg[0][0][0][0][0][0];