1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_malloc.h>
7 #include "otx2_ethdev.h"
10 /* Use last LVL_CNT nodes as default nodes */
11 #define NIX_DEFAULT_NODE_ID_START (RTE_TM_NODE_ID_NULL - NIX_TXSCH_LVL_CNT)
13 enum otx2_tm_node_level {
24 uint64_t shaper2regval(struct shaper_params *shaper)
26 return (shaper->burst_exponent << 37) | (shaper->burst_mantissa << 29) |
27 (shaper->div_exp << 13) | (shaper->exponent << 9) |
28 (shaper->mantissa << 1);
32 nix_get_link(struct otx2_eth_dev *dev)
34 int link = 13 /* SDP */;
38 lmac_chan = dev->tx_chan_base;
41 if (lmac_chan >= 0x800) {
42 map = lmac_chan & 0x7FF;
43 link = 4 * ((map >> 8) & 0xF) + ((map >> 4) & 0xF);
44 } else if (lmac_chan < 0x700) {
53 nix_get_relchan(struct otx2_eth_dev *dev)
55 return dev->tx_chan_base & 0xff;
59 nix_tm_have_tl1_access(struct otx2_eth_dev *dev)
61 bool is_lbk = otx2_dev_is_lbk(dev);
62 return otx2_dev_is_pf(dev) && !otx2_dev_is_Ax(dev) && !is_lbk;
66 nix_tm_is_leaf(struct otx2_eth_dev *dev, int lvl)
68 if (nix_tm_have_tl1_access(dev))
69 return (lvl == OTX2_TM_LVL_QUEUE);
71 return (lvl == OTX2_TM_LVL_SCH4);
75 find_prio_anchor(struct otx2_eth_dev *dev, uint32_t node_id)
77 struct otx2_nix_tm_node *child_node;
79 TAILQ_FOREACH(child_node, &dev->node_list, node) {
80 if (!child_node->parent)
82 if (!(child_node->parent->id == node_id))
84 if (child_node->priority == child_node->parent->rr_prio)
86 return child_node->hw_id - child_node->priority;
92 static struct otx2_nix_tm_shaper_profile *
93 nix_tm_shaper_profile_search(struct otx2_eth_dev *dev, uint32_t shaper_id)
95 struct otx2_nix_tm_shaper_profile *tm_shaper_profile;
97 TAILQ_FOREACH(tm_shaper_profile, &dev->shaper_profile_list, shaper) {
98 if (tm_shaper_profile->shaper_profile_id == shaper_id)
99 return tm_shaper_profile;
104 static inline uint64_t
105 shaper_rate_to_nix(uint64_t value, uint64_t *exponent_p,
106 uint64_t *mantissa_p, uint64_t *div_exp_p)
108 uint64_t div_exp, exponent, mantissa;
110 /* Boundary checks */
111 if (value < MIN_SHAPER_RATE ||
112 value > MAX_SHAPER_RATE)
115 if (value <= SHAPER_RATE(0, 0, 0)) {
116 /* Calculate rate div_exp and mantissa using
117 * the following formula:
119 * value = (2E6 * (256 + mantissa)
120 * / ((1 << div_exp) * 256))
124 mantissa = MAX_RATE_MANTISSA;
126 while (value < (NIX_SHAPER_RATE_CONST / (1 << div_exp)))
130 ((NIX_SHAPER_RATE_CONST * (256 + mantissa)) /
131 ((1 << div_exp) * 256)))
134 /* Calculate rate exponent and mantissa using
135 * the following formula:
137 * value = (2E6 * ((256 + mantissa) << exponent)) / 256
141 exponent = MAX_RATE_EXPONENT;
142 mantissa = MAX_RATE_MANTISSA;
144 while (value < (NIX_SHAPER_RATE_CONST * (1 << exponent)))
147 while (value < ((NIX_SHAPER_RATE_CONST *
148 ((256 + mantissa) << exponent)) / 256))
152 if (div_exp > MAX_RATE_DIV_EXP ||
153 exponent > MAX_RATE_EXPONENT || mantissa > MAX_RATE_MANTISSA)
157 *div_exp_p = div_exp;
159 *exponent_p = exponent;
161 *mantissa_p = mantissa;
163 /* Calculate real rate value */
164 return SHAPER_RATE(exponent, mantissa, div_exp);
167 static inline uint64_t
168 shaper_burst_to_nix(uint64_t value, uint64_t *exponent_p,
169 uint64_t *mantissa_p)
171 uint64_t exponent, mantissa;
173 if (value < MIN_SHAPER_BURST || value > MAX_SHAPER_BURST)
176 /* Calculate burst exponent and mantissa using
177 * the following formula:
179 * value = (((256 + mantissa) << (exponent + 1)
183 exponent = MAX_BURST_EXPONENT;
184 mantissa = MAX_BURST_MANTISSA;
186 while (value < (1ull << (exponent + 1)))
189 while (value < ((256 + mantissa) << (exponent + 1)) / 256)
192 if (exponent > MAX_BURST_EXPONENT || mantissa > MAX_BURST_MANTISSA)
196 *exponent_p = exponent;
198 *mantissa_p = mantissa;
200 return SHAPER_BURST(exponent, mantissa);
204 shaper_config_to_nix(struct otx2_nix_tm_shaper_profile *profile,
205 struct shaper_params *cir,
206 struct shaper_params *pir)
208 struct rte_tm_shaper_params *param = &profile->params;
213 /* Calculate CIR exponent and mantissa */
214 if (param->committed.rate)
215 cir->rate = shaper_rate_to_nix(param->committed.rate,
220 /* Calculate PIR exponent and mantissa */
221 if (param->peak.rate)
222 pir->rate = shaper_rate_to_nix(param->peak.rate,
227 /* Calculate CIR burst exponent and mantissa */
228 if (param->committed.size)
229 cir->burst = shaper_burst_to_nix(param->committed.size,
230 &cir->burst_exponent,
231 &cir->burst_mantissa);
233 /* Calculate PIR burst exponent and mantissa */
234 if (param->peak.size)
235 pir->burst = shaper_burst_to_nix(param->peak.size,
236 &pir->burst_exponent,
237 &pir->burst_mantissa);
241 populate_tm_tl1_default(struct otx2_eth_dev *dev, uint32_t schq)
243 struct otx2_mbox *mbox = dev->mbox;
244 struct nix_txschq_config *req;
247 * Default config for TL1.
248 * For VF this is always ignored.
251 req = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);
252 req->lvl = NIX_TXSCH_LVL_TL1;
254 /* Set DWRR quantum */
255 req->reg[0] = NIX_AF_TL1X_SCHEDULE(schq);
256 req->regval[0] = TXSCH_TL1_DFLT_RR_QTM;
259 req->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq);
260 req->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1);
263 req->reg[2] = NIX_AF_TL1X_CIR(schq);
267 return otx2_mbox_process(mbox);
271 prepare_tm_sched_reg(struct otx2_eth_dev *dev,
272 struct otx2_nix_tm_node *tm_node,
273 volatile uint64_t *reg, volatile uint64_t *regval)
275 uint64_t strict_prio = tm_node->priority;
276 uint32_t hw_lvl = tm_node->hw_lvl;
277 uint32_t schq = tm_node->hw_id;
281 rr_quantum = NIX_TM_WEIGHT_TO_RR_QUANTUM(tm_node->weight);
283 /* For children to root, strict prio is default if either
284 * device root is TL2 or TL1 Static Priority is disabled.
286 if (hw_lvl == NIX_TXSCH_LVL_TL2 &&
287 (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2 ||
288 dev->tm_flags & NIX_TM_TL1_NO_SP))
289 strict_prio = TXSCH_TL1_DFLT_RR_PRIO;
291 otx2_tm_dbg("Schedule config node %s(%u) lvl %u id %u, "
292 "prio 0x%" PRIx64 ", rr_quantum 0x%" PRIx64 " (%p)",
293 nix_hwlvl2str(tm_node->hw_lvl), schq, tm_node->lvl,
294 tm_node->id, strict_prio, rr_quantum, tm_node);
297 case NIX_TXSCH_LVL_SMQ:
298 reg[k] = NIX_AF_MDQX_SCHEDULE(schq);
299 regval[k] = (strict_prio << 24) | rr_quantum;
303 case NIX_TXSCH_LVL_TL4:
304 reg[k] = NIX_AF_TL4X_SCHEDULE(schq);
305 regval[k] = (strict_prio << 24) | rr_quantum;
309 case NIX_TXSCH_LVL_TL3:
310 reg[k] = NIX_AF_TL3X_SCHEDULE(schq);
311 regval[k] = (strict_prio << 24) | rr_quantum;
315 case NIX_TXSCH_LVL_TL2:
316 reg[k] = NIX_AF_TL2X_SCHEDULE(schq);
317 regval[k] = (strict_prio << 24) | rr_quantum;
321 case NIX_TXSCH_LVL_TL1:
322 reg[k] = NIX_AF_TL1X_SCHEDULE(schq);
323 regval[k] = rr_quantum;
333 prepare_tm_shaper_reg(struct otx2_nix_tm_node *tm_node,
334 struct otx2_nix_tm_shaper_profile *profile,
335 volatile uint64_t *reg, volatile uint64_t *regval)
337 struct shaper_params cir, pir;
338 uint32_t schq = tm_node->hw_id;
341 memset(&cir, 0, sizeof(cir));
342 memset(&pir, 0, sizeof(pir));
343 shaper_config_to_nix(profile, &cir, &pir);
345 otx2_tm_dbg("Shaper config node %s(%u) lvl %u id %u, "
346 "pir %" PRIu64 "(%" PRIu64 "B),"
347 " cir %" PRIu64 "(%" PRIu64 "B) (%p)",
348 nix_hwlvl2str(tm_node->hw_lvl), schq, tm_node->lvl,
349 tm_node->id, pir.rate, pir.burst,
350 cir.rate, cir.burst, tm_node);
352 switch (tm_node->hw_lvl) {
353 case NIX_TXSCH_LVL_SMQ:
354 /* Configure PIR, CIR */
355 reg[k] = NIX_AF_MDQX_PIR(schq);
356 regval[k] = (pir.rate && pir.burst) ?
357 (shaper2regval(&pir) | 1) : 0;
360 reg[k] = NIX_AF_MDQX_CIR(schq);
361 regval[k] = (cir.rate && cir.burst) ?
362 (shaper2regval(&cir) | 1) : 0;
365 /* Configure RED ALG */
366 reg[k] = NIX_AF_MDQX_SHAPE(schq);
367 regval[k] = ((uint64_t)tm_node->red_algo << 9);
370 case NIX_TXSCH_LVL_TL4:
371 /* Configure PIR, CIR */
372 reg[k] = NIX_AF_TL4X_PIR(schq);
373 regval[k] = (pir.rate && pir.burst) ?
374 (shaper2regval(&pir) | 1) : 0;
377 reg[k] = NIX_AF_TL4X_CIR(schq);
378 regval[k] = (cir.rate && cir.burst) ?
379 (shaper2regval(&cir) | 1) : 0;
382 /* Configure RED algo */
383 reg[k] = NIX_AF_TL4X_SHAPE(schq);
384 regval[k] = ((uint64_t)tm_node->red_algo << 9);
387 case NIX_TXSCH_LVL_TL3:
388 /* Configure PIR, CIR */
389 reg[k] = NIX_AF_TL3X_PIR(schq);
390 regval[k] = (pir.rate && pir.burst) ?
391 (shaper2regval(&pir) | 1) : 0;
394 reg[k] = NIX_AF_TL3X_CIR(schq);
395 regval[k] = (cir.rate && cir.burst) ?
396 (shaper2regval(&cir) | 1) : 0;
399 /* Configure RED algo */
400 reg[k] = NIX_AF_TL3X_SHAPE(schq);
401 regval[k] = ((uint64_t)tm_node->red_algo << 9);
405 case NIX_TXSCH_LVL_TL2:
406 /* Configure PIR, CIR */
407 reg[k] = NIX_AF_TL2X_PIR(schq);
408 regval[k] = (pir.rate && pir.burst) ?
409 (shaper2regval(&pir) | 1) : 0;
412 reg[k] = NIX_AF_TL2X_CIR(schq);
413 regval[k] = (cir.rate && cir.burst) ?
414 (shaper2regval(&cir) | 1) : 0;
417 /* Configure RED algo */
418 reg[k] = NIX_AF_TL2X_SHAPE(schq);
419 regval[k] = ((uint64_t)tm_node->red_algo << 9);
423 case NIX_TXSCH_LVL_TL1:
425 reg[k] = NIX_AF_TL1X_CIR(schq);
426 regval[k] = (cir.rate && cir.burst) ?
427 (shaper2regval(&cir) | 1) : 0;
436 prepare_tm_sw_xoff(struct otx2_nix_tm_node *tm_node, bool enable,
437 volatile uint64_t *reg, volatile uint64_t *regval)
439 uint32_t hw_lvl = tm_node->hw_lvl;
440 uint32_t schq = tm_node->hw_id;
443 otx2_tm_dbg("sw xoff config node %s(%u) lvl %u id %u, enable %u (%p)",
444 nix_hwlvl2str(hw_lvl), schq, tm_node->lvl,
445 tm_node->id, enable, tm_node);
450 case NIX_TXSCH_LVL_MDQ:
451 reg[k] = NIX_AF_MDQX_SW_XOFF(schq);
454 case NIX_TXSCH_LVL_TL4:
455 reg[k] = NIX_AF_TL4X_SW_XOFF(schq);
458 case NIX_TXSCH_LVL_TL3:
459 reg[k] = NIX_AF_TL3X_SW_XOFF(schq);
462 case NIX_TXSCH_LVL_TL2:
463 reg[k] = NIX_AF_TL2X_SW_XOFF(schq);
466 case NIX_TXSCH_LVL_TL1:
467 reg[k] = NIX_AF_TL1X_SW_XOFF(schq);
478 populate_tm_reg(struct otx2_eth_dev *dev,
479 struct otx2_nix_tm_node *tm_node)
481 struct otx2_nix_tm_shaper_profile *profile;
482 uint64_t regval_mask[MAX_REGS_PER_MBOX_MSG];
483 uint64_t regval[MAX_REGS_PER_MBOX_MSG];
484 uint64_t reg[MAX_REGS_PER_MBOX_MSG];
485 struct otx2_mbox *mbox = dev->mbox;
486 uint64_t parent = 0, child = 0;
487 uint32_t hw_lvl, rr_prio, schq;
488 struct nix_txschq_config *req;
492 memset(regval_mask, 0, sizeof(regval_mask));
493 profile = nix_tm_shaper_profile_search(dev,
494 tm_node->params.shaper_profile_id);
495 rr_prio = tm_node->rr_prio;
496 hw_lvl = tm_node->hw_lvl;
497 schq = tm_node->hw_id;
499 /* Root node will not have a parent node */
500 if (hw_lvl == dev->otx2_tm_root_lvl)
501 parent = tm_node->parent_hw_id;
503 parent = tm_node->parent->hw_id;
505 /* Do we need this trigger to configure TL1 */
506 if (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2 &&
507 hw_lvl == dev->otx2_tm_root_lvl) {
508 rc = populate_tm_tl1_default(dev, parent);
513 if (hw_lvl != NIX_TXSCH_LVL_SMQ)
514 child = find_prio_anchor(dev, tm_node->id);
516 /* Override default rr_prio when TL1
517 * Static Priority is disabled
519 if (hw_lvl == NIX_TXSCH_LVL_TL1 &&
520 dev->tm_flags & NIX_TM_TL1_NO_SP) {
521 rr_prio = TXSCH_TL1_DFLT_RR_PRIO;
525 otx2_tm_dbg("Topology config node %s(%u)->%s(%"PRIu64") lvl %u, id %u"
526 " prio_anchor %"PRIu64" rr_prio %u (%p)",
527 nix_hwlvl2str(hw_lvl), schq, nix_hwlvl2str(hw_lvl + 1),
528 parent, tm_node->lvl, tm_node->id, child, rr_prio, tm_node);
530 /* Prepare Topology and Link config */
532 case NIX_TXSCH_LVL_SMQ:
534 /* Set xoff which will be cleared later */
535 reg[k] = NIX_AF_SMQX_CFG(schq);
536 regval[k] = BIT_ULL(50);
537 regval_mask[k] = ~BIT_ULL(50);
540 /* Parent and schedule conf */
541 reg[k] = NIX_AF_MDQX_PARENT(schq);
542 regval[k] = parent << 16;
546 case NIX_TXSCH_LVL_TL4:
547 /* Parent and schedule conf */
548 reg[k] = NIX_AF_TL4X_PARENT(schq);
549 regval[k] = parent << 16;
552 reg[k] = NIX_AF_TL4X_TOPOLOGY(schq);
553 regval[k] = (child << 32) | (rr_prio << 1);
556 /* Configure TL4 to send to SDP channel instead of CGX/LBK */
557 if (otx2_dev_is_sdp(dev)) {
558 reg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq);
559 regval[k] = BIT_ULL(12);
563 case NIX_TXSCH_LVL_TL3:
564 /* Parent and schedule conf */
565 reg[k] = NIX_AF_TL3X_PARENT(schq);
566 regval[k] = parent << 16;
569 reg[k] = NIX_AF_TL3X_TOPOLOGY(schq);
570 regval[k] = (child << 32) | (rr_prio << 1);
573 /* Link configuration */
574 if (!otx2_dev_is_sdp(dev) &&
575 dev->link_cfg_lvl == NIX_TXSCH_LVL_TL3) {
576 reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq,
578 regval[k] = BIT_ULL(12) | nix_get_relchan(dev);
583 case NIX_TXSCH_LVL_TL2:
584 /* Parent and schedule conf */
585 reg[k] = NIX_AF_TL2X_PARENT(schq);
586 regval[k] = parent << 16;
589 reg[k] = NIX_AF_TL2X_TOPOLOGY(schq);
590 regval[k] = (child << 32) | (rr_prio << 1);
593 /* Link configuration */
594 if (!otx2_dev_is_sdp(dev) &&
595 dev->link_cfg_lvl == NIX_TXSCH_LVL_TL2) {
596 reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq,
598 regval[k] = BIT_ULL(12) | nix_get_relchan(dev);
603 case NIX_TXSCH_LVL_TL1:
604 reg[k] = NIX_AF_TL1X_TOPOLOGY(schq);
605 regval[k] = (child << 32) | (rr_prio << 1 /*RR_PRIO*/);
611 /* Prepare schedule config */
612 k += prepare_tm_sched_reg(dev, tm_node, ®[k], ®val[k]);
614 /* Prepare shaping config */
615 k += prepare_tm_shaper_reg(tm_node, profile, ®[k], ®val[k]);
620 /* Copy and send config mbox */
621 req = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);
625 otx2_mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);
626 otx2_mbox_memcpy(req->regval, regval, sizeof(uint64_t) * k);
627 otx2_mbox_memcpy(req->regval_mask, regval_mask, sizeof(uint64_t) * k);
629 rc = otx2_mbox_process(mbox);
635 otx2_err("Txschq cfg request failed for node %p, rc=%d", tm_node, rc);
641 nix_tm_txsch_reg_config(struct otx2_eth_dev *dev)
643 struct otx2_nix_tm_node *tm_node;
647 for (hw_lvl = 0; hw_lvl <= dev->otx2_tm_root_lvl; hw_lvl++) {
648 TAILQ_FOREACH(tm_node, &dev->node_list, node) {
649 if (tm_node->hw_lvl == hw_lvl &&
650 tm_node->hw_lvl != NIX_TXSCH_LVL_CNT) {
651 rc = populate_tm_reg(dev, tm_node);
661 static struct otx2_nix_tm_node *
662 nix_tm_node_search(struct otx2_eth_dev *dev,
663 uint32_t node_id, bool user)
665 struct otx2_nix_tm_node *tm_node;
667 TAILQ_FOREACH(tm_node, &dev->node_list, node) {
668 if (tm_node->id == node_id &&
669 (user == !!(tm_node->flags & NIX_TM_NODE_USER)))
676 check_rr(struct otx2_eth_dev *dev, uint32_t priority, uint32_t parent_id)
678 struct otx2_nix_tm_node *tm_node;
681 TAILQ_FOREACH(tm_node, &dev->node_list, node) {
682 if (!tm_node->parent)
685 if (!(tm_node->parent->id == parent_id))
688 if (tm_node->priority == priority)
695 nix_tm_update_parent_info(struct otx2_eth_dev *dev)
697 struct otx2_nix_tm_node *tm_node_child;
698 struct otx2_nix_tm_node *tm_node;
699 struct otx2_nix_tm_node *parent;
703 TAILQ_FOREACH(tm_node, &dev->node_list, node) {
704 if (!tm_node->parent)
706 /* Count group of children of same priority i.e are RR */
707 parent = tm_node->parent;
708 priority = tm_node->priority;
709 rr_num = check_rr(dev, priority, parent->id);
711 /* Assuming that multiple RR groups are
712 * not configured based on capability.
715 parent->rr_prio = priority;
716 parent->rr_num = rr_num;
719 /* Find out static priority children that are not in RR */
720 TAILQ_FOREACH(tm_node_child, &dev->node_list, node) {
721 if (!tm_node_child->parent)
723 if (parent->id != tm_node_child->parent->id)
725 if (parent->max_prio == UINT32_MAX &&
726 tm_node_child->priority != parent->rr_prio)
727 parent->max_prio = 0;
729 if (parent->max_prio < tm_node_child->priority &&
730 parent->rr_prio != tm_node_child->priority)
731 parent->max_prio = tm_node_child->priority;
739 nix_tm_node_add_to_list(struct otx2_eth_dev *dev, uint32_t node_id,
740 uint32_t parent_node_id, uint32_t priority,
741 uint32_t weight, uint16_t hw_lvl,
742 uint16_t lvl, bool user,
743 struct rte_tm_node_params *params)
745 struct otx2_nix_tm_shaper_profile *profile;
746 struct otx2_nix_tm_node *tm_node, *parent_node;
747 struct shaper_params cir, pir;
750 profile_id = params->shaper_profile_id;
751 profile = nix_tm_shaper_profile_search(dev, profile_id);
753 parent_node = nix_tm_node_search(dev, parent_node_id, user);
755 tm_node = rte_zmalloc("otx2_nix_tm_node",
756 sizeof(struct otx2_nix_tm_node), 0);
761 tm_node->hw_lvl = hw_lvl;
763 /* Maintain minimum weight */
767 tm_node->id = node_id;
768 tm_node->priority = priority;
769 tm_node->weight = weight;
770 tm_node->rr_prio = 0xf;
771 tm_node->max_prio = UINT32_MAX;
772 tm_node->hw_id = UINT32_MAX;
775 tm_node->flags = NIX_TM_NODE_USER;
776 rte_memcpy(&tm_node->params, params, sizeof(struct rte_tm_node_params));
779 profile->reference_count++;
781 memset(&cir, 0, sizeof(cir));
782 memset(&pir, 0, sizeof(pir));
783 shaper_config_to_nix(profile, &cir, &pir);
785 tm_node->parent = parent_node;
786 tm_node->parent_hw_id = UINT32_MAX;
787 /* C0 doesn't support STALL when both PIR & CIR are enabled */
788 if (lvl < OTX2_TM_LVL_QUEUE &&
789 otx2_dev_is_96xx_Cx(dev) &&
790 pir.rate && cir.rate)
791 tm_node->red_algo = NIX_REDALG_DISCARD;
793 tm_node->red_algo = NIX_REDALG_STD;
795 TAILQ_INSERT_TAIL(&dev->node_list, tm_node, node);
801 nix_tm_clear_shaper_profiles(struct otx2_eth_dev *dev)
803 struct otx2_nix_tm_shaper_profile *shaper_profile;
805 while ((shaper_profile = TAILQ_FIRST(&dev->shaper_profile_list))) {
806 if (shaper_profile->reference_count)
807 otx2_tm_dbg("Shaper profile %u has non zero references",
808 shaper_profile->shaper_profile_id);
809 TAILQ_REMOVE(&dev->shaper_profile_list, shaper_profile, shaper);
810 rte_free(shaper_profile);
817 nix_clear_path_xoff(struct otx2_eth_dev *dev,
818 struct otx2_nix_tm_node *tm_node)
820 struct nix_txschq_config *req;
821 struct otx2_nix_tm_node *p;
824 /* Manipulating SW_XOFF not supported on Ax */
825 if (otx2_dev_is_Ax(dev))
828 /* Enable nodes in path for flush to succeed */
829 if (!nix_tm_is_leaf(dev, tm_node->lvl))
834 if (!(p->flags & NIX_TM_NODE_ENABLED) &&
835 (p->flags & NIX_TM_NODE_HWRES)) {
836 req = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);
837 req->lvl = p->hw_lvl;
838 req->num_regs = prepare_tm_sw_xoff(p, false, req->reg,
840 rc = otx2_mbox_process(dev->mbox);
844 p->flags |= NIX_TM_NODE_ENABLED;
853 nix_smq_xoff(struct otx2_eth_dev *dev,
854 struct otx2_nix_tm_node *tm_node,
857 struct otx2_mbox *mbox = dev->mbox;
858 struct nix_txschq_config *req;
862 smq = tm_node->hw_id;
863 otx2_tm_dbg("Setting SMQ %u XOFF/FLUSH to %s", smq,
864 enable ? "enable" : "disable");
866 rc = nix_clear_path_xoff(dev, tm_node);
870 req = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);
871 req->lvl = NIX_TXSCH_LVL_SMQ;
874 req->reg[0] = NIX_AF_SMQX_CFG(smq);
875 req->regval[0] = enable ? (BIT_ULL(50) | BIT_ULL(49)) : 0;
876 req->regval_mask[0] = enable ?
877 ~(BIT_ULL(50) | BIT_ULL(49)) : ~BIT_ULL(50);
879 return otx2_mbox_process(mbox);
883 otx2_nix_sq_sqb_aura_fc(void *__txq, bool enable)
885 struct otx2_eth_txq *txq = __txq;
886 struct npa_aq_enq_req *req;
887 struct npa_aq_enq_rsp *rsp;
888 struct otx2_npa_lf *lf;
889 struct otx2_mbox *mbox;
890 uint64_t aura_handle;
893 otx2_tm_dbg("Setting SQ %u SQB aura FC to %s", txq->sq,
894 enable ? "enable" : "disable");
896 lf = otx2_npa_lf_obj_get();
900 /* Set/clear sqb aura fc_ena */
901 aura_handle = txq->sqb_pool->pool_id;
902 req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);
904 req->aura_id = npa_lf_aura_handle_to_aura(aura_handle);
905 req->ctype = NPA_AQ_CTYPE_AURA;
906 req->op = NPA_AQ_INSTOP_WRITE;
907 /* Below is not needed for aura writes but AF driver needs it */
908 /* AF will translate to associated poolctx */
909 req->aura.pool_addr = req->aura_id;
911 req->aura.fc_ena = enable;
912 req->aura_mask.fc_ena = 1;
914 rc = otx2_mbox_process(mbox);
918 /* Read back npa aura ctx */
919 req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);
921 req->aura_id = npa_lf_aura_handle_to_aura(aura_handle);
922 req->ctype = NPA_AQ_CTYPE_AURA;
923 req->op = NPA_AQ_INSTOP_READ;
925 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
929 /* Init when enabled as there might be no triggers */
931 *(volatile uint64_t *)txq->fc_mem = rsp->aura.count;
933 *(volatile uint64_t *)txq->fc_mem = txq->nb_sqb_bufs;
934 /* Sync write barrier */
941 nix_txq_flush_sq_spin(struct otx2_eth_txq *txq)
943 uint16_t sqb_cnt, head_off, tail_off;
944 struct otx2_eth_dev *dev = txq->dev;
945 uint64_t wdata, val, prev;
946 uint16_t sq = txq->sq;
948 uint64_t timeout;/* 10's of usec */
950 /* Wait for enough time based on shaper min rate */
951 timeout = (txq->qconf.nb_desc * NIX_MAX_HW_FRS * 8 * 1E5);
952 timeout = timeout / dev->tm_rate_min;
956 wdata = ((uint64_t)sq << 32);
957 regaddr = (int64_t *)(dev->base + NIX_LF_SQ_OP_STATUS);
958 val = otx2_atomic64_add_nosync(wdata, regaddr);
960 /* Spin multiple iterations as "txq->fc_cache_pkts" can still
961 * have space to send pkts even though fc_mem is disabled
967 val = otx2_atomic64_add_nosync(wdata, regaddr);
968 /* Continue on error */
969 if (val & BIT_ULL(63))
975 sqb_cnt = val & 0xFFFF;
976 head_off = (val >> 20) & 0x3F;
977 tail_off = (val >> 28) & 0x3F;
979 /* SQ reached quiescent state */
980 if (sqb_cnt <= 1 && head_off == tail_off &&
981 (*txq->fc_mem == txq->nb_sqb_bufs)) {
996 /* Flush and disable tx queue and its parent SMQ */
997 int otx2_nix_sq_flush_pre(void *_txq, bool dev_started)
999 struct otx2_nix_tm_node *tm_node, *sibling;
1000 struct otx2_eth_txq *txq;
1001 struct otx2_eth_dev *dev;
1010 user = !!(dev->tm_flags & NIX_TM_COMMITTED);
1012 /* Find the node for this SQ */
1013 tm_node = nix_tm_node_search(dev, sq, user);
1014 if (!tm_node || !(tm_node->flags & NIX_TM_NODE_ENABLED)) {
1015 otx2_err("Invalid node/state for sq %u", sq);
1019 /* Enable CGX RXTX to drain pkts */
1021 /* Though it enables both RX MCAM Entries and CGX Link
1022 * we assume all the rx queues are stopped way back.
1024 otx2_mbox_alloc_msg_nix_lf_start_rx(dev->mbox);
1025 rc = otx2_mbox_process(dev->mbox);
1027 otx2_err("cgx start failed, rc=%d", rc);
1032 /* Disable smq xoff for case it was enabled earlier */
1033 rc = nix_smq_xoff(dev, tm_node->parent, false);
1035 otx2_err("Failed to enable smq %u, rc=%d",
1036 tm_node->parent->hw_id, rc);
1040 /* As per HRM, to disable an SQ, all other SQ's
1041 * that feed to same SMQ must be paused before SMQ flush.
1043 TAILQ_FOREACH(sibling, &dev->node_list, node) {
1044 if (sibling->parent != tm_node->parent)
1046 if (!(sibling->flags & NIX_TM_NODE_ENABLED))
1050 txq = dev->eth_dev->data->tx_queues[sq];
1054 rc = otx2_nix_sq_sqb_aura_fc(txq, false);
1056 otx2_err("Failed to disable sqb aura fc, rc=%d", rc);
1060 /* Wait for sq entries to be flushed */
1061 rc = nix_txq_flush_sq_spin(txq);
1063 otx2_err("Failed to drain sq %u, rc=%d\n", txq->sq, rc);
1068 tm_node->flags &= ~NIX_TM_NODE_ENABLED;
1070 /* Disable and flush */
1071 rc = nix_smq_xoff(dev, tm_node->parent, true);
1073 otx2_err("Failed to disable smq %u, rc=%d",
1074 tm_node->parent->hw_id, rc);
1078 /* Restore cgx state */
1080 otx2_mbox_alloc_msg_nix_lf_stop_rx(dev->mbox);
1081 rc |= otx2_mbox_process(dev->mbox);
1087 int otx2_nix_sq_flush_post(void *_txq)
1089 struct otx2_nix_tm_node *tm_node, *sibling;
1090 struct otx2_eth_txq *txq = _txq;
1091 struct otx2_eth_txq *s_txq;
1092 struct otx2_eth_dev *dev;
1100 user = !!(dev->tm_flags & NIX_TM_COMMITTED);
1102 /* Find the node for this SQ */
1103 tm_node = nix_tm_node_search(dev, sq, user);
1105 otx2_err("Invalid node for sq %u", sq);
1109 /* Enable all the siblings back */
1110 TAILQ_FOREACH(sibling, &dev->node_list, node) {
1111 if (sibling->parent != tm_node->parent)
1114 if (sibling->id == sq)
1117 if (!(sibling->flags & NIX_TM_NODE_ENABLED))
1121 s_txq = dev->eth_dev->data->tx_queues[s_sq];
1126 /* Enable back if any SQ is still present */
1127 rc = nix_smq_xoff(dev, tm_node->parent, false);
1129 otx2_err("Failed to enable smq %u, rc=%d",
1130 tm_node->parent->hw_id, rc);
1136 rc = otx2_nix_sq_sqb_aura_fc(s_txq, true);
1138 otx2_err("Failed to enable sqb aura fc, rc=%d", rc);
1147 nix_sq_sched_data(struct otx2_eth_dev *dev,
1148 struct otx2_nix_tm_node *tm_node,
1149 bool rr_quantum_only)
1151 struct rte_eth_dev *eth_dev = dev->eth_dev;
1152 struct otx2_mbox *mbox = dev->mbox;
1153 uint16_t sq = tm_node->id, smq;
1154 struct nix_aq_enq_req *req;
1155 uint64_t rr_quantum;
1158 smq = tm_node->parent->hw_id;
1159 rr_quantum = NIX_TM_WEIGHT_TO_RR_QUANTUM(tm_node->weight);
1161 if (rr_quantum_only)
1162 otx2_tm_dbg("Update sq(%u) rr_quantum 0x%"PRIx64, sq, rr_quantum);
1164 otx2_tm_dbg("Enabling sq(%u)->smq(%u), rr_quantum 0x%"PRIx64,
1165 sq, smq, rr_quantum);
1167 if (sq > eth_dev->data->nb_tx_queues)
1170 req = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
1172 req->ctype = NIX_AQ_CTYPE_SQ;
1173 req->op = NIX_AQ_INSTOP_WRITE;
1175 /* smq update only when needed */
1176 if (!rr_quantum_only) {
1178 req->sq_mask.smq = ~req->sq_mask.smq;
1180 req->sq.smq_rr_quantum = rr_quantum;
1181 req->sq_mask.smq_rr_quantum = ~req->sq_mask.smq_rr_quantum;
1183 rc = otx2_mbox_process(mbox);
1185 otx2_err("Failed to set smq, rc=%d", rc);
1189 int otx2_nix_sq_enable(void *_txq)
1191 struct otx2_eth_txq *txq = _txq;
1194 /* Enable sqb_aura fc */
1195 rc = otx2_nix_sq_sqb_aura_fc(txq, true);
1197 otx2_err("Failed to enable sqb aura fc, rc=%d", rc);
1205 nix_tm_free_resources(struct otx2_eth_dev *dev, uint32_t flags_mask,
1206 uint32_t flags, bool hw_only)
1208 struct otx2_nix_tm_shaper_profile *profile;
1209 struct otx2_nix_tm_node *tm_node, *next_node;
1210 struct otx2_mbox *mbox = dev->mbox;
1211 struct nix_txsch_free_req *req;
1212 uint32_t profile_id;
1215 next_node = TAILQ_FIRST(&dev->node_list);
1217 tm_node = next_node;
1218 next_node = TAILQ_NEXT(tm_node, node);
1220 /* Check for only requested nodes */
1221 if ((tm_node->flags & flags_mask) != flags)
1224 if (!nix_tm_is_leaf(dev, tm_node->lvl) &&
1225 tm_node->hw_lvl != NIX_TXSCH_LVL_TL1 &&
1226 tm_node->flags & NIX_TM_NODE_HWRES) {
1227 /* Free specific HW resource */
1228 otx2_tm_dbg("Free hwres %s(%u) lvl %u id %u (%p)",
1229 nix_hwlvl2str(tm_node->hw_lvl),
1230 tm_node->hw_id, tm_node->lvl,
1231 tm_node->id, tm_node);
1233 rc = nix_clear_path_xoff(dev, tm_node);
1237 req = otx2_mbox_alloc_msg_nix_txsch_free(mbox);
1239 req->schq_lvl = tm_node->hw_lvl;
1240 req->schq = tm_node->hw_id;
1241 rc = otx2_mbox_process(mbox);
1244 tm_node->flags &= ~NIX_TM_NODE_HWRES;
1247 /* Leave software elements if needed */
1251 otx2_tm_dbg("Free node lvl %u id %u (%p)",
1252 tm_node->lvl, tm_node->id, tm_node);
1254 profile_id = tm_node->params.shaper_profile_id;
1255 profile = nix_tm_shaper_profile_search(dev, profile_id);
1257 profile->reference_count--;
1259 TAILQ_REMOVE(&dev->node_list, tm_node, node);
1264 /* Free all hw resources */
1265 req = otx2_mbox_alloc_msg_nix_txsch_free(mbox);
1266 req->flags = TXSCHQ_FREE_ALL;
1268 return otx2_mbox_process(mbox);
1275 nix_tm_copy_rsp_to_dev(struct otx2_eth_dev *dev,
1276 struct nix_txsch_alloc_rsp *rsp)
1281 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
1282 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) {
1283 dev->txschq_list[lvl][schq] = rsp->schq_list[lvl][schq];
1284 dev->txschq_contig_list[lvl][schq] =
1285 rsp->schq_contig_list[lvl][schq];
1288 dev->txschq[lvl] = rsp->schq[lvl];
1289 dev->txschq_contig[lvl] = rsp->schq_contig[lvl];
1295 nix_tm_assign_id_to_node(struct otx2_eth_dev *dev,
1296 struct otx2_nix_tm_node *child,
1297 struct otx2_nix_tm_node *parent)
1299 uint32_t hw_id, schq_con_index, prio_offset;
1300 uint32_t l_id, schq_index;
1302 otx2_tm_dbg("Assign hw id for child node %s lvl %u id %u (%p)",
1303 nix_hwlvl2str(child->hw_lvl), child->lvl, child->id, child);
1305 child->flags |= NIX_TM_NODE_HWRES;
1307 /* Process root nodes */
1308 if (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2 &&
1309 child->hw_lvl == dev->otx2_tm_root_lvl && !parent) {
1311 uint32_t tschq_con_index;
1313 l_id = child->hw_lvl;
1314 tschq_con_index = dev->txschq_contig_index[l_id];
1315 hw_id = dev->txschq_contig_list[l_id][tschq_con_index];
1316 child->hw_id = hw_id;
1317 dev->txschq_contig_index[l_id]++;
1318 /* Update TL1 hw_id for its parent for config purpose */
1319 idx = dev->txschq_index[NIX_TXSCH_LVL_TL1]++;
1320 hw_id = dev->txschq_list[NIX_TXSCH_LVL_TL1][idx];
1321 child->parent_hw_id = hw_id;
1324 if (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL1 &&
1325 child->hw_lvl == dev->otx2_tm_root_lvl && !parent) {
1326 uint32_t tschq_con_index;
1328 l_id = child->hw_lvl;
1329 tschq_con_index = dev->txschq_index[l_id];
1330 hw_id = dev->txschq_list[l_id][tschq_con_index];
1331 child->hw_id = hw_id;
1332 dev->txschq_index[l_id]++;
1336 /* Process children with parents */
1337 l_id = child->hw_lvl;
1338 schq_index = dev->txschq_index[l_id];
1339 schq_con_index = dev->txschq_contig_index[l_id];
1341 if (child->priority == parent->rr_prio) {
1342 hw_id = dev->txschq_list[l_id][schq_index];
1343 child->hw_id = hw_id;
1344 child->parent_hw_id = parent->hw_id;
1345 dev->txschq_index[l_id]++;
1347 prio_offset = schq_con_index + child->priority;
1348 hw_id = dev->txschq_contig_list[l_id][prio_offset];
1349 child->hw_id = hw_id;
1355 nix_tm_assign_hw_id(struct otx2_eth_dev *dev)
1357 struct otx2_nix_tm_node *parent, *child;
1358 uint32_t child_hw_lvl, con_index_inc, i;
1360 for (i = NIX_TXSCH_LVL_TL1; i > 0; i--) {
1361 TAILQ_FOREACH(parent, &dev->node_list, node) {
1362 child_hw_lvl = parent->hw_lvl - 1;
1363 if (parent->hw_lvl != i)
1365 TAILQ_FOREACH(child, &dev->node_list, node) {
1368 if (child->parent->id != parent->id)
1370 nix_tm_assign_id_to_node(dev, child, parent);
1373 con_index_inc = parent->max_prio + 1;
1374 dev->txschq_contig_index[child_hw_lvl] += con_index_inc;
1377 * Explicitly assign id to parent node if it
1378 * doesn't have a parent
1380 if (parent->hw_lvl == dev->otx2_tm_root_lvl)
1381 nix_tm_assign_id_to_node(dev, parent, NULL);
1388 nix_tm_count_req_schq(struct otx2_eth_dev *dev,
1389 struct nix_txsch_alloc_req *req, uint8_t lvl)
1391 struct otx2_nix_tm_node *tm_node;
1392 uint8_t contig_count;
1394 TAILQ_FOREACH(tm_node, &dev->node_list, node) {
1395 if (lvl == tm_node->hw_lvl) {
1396 req->schq[lvl - 1] += tm_node->rr_num;
1397 if (tm_node->max_prio != UINT32_MAX) {
1398 contig_count = tm_node->max_prio + 1;
1399 req->schq_contig[lvl - 1] += contig_count;
1402 if (lvl == dev->otx2_tm_root_lvl &&
1403 dev->otx2_tm_root_lvl && lvl == NIX_TXSCH_LVL_TL2 &&
1404 tm_node->hw_lvl == dev->otx2_tm_root_lvl) {
1405 req->schq_contig[dev->otx2_tm_root_lvl]++;
1409 req->schq[NIX_TXSCH_LVL_TL1] = 1;
1410 req->schq_contig[NIX_TXSCH_LVL_TL1] = 0;
1416 nix_tm_prepare_txschq_req(struct otx2_eth_dev *dev,
1417 struct nix_txsch_alloc_req *req)
1421 for (i = NIX_TXSCH_LVL_TL1; i > 0; i--)
1422 nix_tm_count_req_schq(dev, req, i);
1424 for (i = 0; i < NIX_TXSCH_LVL_CNT; i++) {
1425 dev->txschq_index[i] = 0;
1426 dev->txschq_contig_index[i] = 0;
1432 nix_tm_send_txsch_alloc_msg(struct otx2_eth_dev *dev)
1434 struct otx2_mbox *mbox = dev->mbox;
1435 struct nix_txsch_alloc_req *req;
1436 struct nix_txsch_alloc_rsp *rsp;
1439 req = otx2_mbox_alloc_msg_nix_txsch_alloc(mbox);
1441 rc = nix_tm_prepare_txschq_req(dev, req);
1445 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
1449 nix_tm_copy_rsp_to_dev(dev, rsp);
1450 dev->link_cfg_lvl = rsp->link_cfg_lvl;
1452 nix_tm_assign_hw_id(dev);
1457 nix_tm_alloc_resources(struct rte_eth_dev *eth_dev, bool xmit_enable)
1459 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1460 struct otx2_nix_tm_node *tm_node;
1461 struct otx2_eth_txq *txq;
1465 nix_tm_update_parent_info(dev);
1467 rc = nix_tm_send_txsch_alloc_msg(dev);
1469 otx2_err("TM failed to alloc tm resources=%d", rc);
1473 rc = nix_tm_txsch_reg_config(dev);
1475 otx2_err("TM failed to configure sched registers=%d", rc);
1479 /* Trigger MTU recalculate as SMQ needs MTU conf */
1480 if (eth_dev->data->dev_started && eth_dev->data->nb_rx_queues) {
1481 rc = otx2_nix_recalc_mtu(eth_dev);
1483 otx2_err("TM MTU update failed, rc=%d", rc);
1488 /* Mark all non-leaf's as enabled */
1489 TAILQ_FOREACH(tm_node, &dev->node_list, node) {
1490 if (!nix_tm_is_leaf(dev, tm_node->lvl))
1491 tm_node->flags |= NIX_TM_NODE_ENABLED;
1497 /* Update SQ Sched Data while SQ is idle */
1498 TAILQ_FOREACH(tm_node, &dev->node_list, node) {
1499 if (!nix_tm_is_leaf(dev, tm_node->lvl))
1502 rc = nix_sq_sched_data(dev, tm_node, false);
1504 otx2_err("SQ %u sched update failed, rc=%d",
1510 /* Finally XON all SMQ's */
1511 TAILQ_FOREACH(tm_node, &dev->node_list, node) {
1512 if (tm_node->hw_lvl != NIX_TXSCH_LVL_SMQ)
1515 rc = nix_smq_xoff(dev, tm_node, false);
1517 otx2_err("Failed to enable smq %u, rc=%d",
1518 tm_node->hw_id, rc);
1523 /* Enable xmit as all the topology is ready */
1524 TAILQ_FOREACH(tm_node, &dev->node_list, node) {
1525 if (!nix_tm_is_leaf(dev, tm_node->lvl))
1529 txq = eth_dev->data->tx_queues[sq];
1531 rc = otx2_nix_sq_enable(txq);
1533 otx2_err("TM sw xon failed on SQ %u, rc=%d",
1537 tm_node->flags |= NIX_TM_NODE_ENABLED;
1544 nix_tm_prepare_default_tree(struct rte_eth_dev *eth_dev)
1546 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1547 uint32_t def = eth_dev->data->nb_tx_queues;
1548 struct rte_tm_node_params params;
1549 uint32_t leaf_parent, i;
1550 int rc = 0, leaf_level;
1552 /* Default params */
1553 memset(¶ms, 0, sizeof(params));
1554 params.shaper_profile_id = RTE_TM_SHAPER_PROFILE_ID_NONE;
1556 if (nix_tm_have_tl1_access(dev)) {
1557 dev->otx2_tm_root_lvl = NIX_TXSCH_LVL_TL1;
1558 rc = nix_tm_node_add_to_list(dev, def, RTE_TM_NODE_ID_NULL, 0,
1561 OTX2_TM_LVL_ROOT, false, ¶ms);
1564 rc = nix_tm_node_add_to_list(dev, def + 1, def, 0,
1567 OTX2_TM_LVL_SCH1, false, ¶ms);
1571 rc = nix_tm_node_add_to_list(dev, def + 2, def + 1, 0,
1574 OTX2_TM_LVL_SCH2, false, ¶ms);
1578 rc = nix_tm_node_add_to_list(dev, def + 3, def + 2, 0,
1581 OTX2_TM_LVL_SCH3, false, ¶ms);
1585 rc = nix_tm_node_add_to_list(dev, def + 4, def + 3, 0,
1588 OTX2_TM_LVL_SCH4, false, ¶ms);
1592 leaf_parent = def + 4;
1593 leaf_level = OTX2_TM_LVL_QUEUE;
1595 dev->otx2_tm_root_lvl = NIX_TXSCH_LVL_TL2;
1596 rc = nix_tm_node_add_to_list(dev, def, RTE_TM_NODE_ID_NULL, 0,
1599 OTX2_TM_LVL_ROOT, false, ¶ms);
1603 rc = nix_tm_node_add_to_list(dev, def + 1, def, 0,
1606 OTX2_TM_LVL_SCH1, false, ¶ms);
1610 rc = nix_tm_node_add_to_list(dev, def + 2, def + 1, 0,
1613 OTX2_TM_LVL_SCH2, false, ¶ms);
1617 rc = nix_tm_node_add_to_list(dev, def + 3, def + 2, 0,
1620 OTX2_TM_LVL_SCH3, false, ¶ms);
1624 leaf_parent = def + 3;
1625 leaf_level = OTX2_TM_LVL_SCH4;
1628 /* Add leaf nodes */
1629 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1630 rc = nix_tm_node_add_to_list(dev, i, leaf_parent, 0,
1633 leaf_level, false, ¶ms);
1642 void otx2_nix_tm_conf_init(struct rte_eth_dev *eth_dev)
1644 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1646 TAILQ_INIT(&dev->node_list);
1647 TAILQ_INIT(&dev->shaper_profile_list);
1648 dev->tm_rate_min = 1E9; /* 1Gbps */
1651 int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev)
1653 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1654 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1655 uint16_t sq_cnt = eth_dev->data->nb_tx_queues;
1658 /* Free up all resources already held */
1659 rc = nix_tm_free_resources(dev, 0, 0, false);
1661 otx2_err("Failed to freeup existing resources,rc=%d", rc);
1665 /* Clear shaper profiles */
1666 nix_tm_clear_shaper_profiles(dev);
1667 dev->tm_flags = NIX_TM_DEFAULT_TREE;
1669 /* Disable TL1 Static Priority when VF's are enabled
1670 * as otherwise VF's TL2 reallocation will be needed
1671 * runtime to support a specific topology of PF.
1673 if (pci_dev->max_vfs)
1674 dev->tm_flags |= NIX_TM_TL1_NO_SP;
1676 rc = nix_tm_prepare_default_tree(eth_dev);
1680 rc = nix_tm_alloc_resources(eth_dev, false);
1683 dev->tm_leaf_cnt = sq_cnt;
1689 otx2_nix_tm_fini(struct rte_eth_dev *eth_dev)
1691 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
1694 /* Xmit is assumed to be disabled */
1695 /* Free up resources already held */
1696 rc = nix_tm_free_resources(dev, 0, 0, false);
1698 otx2_err("Failed to freeup existing resources,rc=%d", rc);
1702 /* Clear shaper profiles */
1703 nix_tm_clear_shaper_profiles(dev);
1710 otx2_nix_tm_get_leaf_data(struct otx2_eth_dev *dev, uint16_t sq,
1711 uint32_t *rr_quantum, uint16_t *smq)
1713 struct otx2_nix_tm_node *tm_node;
1716 /* 0..sq_cnt-1 are leaf nodes */
1717 if (sq >= dev->tm_leaf_cnt)
1720 /* Search for internal node first */
1721 tm_node = nix_tm_node_search(dev, sq, false);
1723 tm_node = nix_tm_node_search(dev, sq, true);
1725 /* Check if we found a valid leaf node */
1726 if (!tm_node || !nix_tm_is_leaf(dev, tm_node->lvl) ||
1727 !tm_node->parent || tm_node->parent->hw_id == UINT32_MAX) {
1731 /* Get SMQ Id of leaf node's parent */
1732 *smq = tm_node->parent->hw_id;
1733 *rr_quantum = NIX_TM_WEIGHT_TO_RR_QUANTUM(tm_node->weight);
1735 rc = nix_smq_xoff(dev, tm_node->parent, false);
1738 tm_node->flags |= NIX_TM_NODE_ENABLED;