1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_malloc.h>
7 #include "otx2_ethdev.h"
10 /* Use last LVL_CNT nodes as default nodes */
11 #define NIX_DEFAULT_NODE_ID_START (RTE_TM_NODE_ID_NULL - NIX_TXSCH_LVL_CNT)
13 enum otx2_tm_node_level {
24 nix_tm_have_tl1_access(struct otx2_eth_dev *dev)
26 bool is_lbk = otx2_dev_is_lbk(dev);
27 return otx2_dev_is_pf(dev) && !otx2_dev_is_A0(dev) &&
28 !is_lbk && !dev->maxvf;
31 static struct otx2_nix_tm_shaper_profile *
32 nix_tm_shaper_profile_search(struct otx2_eth_dev *dev, uint32_t shaper_id)
34 struct otx2_nix_tm_shaper_profile *tm_shaper_profile;
36 TAILQ_FOREACH(tm_shaper_profile, &dev->shaper_profile_list, shaper) {
37 if (tm_shaper_profile->shaper_profile_id == shaper_id)
38 return tm_shaper_profile;
43 static struct otx2_nix_tm_node *
44 nix_tm_node_search(struct otx2_eth_dev *dev,
45 uint32_t node_id, bool user)
47 struct otx2_nix_tm_node *tm_node;
49 TAILQ_FOREACH(tm_node, &dev->node_list, node) {
50 if (tm_node->id == node_id &&
51 (user == !!(tm_node->flags & NIX_TM_NODE_USER)))
58 check_rr(struct otx2_eth_dev *dev, uint32_t priority, uint32_t parent_id)
60 struct otx2_nix_tm_node *tm_node;
63 TAILQ_FOREACH(tm_node, &dev->node_list, node) {
67 if (!(tm_node->parent->id == parent_id))
70 if (tm_node->priority == priority)
77 nix_tm_update_parent_info(struct otx2_eth_dev *dev)
79 struct otx2_nix_tm_node *tm_node_child;
80 struct otx2_nix_tm_node *tm_node;
81 struct otx2_nix_tm_node *parent;
85 TAILQ_FOREACH(tm_node, &dev->node_list, node) {
88 /* Count group of children of same priority i.e are RR */
89 parent = tm_node->parent;
90 priority = tm_node->priority;
91 rr_num = check_rr(dev, priority, parent->id);
93 /* Assuming that multiple RR groups are
94 * not configured based on capability.
97 parent->rr_prio = priority;
98 parent->rr_num = rr_num;
101 /* Find out static priority children that are not in RR */
102 TAILQ_FOREACH(tm_node_child, &dev->node_list, node) {
103 if (!tm_node_child->parent)
105 if (parent->id != tm_node_child->parent->id)
107 if (parent->max_prio == UINT32_MAX &&
108 tm_node_child->priority != parent->rr_prio)
109 parent->max_prio = 0;
111 if (parent->max_prio < tm_node_child->priority &&
112 parent->rr_prio != tm_node_child->priority)
113 parent->max_prio = tm_node_child->priority;
121 nix_tm_node_add_to_list(struct otx2_eth_dev *dev, uint32_t node_id,
122 uint32_t parent_node_id, uint32_t priority,
123 uint32_t weight, uint16_t hw_lvl_id,
124 uint16_t level_id, bool user,
125 struct rte_tm_node_params *params)
127 struct otx2_nix_tm_shaper_profile *shaper_profile;
128 struct otx2_nix_tm_node *tm_node, *parent_node;
129 uint32_t shaper_profile_id;
131 shaper_profile_id = params->shaper_profile_id;
132 shaper_profile = nix_tm_shaper_profile_search(dev, shaper_profile_id);
134 parent_node = nix_tm_node_search(dev, parent_node_id, user);
136 tm_node = rte_zmalloc("otx2_nix_tm_node",
137 sizeof(struct otx2_nix_tm_node), 0);
141 tm_node->level_id = level_id;
142 tm_node->hw_lvl_id = hw_lvl_id;
144 tm_node->id = node_id;
145 tm_node->priority = priority;
146 tm_node->weight = weight;
147 tm_node->rr_prio = 0xf;
148 tm_node->max_prio = UINT32_MAX;
149 tm_node->hw_id = UINT32_MAX;
152 tm_node->flags = NIX_TM_NODE_USER;
153 rte_memcpy(&tm_node->params, params, sizeof(struct rte_tm_node_params));
156 shaper_profile->reference_count++;
157 tm_node->parent = parent_node;
158 tm_node->parent_hw_id = UINT32_MAX;
160 TAILQ_INSERT_TAIL(&dev->node_list, tm_node, node);
166 nix_tm_clear_shaper_profiles(struct otx2_eth_dev *dev)
168 struct otx2_nix_tm_shaper_profile *shaper_profile;
170 while ((shaper_profile = TAILQ_FIRST(&dev->shaper_profile_list))) {
171 if (shaper_profile->reference_count)
172 otx2_tm_dbg("Shaper profile %u has non zero references",
173 shaper_profile->shaper_profile_id);
174 TAILQ_REMOVE(&dev->shaper_profile_list, shaper_profile, shaper);
175 rte_free(shaper_profile);
182 nix_tm_free_resources(struct otx2_eth_dev *dev, uint32_t flags_mask,
183 uint32_t flags, bool hw_only)
185 struct otx2_nix_tm_shaper_profile *shaper_profile;
186 struct otx2_nix_tm_node *tm_node, *next_node;
187 struct otx2_mbox *mbox = dev->mbox;
188 struct nix_txsch_free_req *req;
189 uint32_t shaper_profile_id;
190 bool skip_node = false;
193 next_node = TAILQ_FIRST(&dev->node_list);
196 next_node = TAILQ_NEXT(tm_node, node);
198 /* Check for only requested nodes */
199 if ((tm_node->flags & flags_mask) != flags)
202 if (nix_tm_have_tl1_access(dev) &&
203 tm_node->hw_lvl_id == NIX_TXSCH_LVL_TL1)
206 otx2_tm_dbg("Free hwres for node %u, hwlvl %u, hw_id %u (%p)",
207 tm_node->id, tm_node->hw_lvl_id,
208 tm_node->hw_id, tm_node);
209 /* Free specific HW resource if requested */
210 if (!skip_node && flags_mask &&
211 tm_node->flags & NIX_TM_NODE_HWRES) {
212 req = otx2_mbox_alloc_msg_nix_txsch_free(mbox);
214 req->schq_lvl = tm_node->hw_lvl_id;
215 req->schq = tm_node->hw_id;
216 rc = otx2_mbox_process(mbox);
222 tm_node->flags &= ~NIX_TM_NODE_HWRES;
224 /* Leave software elements if needed */
228 shaper_profile_id = tm_node->params.shaper_profile_id;
230 nix_tm_shaper_profile_search(dev, shaper_profile_id);
232 shaper_profile->reference_count--;
234 TAILQ_REMOVE(&dev->node_list, tm_node, node);
239 /* Free all hw resources */
240 req = otx2_mbox_alloc_msg_nix_txsch_free(mbox);
241 req->flags = TXSCHQ_FREE_ALL;
243 return otx2_mbox_process(mbox);
250 nix_tm_copy_rsp_to_dev(struct otx2_eth_dev *dev,
251 struct nix_txsch_alloc_rsp *rsp)
256 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
257 for (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) {
258 dev->txschq_list[lvl][schq] = rsp->schq_list[lvl][schq];
259 dev->txschq_contig_list[lvl][schq] =
260 rsp->schq_contig_list[lvl][schq];
263 dev->txschq[lvl] = rsp->schq[lvl];
264 dev->txschq_contig[lvl] = rsp->schq_contig[lvl];
270 nix_tm_assign_id_to_node(struct otx2_eth_dev *dev,
271 struct otx2_nix_tm_node *child,
272 struct otx2_nix_tm_node *parent)
274 uint32_t hw_id, schq_con_index, prio_offset;
275 uint32_t l_id, schq_index;
277 otx2_tm_dbg("Assign hw id for child node %u, lvl %u, hw_lvl %u (%p)",
278 child->id, child->level_id, child->hw_lvl_id, child);
280 child->flags |= NIX_TM_NODE_HWRES;
282 /* Process root nodes */
283 if (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2 &&
284 child->hw_lvl_id == dev->otx2_tm_root_lvl && !parent) {
286 uint32_t tschq_con_index;
288 l_id = child->hw_lvl_id;
289 tschq_con_index = dev->txschq_contig_index[l_id];
290 hw_id = dev->txschq_contig_list[l_id][tschq_con_index];
291 child->hw_id = hw_id;
292 dev->txschq_contig_index[l_id]++;
293 /* Update TL1 hw_id for its parent for config purpose */
294 idx = dev->txschq_index[NIX_TXSCH_LVL_TL1]++;
295 hw_id = dev->txschq_list[NIX_TXSCH_LVL_TL1][idx];
296 child->parent_hw_id = hw_id;
299 if (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL1 &&
300 child->hw_lvl_id == dev->otx2_tm_root_lvl && !parent) {
301 uint32_t tschq_con_index;
303 l_id = child->hw_lvl_id;
304 tschq_con_index = dev->txschq_index[l_id];
305 hw_id = dev->txschq_list[l_id][tschq_con_index];
306 child->hw_id = hw_id;
307 dev->txschq_index[l_id]++;
311 /* Process children with parents */
312 l_id = child->hw_lvl_id;
313 schq_index = dev->txschq_index[l_id];
314 schq_con_index = dev->txschq_contig_index[l_id];
316 if (child->priority == parent->rr_prio) {
317 hw_id = dev->txschq_list[l_id][schq_index];
318 child->hw_id = hw_id;
319 child->parent_hw_id = parent->hw_id;
320 dev->txschq_index[l_id]++;
322 prio_offset = schq_con_index + child->priority;
323 hw_id = dev->txschq_contig_list[l_id][prio_offset];
324 child->hw_id = hw_id;
330 nix_tm_assign_hw_id(struct otx2_eth_dev *dev)
332 struct otx2_nix_tm_node *parent, *child;
333 uint32_t child_hw_lvl, con_index_inc, i;
335 for (i = NIX_TXSCH_LVL_TL1; i > 0; i--) {
336 TAILQ_FOREACH(parent, &dev->node_list, node) {
337 child_hw_lvl = parent->hw_lvl_id - 1;
338 if (parent->hw_lvl_id != i)
340 TAILQ_FOREACH(child, &dev->node_list, node) {
343 if (child->parent->id != parent->id)
345 nix_tm_assign_id_to_node(dev, child, parent);
348 con_index_inc = parent->max_prio + 1;
349 dev->txschq_contig_index[child_hw_lvl] += con_index_inc;
352 * Explicitly assign id to parent node if it
353 * doesn't have a parent
355 if (parent->hw_lvl_id == dev->otx2_tm_root_lvl)
356 nix_tm_assign_id_to_node(dev, parent, NULL);
363 nix_tm_count_req_schq(struct otx2_eth_dev *dev,
364 struct nix_txsch_alloc_req *req, uint8_t lvl)
366 struct otx2_nix_tm_node *tm_node;
367 uint8_t contig_count;
369 TAILQ_FOREACH(tm_node, &dev->node_list, node) {
370 if (lvl == tm_node->hw_lvl_id) {
371 req->schq[lvl - 1] += tm_node->rr_num;
372 if (tm_node->max_prio != UINT32_MAX) {
373 contig_count = tm_node->max_prio + 1;
374 req->schq_contig[lvl - 1] += contig_count;
377 if (lvl == dev->otx2_tm_root_lvl &&
378 dev->otx2_tm_root_lvl && lvl == NIX_TXSCH_LVL_TL2 &&
379 tm_node->hw_lvl_id == dev->otx2_tm_root_lvl) {
380 req->schq_contig[dev->otx2_tm_root_lvl]++;
384 req->schq[NIX_TXSCH_LVL_TL1] = 1;
385 req->schq_contig[NIX_TXSCH_LVL_TL1] = 0;
391 nix_tm_prepare_txschq_req(struct otx2_eth_dev *dev,
392 struct nix_txsch_alloc_req *req)
396 for (i = NIX_TXSCH_LVL_TL1; i > 0; i--)
397 nix_tm_count_req_schq(dev, req, i);
399 for (i = 0; i < NIX_TXSCH_LVL_CNT; i++) {
400 dev->txschq_index[i] = 0;
401 dev->txschq_contig_index[i] = 0;
407 nix_tm_send_txsch_alloc_msg(struct otx2_eth_dev *dev)
409 struct otx2_mbox *mbox = dev->mbox;
410 struct nix_txsch_alloc_req *req;
411 struct nix_txsch_alloc_rsp *rsp;
414 req = otx2_mbox_alloc_msg_nix_txsch_alloc(mbox);
416 rc = nix_tm_prepare_txschq_req(dev, req);
420 rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
424 nix_tm_copy_rsp_to_dev(dev, rsp);
426 nix_tm_assign_hw_id(dev);
431 nix_tm_alloc_resources(struct rte_eth_dev *eth_dev, bool xmit_enable)
433 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
436 RTE_SET_USED(xmit_enable);
438 nix_tm_update_parent_info(dev);
440 rc = nix_tm_send_txsch_alloc_msg(dev);
442 otx2_err("TM failed to alloc tm resources=%d", rc);
450 nix_tm_prepare_default_tree(struct rte_eth_dev *eth_dev)
452 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
453 uint32_t def = eth_dev->data->nb_tx_queues;
454 struct rte_tm_node_params params;
455 uint32_t leaf_parent, i;
459 memset(¶ms, 0, sizeof(params));
460 params.shaper_profile_id = RTE_TM_SHAPER_PROFILE_ID_NONE;
462 if (nix_tm_have_tl1_access(dev)) {
463 dev->otx2_tm_root_lvl = NIX_TXSCH_LVL_TL1;
464 rc = nix_tm_node_add_to_list(dev, def, RTE_TM_NODE_ID_NULL, 0,
467 OTX2_TM_LVL_ROOT, false, ¶ms);
470 rc = nix_tm_node_add_to_list(dev, def + 1, def, 0,
473 OTX2_TM_LVL_SCH1, false, ¶ms);
477 rc = nix_tm_node_add_to_list(dev, def + 2, def + 1, 0,
480 OTX2_TM_LVL_SCH2, false, ¶ms);
484 rc = nix_tm_node_add_to_list(dev, def + 3, def + 2, 0,
487 OTX2_TM_LVL_SCH3, false, ¶ms);
491 rc = nix_tm_node_add_to_list(dev, def + 4, def + 3, 0,
494 OTX2_TM_LVL_SCH4, false, ¶ms);
498 leaf_parent = def + 4;
500 dev->otx2_tm_root_lvl = NIX_TXSCH_LVL_TL2;
501 rc = nix_tm_node_add_to_list(dev, def, RTE_TM_NODE_ID_NULL, 0,
504 OTX2_TM_LVL_ROOT, false, ¶ms);
508 rc = nix_tm_node_add_to_list(dev, def + 1, def, 0,
511 OTX2_TM_LVL_SCH1, false, ¶ms);
515 rc = nix_tm_node_add_to_list(dev, def + 2, def + 1, 0,
518 OTX2_TM_LVL_SCH2, false, ¶ms);
522 rc = nix_tm_node_add_to_list(dev, def + 3, def + 2, 0,
525 OTX2_TM_LVL_SCH3, false, ¶ms);
529 leaf_parent = def + 3;
533 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
534 rc = nix_tm_node_add_to_list(dev, i, leaf_parent, 0,
537 OTX2_TM_LVL_QUEUE, false, ¶ms);
546 void otx2_nix_tm_conf_init(struct rte_eth_dev *eth_dev)
548 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
550 TAILQ_INIT(&dev->node_list);
551 TAILQ_INIT(&dev->shaper_profile_list);
554 int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev)
556 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
557 uint16_t sq_cnt = eth_dev->data->nb_tx_queues;
560 /* Free up all resources already held */
561 rc = nix_tm_free_resources(dev, 0, 0, false);
563 otx2_err("Failed to freeup existing resources,rc=%d", rc);
567 /* Clear shaper profiles */
568 nix_tm_clear_shaper_profiles(dev);
569 dev->tm_flags = NIX_TM_DEFAULT_TREE;
571 rc = nix_tm_prepare_default_tree(eth_dev);
575 rc = nix_tm_alloc_resources(eth_dev, false);
578 dev->tm_leaf_cnt = sq_cnt;
584 otx2_nix_tm_fini(struct rte_eth_dev *eth_dev)
586 struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
589 /* Xmit is assumed to be disabled */
590 /* Free up resources already held */
591 rc = nix_tm_free_resources(dev, 0, 0, false);
593 otx2_err("Failed to freeup existing resources,rc=%d", rc);
597 /* Clear shaper profiles */
598 nix_tm_clear_shaper_profiles(dev);