1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
10 #include <rte_tm_driver.h>
12 #define NIX_TM_DEFAULT_TREE BIT_ULL(0)
13 #define NIX_TM_COMMITTED BIT_ULL(1)
14 #define NIX_TM_TL1_NO_SP BIT_ULL(3)
18 void otx2_nix_tm_conf_init(struct rte_eth_dev *eth_dev);
19 int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev);
20 int otx2_nix_tm_fini(struct rte_eth_dev *eth_dev);
21 int otx2_nix_tm_get_leaf_data(struct otx2_eth_dev *dev, uint16_t sq,
22 uint32_t *rr_quantum, uint16_t *smq);
23 int otx2_nix_sq_flush_pre(void *_txq, bool dev_started);
24 int otx2_nix_sq_flush_post(void *_txq);
25 int otx2_nix_sq_enable(void *_txq);
26 int otx2_nix_sq_sqb_aura_fc(void *_txq, bool enable);
28 struct otx2_nix_tm_node {
29 TAILQ_ENTRY(otx2_nix_tm_node) node;
39 uint32_t parent_hw_id;
41 #define NIX_TM_NODE_HWRES BIT_ULL(0)
42 #define NIX_TM_NODE_ENABLED BIT_ULL(1)
43 #define NIX_TM_NODE_USER BIT_ULL(2)
44 /* Shaper algorithm for RED state @NIX_REDALG_E */
47 struct otx2_nix_tm_node *parent;
48 struct rte_tm_node_params params;
51 struct otx2_nix_tm_shaper_profile {
52 TAILQ_ENTRY(otx2_nix_tm_shaper_profile) shaper;
53 uint32_t shaper_profile_id;
54 uint32_t reference_count;
55 struct rte_tm_shaper_params params; /* Rate in bits/sec */
58 struct shaper_params {
59 uint64_t burst_exponent;
60 uint64_t burst_mantissa;
68 TAILQ_HEAD(otx2_nix_tm_node_list, otx2_nix_tm_node);
69 TAILQ_HEAD(otx2_nix_tm_shaper_profile_list, otx2_nix_tm_shaper_profile);
71 #define MAX_SCHED_WEIGHT ((uint8_t)~0)
72 #define NIX_TM_RR_QUANTUM_MAX (BIT_ULL(24) - 1)
73 #define NIX_TM_WEIGHT_TO_RR_QUANTUM(__weight) \
74 ((((__weight) & MAX_SCHED_WEIGHT) * \
75 NIX_TM_RR_QUANTUM_MAX) / MAX_SCHED_WEIGHT)
77 /* DEFAULT_RR_WEIGHT * NIX_TM_RR_QUANTUM_MAX / MAX_SCHED_WEIGHT */
78 /* = NIX_MAX_HW_MTU */
79 #define DEFAULT_RR_WEIGHT 71
81 /** NIX rate limits */
82 #define MAX_RATE_DIV_EXP 12
83 #define MAX_RATE_EXPONENT 0xf
84 #define MAX_RATE_MANTISSA 0xff
86 #define NIX_SHAPER_RATE_CONST ((uint64_t)2E6)
88 /* NIX rate calculation in Bits/Sec
89 * PIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA])
90 * << NIX_*_PIR[RATE_EXPONENT]) / 256
91 * PIR = (2E6 * PIR_ADD / (1 << NIX_*_PIR[RATE_DIVIDER_EXPONENT]))
93 * CIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA])
94 * << NIX_*_CIR[RATE_EXPONENT]) / 256
95 * CIR = (2E6 * CIR_ADD / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT]))
97 #define SHAPER_RATE(exponent, mantissa, div_exp) \
98 ((NIX_SHAPER_RATE_CONST * ((256 + (mantissa)) << (exponent)))\
99 / (((1ull << (div_exp)) * 256)))
101 /* 96xx rate limits in Bits/Sec */
102 #define MIN_SHAPER_RATE \
103 SHAPER_RATE(0, 0, MAX_RATE_DIV_EXP)
105 #define MAX_SHAPER_RATE \
106 SHAPER_RATE(MAX_RATE_EXPONENT, MAX_RATE_MANTISSA, 0)
108 /** TM Shaper - low level operations */
110 /** NIX burst limits */
111 #define MAX_BURST_EXPONENT 0xf
112 #define MAX_BURST_MANTISSA 0xff
114 /* NIX burst calculation
115 * PIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA])
116 * << (NIX_*_PIR[BURST_EXPONENT] + 1))
119 * CIR_BURST = ((256 + NIX_*_CIR[BURST_MANTISSA])
120 * << (NIX_*_CIR[BURST_EXPONENT] + 1))
123 #define SHAPER_BURST(exponent, mantissa) \
124 (((256 + (mantissa)) << ((exponent) + 1)) / 256)
126 /** Shaper burst limits */
127 #define MIN_SHAPER_BURST \
130 #define MAX_SHAPER_BURST \
131 SHAPER_BURST(MAX_BURST_EXPONENT,\
134 /* Default TL1 priority and Quantum from AF */
135 #define TXSCH_TL1_DFLT_RR_QTM ((1 << 24) - 1)
136 #define TXSCH_TL1_DFLT_RR_PRIO 1
138 static inline const char *
139 nix_hwlvl2str(uint32_t hw_lvl)
142 case NIX_TXSCH_LVL_MDQ:
144 case NIX_TXSCH_LVL_TL4:
146 case NIX_TXSCH_LVL_TL3:
148 case NIX_TXSCH_LVL_TL2:
150 case NIX_TXSCH_LVL_TL1:
159 #endif /* __OTX2_TM_H__ */