1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
10 #include <rte_tm_driver.h>
12 #define NIX_TM_DEFAULT_TREE BIT_ULL(0)
13 #define NIX_TM_COMMITTED BIT_ULL(1)
14 #define NIX_TM_RATE_LIMIT_TREE BIT_ULL(2)
15 #define NIX_TM_TL1_NO_SP BIT_ULL(3)
19 void otx2_nix_tm_conf_init(struct rte_eth_dev *eth_dev);
20 int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev);
21 int otx2_nix_tm_fini(struct rte_eth_dev *eth_dev);
22 int otx2_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops);
23 int otx2_nix_tm_get_leaf_data(struct otx2_eth_dev *dev, uint16_t sq,
24 uint32_t *rr_quantum, uint16_t *smq);
25 int otx2_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,
26 uint16_t queue_idx, uint16_t tx_rate);
27 int otx2_nix_sq_flush_pre(void *_txq, bool dev_started);
28 int otx2_nix_sq_flush_post(void *_txq);
29 int otx2_nix_sq_enable(void *_txq);
30 int otx2_nix_get_link(struct otx2_eth_dev *dev);
31 int otx2_nix_sq_sqb_aura_fc(void *_txq, bool enable);
33 struct otx2_nix_tm_node {
34 TAILQ_ENTRY(otx2_nix_tm_node) node;
44 uint32_t parent_hw_id;
46 #define NIX_TM_NODE_HWRES BIT_ULL(0)
47 #define NIX_TM_NODE_ENABLED BIT_ULL(1)
48 #define NIX_TM_NODE_USER BIT_ULL(2)
49 #define NIX_TM_NODE_RED_DISCARD BIT_ULL(3)
50 /* Shaper algorithm for RED state @NIX_REDALG_E */
53 struct otx2_nix_tm_node *parent;
54 struct rte_tm_node_params params;
61 struct otx2_nix_tm_shaper_profile {
62 TAILQ_ENTRY(otx2_nix_tm_shaper_profile) shaper;
63 uint32_t shaper_profile_id;
64 uint32_t reference_count;
65 struct rte_tm_shaper_params params; /* Rate in bits/sec */
68 struct shaper_params {
69 uint64_t burst_exponent;
70 uint64_t burst_mantissa;
78 TAILQ_HEAD(otx2_nix_tm_node_list, otx2_nix_tm_node);
79 TAILQ_HEAD(otx2_nix_tm_shaper_profile_list, otx2_nix_tm_shaper_profile);
81 #define MAX_SCHED_WEIGHT ((uint8_t)~0)
82 #define NIX_TM_RR_QUANTUM_MAX (BIT_ULL(24) - 1)
83 #define NIX_TM_WEIGHT_TO_RR_QUANTUM(__weight) \
84 ((((__weight) & MAX_SCHED_WEIGHT) * \
85 NIX_TM_RR_QUANTUM_MAX) / MAX_SCHED_WEIGHT)
87 /* DEFAULT_RR_WEIGHT * NIX_TM_RR_QUANTUM_MAX / MAX_SCHED_WEIGHT */
88 /* = NIX_MAX_HW_MTU */
89 #define DEFAULT_RR_WEIGHT 71
91 /** NIX rate limits */
92 #define MAX_RATE_DIV_EXP 12
93 #define MAX_RATE_EXPONENT 0xf
94 #define MAX_RATE_MANTISSA 0xff
96 #define NIX_SHAPER_RATE_CONST ((uint64_t)2E6)
98 /* NIX rate calculation in Bits/Sec
99 * PIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA])
100 * << NIX_*_PIR[RATE_EXPONENT]) / 256
101 * PIR = (2E6 * PIR_ADD / (1 << NIX_*_PIR[RATE_DIVIDER_EXPONENT]))
103 * CIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA])
104 * << NIX_*_CIR[RATE_EXPONENT]) / 256
105 * CIR = (2E6 * CIR_ADD / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT]))
107 #define SHAPER_RATE(exponent, mantissa, div_exp) \
108 ((NIX_SHAPER_RATE_CONST * ((256 + (mantissa)) << (exponent)))\
109 / (((1ull << (div_exp)) * 256)))
111 /* 96xx rate limits in Bits/Sec */
112 #define MIN_SHAPER_RATE \
113 SHAPER_RATE(0, 0, MAX_RATE_DIV_EXP)
115 #define MAX_SHAPER_RATE \
116 SHAPER_RATE(MAX_RATE_EXPONENT, MAX_RATE_MANTISSA, 0)
118 /** TM Shaper - low level operations */
120 /** NIX burst limits */
121 #define MAX_BURST_EXPONENT 0xf
122 #define MAX_BURST_MANTISSA 0xff
124 /* NIX burst calculation
125 * PIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA])
126 * << (NIX_*_PIR[BURST_EXPONENT] + 1))
129 * CIR_BURST = ((256 + NIX_*_CIR[BURST_MANTISSA])
130 * << (NIX_*_CIR[BURST_EXPONENT] + 1))
133 #define SHAPER_BURST(exponent, mantissa) \
134 (((256 + (mantissa)) << ((exponent) + 1)) / 256)
136 /** Shaper burst limits */
137 #define MIN_SHAPER_BURST \
140 #define MAX_SHAPER_BURST \
141 SHAPER_BURST(MAX_BURST_EXPONENT,\
144 /* Default TL1 priority and Quantum from AF */
145 #define TXSCH_TL1_DFLT_RR_QTM ((1 << 24) - 1)
146 #define TXSCH_TL1_DFLT_RR_PRIO 1
148 #define TXSCH_TLX_SP_PRIO_MAX 10
150 static inline const char *
151 nix_hwlvl2str(uint32_t hw_lvl)
154 case NIX_TXSCH_LVL_MDQ:
156 case NIX_TXSCH_LVL_TL4:
158 case NIX_TXSCH_LVL_TL3:
160 case NIX_TXSCH_LVL_TL2:
162 case NIX_TXSCH_LVL_TL1:
171 #endif /* __OTX2_TM_H__ */