1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
10 #include <rte_tm_driver.h>
12 #define NIX_TM_DEFAULT_TREE BIT_ULL(0)
16 void otx2_nix_tm_conf_init(struct rte_eth_dev *eth_dev);
17 int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev);
18 int otx2_nix_tm_fini(struct rte_eth_dev *eth_dev);
20 struct otx2_nix_tm_node {
21 TAILQ_ENTRY(otx2_nix_tm_node) node;
31 uint32_t parent_hw_id;
33 #define NIX_TM_NODE_HWRES BIT_ULL(0)
34 #define NIX_TM_NODE_ENABLED BIT_ULL(1)
35 #define NIX_TM_NODE_USER BIT_ULL(2)
36 struct otx2_nix_tm_node *parent;
37 struct rte_tm_node_params params;
40 struct otx2_nix_tm_shaper_profile {
41 TAILQ_ENTRY(otx2_nix_tm_shaper_profile) shaper;
42 uint32_t shaper_profile_id;
43 uint32_t reference_count;
44 struct rte_tm_shaper_params profile;
47 struct shaper_params {
48 uint64_t burst_exponent;
49 uint64_t burst_mantissa;
57 TAILQ_HEAD(otx2_nix_tm_node_list, otx2_nix_tm_node);
58 TAILQ_HEAD(otx2_nix_tm_shaper_profile_list, otx2_nix_tm_shaper_profile);
60 #define MAX_SCHED_WEIGHT ((uint8_t)~0)
61 #define NIX_TM_RR_QUANTUM_MAX ((1 << 24) - 1)
63 /* DEFAULT_RR_WEIGHT * NIX_TM_RR_QUANTUM_MAX / MAX_SCHED_WEIGHT */
64 /* = NIX_MAX_HW_MTU */
65 #define DEFAULT_RR_WEIGHT 71
67 /** NIX rate limits */
68 #define MAX_RATE_DIV_EXP 12
69 #define MAX_RATE_EXPONENT 0xf
70 #define MAX_RATE_MANTISSA 0xff
72 /** NIX rate limiter time-wheel resolution */
73 #define L1_TIME_WHEEL_CCLK_TICKS 240
74 #define LX_TIME_WHEEL_CCLK_TICKS 860
76 #define CCLK_HZ 1000000000
78 /* NIX rate calculation
79 * CCLK = coprocessor-clock frequency in MHz
80 * CCLK_TICKS = rate limiter time-wheel resolution
82 * PIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA])
83 * << NIX_*_PIR[RATE_EXPONENT]) / 256
84 * PIR = (CCLK / (CCLK_TICKS << NIX_*_PIR[RATE_DIVIDER_EXPONENT]))
87 * CIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA])
88 * << NIX_*_CIR[RATE_EXPONENT]) / 256
89 * CIR = (CCLK / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT]))
92 #define SHAPER_RATE(cclk_hz, cclk_ticks, \
93 exponent, mantissa, div_exp) \
94 (((uint64_t)(cclk_hz) * ((256 + (mantissa)) << (exponent))) \
95 / (((cclk_ticks) << (div_exp)) * 256))
97 #define L1_SHAPER_RATE(cclk_hz, exponent, mantissa, div_exp) \
98 SHAPER_RATE(cclk_hz, L1_TIME_WHEEL_CCLK_TICKS, \
99 exponent, mantissa, div_exp)
101 #define LX_SHAPER_RATE(cclk_hz, exponent, mantissa, div_exp) \
102 SHAPER_RATE(cclk_hz, LX_TIME_WHEEL_CCLK_TICKS, \
103 exponent, mantissa, div_exp)
105 /* Shaper rate limits */
106 #define MIN_SHAPER_RATE(cclk_hz, cclk_ticks) \
107 SHAPER_RATE(cclk_hz, cclk_ticks, 0, 0, MAX_RATE_DIV_EXP)
109 #define MAX_SHAPER_RATE(cclk_hz, cclk_ticks) \
110 SHAPER_RATE(cclk_hz, cclk_ticks, MAX_RATE_EXPONENT, \
111 MAX_RATE_MANTISSA, 0)
113 #define MIN_L1_SHAPER_RATE(cclk_hz) \
114 MIN_SHAPER_RATE(cclk_hz, L1_TIME_WHEEL_CCLK_TICKS)
116 #define MAX_L1_SHAPER_RATE(cclk_hz) \
117 MAX_SHAPER_RATE(cclk_hz, L1_TIME_WHEEL_CCLK_TICKS)
119 /** TM Shaper - low level operations */
121 /** NIX burst limits */
122 #define MAX_BURST_EXPONENT 0xf
123 #define MAX_BURST_MANTISSA 0xff
125 /* NIX burst calculation
126 * PIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA])
127 * << (NIX_*_PIR[BURST_EXPONENT] + 1))
130 * CIR_BURST = ((256 + NIX_*_CIR[BURST_MANTISSA])
131 * << (NIX_*_CIR[BURST_EXPONENT] + 1))
134 #define SHAPER_BURST(exponent, mantissa) \
135 (((256 + (mantissa)) << ((exponent) + 1)) / 256)
137 /** Shaper burst limits */
138 #define MIN_SHAPER_BURST \
141 #define MAX_SHAPER_BURST \
142 SHAPER_BURST(MAX_BURST_EXPONENT,\
145 /* Default TL1 priority and Quantum from AF */
146 #define TXSCH_TL1_DFLT_RR_QTM ((1 << 24) - 1)
147 #define TXSCH_TL1_DFLT_RR_PRIO 1
149 #endif /* __OTX2_TM_H__ */