1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "otx2_common.h"
6 #include "otx_ep_common.h"
7 #include "otx2_ep_vf.h"
10 otx2_vf_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)
12 volatile uint64_t reg_val = 0ull;
14 /* Select ES, RO, NS, RDSIZE,DPTR Format#0 for IQs
15 * IS_64B is by default enabled.
17 reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(q_no));
19 reg_val |= SDP_VF_R_IN_CTL_RDSIZE;
20 reg_val |= SDP_VF_R_IN_CTL_IS_64B;
21 reg_val |= SDP_VF_R_IN_CTL_ESR;
23 otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(q_no));
27 otx2_vf_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)
29 volatile uint64_t reg_val = 0ull;
31 reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
33 reg_val &= ~(SDP_VF_R_OUT_CTL_IMODE);
34 reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_P);
35 reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_P);
36 reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_I);
37 reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_I);
38 reg_val &= ~(SDP_VF_R_OUT_CTL_ES_I);
39 reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_D);
40 reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_D);
41 reg_val &= ~(SDP_VF_R_OUT_CTL_ES_D);
43 /* INFO/DATA ptr swap is required */
44 reg_val |= (SDP_VF_R_OUT_CTL_ES_P);
46 otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
50 otx2_vf_setup_global_input_regs(struct otx_ep_device *otx_ep)
54 for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
55 otx2_vf_setup_global_iq_reg(otx_ep, q_no);
59 otx2_vf_setup_global_output_regs(struct otx_ep_device *otx_ep)
63 for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
64 otx2_vf_setup_global_oq_reg(otx_ep, q_no);
68 otx2_vf_setup_device_regs(struct otx_ep_device *otx_ep)
70 otx2_vf_setup_global_input_regs(otx_ep);
71 otx2_vf_setup_global_output_regs(otx_ep);
74 static const struct otx_ep_config default_otx2_ep_conf = {
77 .max_iqs = OTX_EP_CFG_IO_QUEUES,
78 .instr_type = OTX_EP_64BYTE_INSTR,
79 .pending_list_size = (OTX_EP_MAX_IQ_DESCRIPTORS *
80 OTX_EP_CFG_IO_QUEUES),
85 .max_oqs = OTX_EP_CFG_IO_QUEUES,
86 .info_ptr = OTX_EP_OQ_INFOPTR_MODE,
87 .refill_threshold = OTX_EP_OQ_REFIL_THRESHOLD,
90 .num_iqdef_descs = OTX_EP_MAX_IQ_DESCRIPTORS,
91 .num_oqdef_descs = OTX_EP_MAX_OQ_DESCRIPTORS,
92 .oqdef_buf_size = OTX_EP_OQ_BUF_SIZE,
95 static const struct otx_ep_config*
96 otx2_ep_get_defconf(struct otx_ep_device *otx_ep_dev __rte_unused)
98 const struct otx_ep_config *default_conf = NULL;
100 default_conf = &default_otx2_ep_conf;
106 otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)
108 uint64_t reg_val = 0ull;
110 /* If application doesn't provide its conf, use driver default conf */
111 if (otx_ep->conf == NULL) {
112 otx_ep->conf = otx2_ep_get_defconf(otx_ep);
113 if (otx_ep->conf == NULL) {
114 otx2_err("SDP VF default config not found");
117 otx2_info("Default config is used");
120 /* Get IOQs (RPVF] count */
121 reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(0));
123 otx_ep->sriov_info.rings_per_vf = ((reg_val >> SDP_VF_R_IN_CTL_RPVF_POS)
124 & SDP_VF_R_IN_CTL_RPVF_MASK);
126 otx2_info("SDP RPVF: %d", otx_ep->sriov_info.rings_per_vf);
128 otx_ep->fn_list.setup_device_regs = otx2_vf_setup_device_regs;