1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "otx2_common.h"
6 #include "otx_ep_common.h"
7 #include "otx2_ep_vf.h"
10 otx2_vf_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no)
12 volatile uint64_t reg_val = 0ull;
14 /* Select ES, RO, NS, RDSIZE,DPTR Format#0 for IQs
15 * IS_64B is by default enabled.
17 reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(q_no));
19 reg_val |= SDP_VF_R_IN_CTL_RDSIZE;
20 reg_val |= SDP_VF_R_IN_CTL_IS_64B;
21 reg_val |= SDP_VF_R_IN_CTL_ESR;
23 otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(q_no));
27 otx2_vf_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no)
29 volatile uint64_t reg_val = 0ull;
31 reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
33 reg_val &= ~(SDP_VF_R_OUT_CTL_IMODE);
34 reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_P);
35 reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_P);
36 reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_I);
37 reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_I);
38 reg_val &= ~(SDP_VF_R_OUT_CTL_ES_I);
39 reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_D);
40 reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_D);
41 reg_val &= ~(SDP_VF_R_OUT_CTL_ES_D);
43 /* INFO/DATA ptr swap is required */
44 reg_val |= (SDP_VF_R_OUT_CTL_ES_P);
46 otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
50 otx2_vf_setup_global_input_regs(struct otx_ep_device *otx_ep)
54 for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
55 otx2_vf_setup_global_iq_reg(otx_ep, q_no);
59 otx2_vf_setup_global_output_regs(struct otx_ep_device *otx_ep)
63 for (q_no = 0; q_no < (otx_ep->sriov_info.rings_per_vf); q_no++)
64 otx2_vf_setup_global_oq_reg(otx_ep, q_no);
68 otx2_vf_setup_device_regs(struct otx_ep_device *otx_ep)
70 otx2_vf_setup_global_input_regs(otx_ep);
71 otx2_vf_setup_global_output_regs(otx_ep);
75 otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
77 struct otx_ep_instr_queue *iq = otx_ep->instr_queue[iq_no];
78 volatile uint64_t reg_val = 0ull;
80 reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(iq_no));
82 /* Wait till IDLE to set to 1, not supposed to configure BADDR
83 * as long as IDLE is 0
85 if (!(reg_val & SDP_VF_R_IN_CTL_IDLE)) {
87 reg_val = otx2_read64(otx_ep->hw_addr +
88 SDP_VF_R_IN_CONTROL(iq_no));
89 } while (!(reg_val & SDP_VF_R_IN_CTL_IDLE));
92 /* Write the start of the input queue's ring and its size */
93 otx2_write64(iq->base_addr_dma, otx_ep->hw_addr +
94 SDP_VF_R_IN_INSTR_BADDR(iq_no));
95 otx2_write64(iq->nb_desc, otx_ep->hw_addr +
96 SDP_VF_R_IN_INSTR_RSIZE(iq_no));
98 /* Remember the doorbell & instruction count register addr
101 iq->doorbell_reg = (uint8_t *)otx_ep->hw_addr +
102 SDP_VF_R_IN_INSTR_DBELL(iq_no);
103 iq->inst_cnt_reg = (uint8_t *)otx_ep->hw_addr +
104 SDP_VF_R_IN_CNTS(iq_no);
106 otx_ep_dbg("InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p",
107 iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
110 reg_val = rte_read32(iq->inst_cnt_reg);
111 rte_write32(reg_val, iq->inst_cnt_reg);
112 } while (reg_val != 0);
114 /* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR
117 otx2_write64(OTX_EP_CLEAR_SDP_IN_INT_LVLS,
118 otx_ep->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));
122 otx2_vf_setup_oq_regs(struct otx_ep_device *otx_ep, uint32_t oq_no)
124 volatile uint64_t reg_val = 0ull;
125 uint64_t oq_ctl = 0ull;
126 struct otx_ep_droq *droq = otx_ep->droq[oq_no];
128 /* Wait on IDLE to set to 1, supposed to configure BADDR
129 * as log as IDLE is 0
131 reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
133 while (!(reg_val & SDP_VF_R_OUT_CTL_IDLE)) {
134 reg_val = otx2_read64(otx_ep->hw_addr +
135 SDP_VF_R_OUT_CONTROL(oq_no));
138 otx2_write64(droq->desc_ring_dma, otx_ep->hw_addr +
139 SDP_VF_R_OUT_SLIST_BADDR(oq_no));
140 otx2_write64(droq->nb_desc, otx_ep->hw_addr +
141 SDP_VF_R_OUT_SLIST_RSIZE(oq_no));
143 oq_ctl = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
145 /* Clear the ISIZE and BSIZE (22-0) */
146 oq_ctl &= ~(OTX_EP_CLEAR_ISIZE_BSIZE);
148 /* Populate the BSIZE (15-0) */
149 oq_ctl |= (droq->buffer_size & OTX_EP_DROQ_BUFSZ_MASK);
151 otx2_write64(oq_ctl, otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
153 /* Mapped address of the pkt_sent and pkts_credit regs */
154 droq->pkts_sent_reg = (uint8_t *)otx_ep->hw_addr +
155 SDP_VF_R_OUT_CNTS(oq_no);
156 droq->pkts_credit_reg = (uint8_t *)otx_ep->hw_addr +
157 SDP_VF_R_OUT_SLIST_DBELL(oq_no);
159 rte_write64(OTX_EP_CLEAR_OUT_INT_LVLS,
160 otx_ep->hw_addr + SDP_VF_R_OUT_INT_LEVELS(oq_no));
162 /* Clear PKT_CNT register */
163 rte_write64(OTX_EP_CLEAR_SDP_OUT_PKT_CNT, (uint8_t *)otx_ep->hw_addr +
164 SDP_VF_R_OUT_PKT_CNT(oq_no));
166 /* Clear the OQ doorbell */
167 rte_write32(OTX_EP_CLEAR_SLIST_DBELL, droq->pkts_credit_reg);
168 while ((rte_read32(droq->pkts_credit_reg) != 0ull)) {
169 rte_write32(OTX_EP_CLEAR_SLIST_DBELL, droq->pkts_credit_reg);
172 otx_ep_dbg("SDP_R[%d]_credit:%x", oq_no,
173 rte_read32(droq->pkts_credit_reg));
175 /* Clear the OQ_OUT_CNTS doorbell */
176 reg_val = rte_read32(droq->pkts_sent_reg);
177 rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
179 otx_ep_dbg("SDP_R[%d]_sent: %x", oq_no,
180 rte_read32(droq->pkts_sent_reg));
182 while (((rte_read32(droq->pkts_sent_reg)) != 0ull)) {
183 reg_val = rte_read32(droq->pkts_sent_reg);
184 rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
187 otx_ep_dbg("SDP_R[%d]_sent: %x", oq_no,
188 rte_read32(droq->pkts_sent_reg));
192 otx2_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
194 uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
195 uint64_t reg_val = 0ull;
197 /* Resetting doorbells during IQ enabling also to handle abrupt
198 * guest reboot. IQ reset does not clear the doorbells.
200 otx2_write64(0xFFFFFFFF, otx_ep->hw_addr +
201 SDP_VF_R_IN_INSTR_DBELL(q_no));
203 while (((otx2_read64(otx_ep->hw_addr +
204 SDP_VF_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) {
209 otx_ep_err("INSTR DBELL not coming back to 0\n");
213 reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
216 otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
218 otx2_info("IQ[%d] enable done", q_no);
224 otx2_vf_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
226 uint64_t reg_val = 0ull;
228 reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
230 otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
232 otx2_info("OQ[%d] enable done", q_no);
238 otx2_vf_enable_io_queues(struct otx_ep_device *otx_ep)
243 for (q_no = 0; q_no < otx_ep->nb_tx_queues; q_no++) {
244 ret = otx2_vf_enable_iq(otx_ep, q_no);
249 for (q_no = 0; q_no < otx_ep->nb_rx_queues; q_no++)
250 otx2_vf_enable_oq(otx_ep, q_no);
256 otx2_vf_disable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
258 uint64_t reg_val = 0ull;
260 /* Reset the doorbell register for this Input Queue. */
261 reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
264 otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
268 otx2_vf_disable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
270 volatile uint64_t reg_val = 0ull;
272 reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
275 otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
279 otx2_vf_disable_io_queues(struct otx_ep_device *otx_ep)
283 for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) {
284 otx2_vf_disable_iq(otx_ep, q_no);
285 otx2_vf_disable_oq(otx_ep, q_no);
289 static const struct otx_ep_config default_otx2_ep_conf = {
292 .max_iqs = OTX_EP_CFG_IO_QUEUES,
293 .instr_type = OTX_EP_64BYTE_INSTR,
294 .pending_list_size = (OTX_EP_MAX_IQ_DESCRIPTORS *
295 OTX_EP_CFG_IO_QUEUES),
300 .max_oqs = OTX_EP_CFG_IO_QUEUES,
301 .info_ptr = OTX_EP_OQ_INFOPTR_MODE,
302 .refill_threshold = OTX_EP_OQ_REFIL_THRESHOLD,
305 .num_iqdef_descs = OTX_EP_MAX_IQ_DESCRIPTORS,
306 .num_oqdef_descs = OTX_EP_MAX_OQ_DESCRIPTORS,
307 .oqdef_buf_size = OTX_EP_OQ_BUF_SIZE,
310 static const struct otx_ep_config*
311 otx2_ep_get_defconf(struct otx_ep_device *otx_ep_dev __rte_unused)
313 const struct otx_ep_config *default_conf = NULL;
315 default_conf = &default_otx2_ep_conf;
321 otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep)
323 uint64_t reg_val = 0ull;
325 /* If application doesn't provide its conf, use driver default conf */
326 if (otx_ep->conf == NULL) {
327 otx_ep->conf = otx2_ep_get_defconf(otx_ep);
328 if (otx_ep->conf == NULL) {
329 otx2_err("SDP VF default config not found");
332 otx2_info("Default config is used");
335 /* Get IOQs (RPVF] count */
336 reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(0));
338 otx_ep->sriov_info.rings_per_vf = ((reg_val >> SDP_VF_R_IN_CTL_RPVF_POS)
339 & SDP_VF_R_IN_CTL_RPVF_MASK);
341 otx2_info("SDP RPVF: %d", otx_ep->sriov_info.rings_per_vf);
343 otx_ep->fn_list.setup_iq_regs = otx2_vf_setup_iq_regs;
344 otx_ep->fn_list.setup_oq_regs = otx2_vf_setup_oq_regs;
346 otx_ep->fn_list.setup_device_regs = otx2_vf_setup_device_regs;
348 otx_ep->fn_list.enable_io_queues = otx2_vf_enable_io_queues;
349 otx_ep->fn_list.disable_io_queues = otx2_vf_disable_io_queues;
351 otx_ep->fn_list.enable_iq = otx2_vf_enable_iq;
352 otx_ep->fn_list.disable_iq = otx2_vf_disable_iq;
354 otx_ep->fn_list.enable_oq = otx2_vf_enable_oq;
355 otx_ep->fn_list.disable_oq = otx2_vf_disable_oq;