drivers/net/octeontx_ep/otx2_ep_vf.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #ifndef _OTX2_EP_VF_H_
   5 #define _OTX2_EP_VF_H_
   6
   7 #include <rte_io.h>
   8
   9 #define SDP_VF_R_IN_CTL_IDLE            (0x1ull << 28)
  10 #define SDP_VF_R_IN_CTL_RDSIZE          (0x3ull << 25) /* Setting to max(4) */
  11 #define SDP_VF_R_IN_CTL_IS_64B          (0x1ull << 24)
  12 #define SDP_VF_R_IN_CTL_ESR             (0x1ull << 1)
  13
  14 #define SDP_VF_BUSY_LOOP_COUNT      (10000)
  15
  16 /* SDP VF OQ Masks */
  17 #define SDP_VF_R_OUT_CTL_IDLE         (1ull << 40)
  18 #define SDP_VF_R_OUT_CTL_ES_I         (1ull << 34)
  19 #define SDP_VF_R_OUT_CTL_NSR_I        (1ull << 33)
  20 #define SDP_VF_R_OUT_CTL_ROR_I        (1ull << 32)
  21 #define SDP_VF_R_OUT_CTL_ES_D         (1ull << 30)
  22 #define SDP_VF_R_OUT_CTL_NSR_D        (1ull << 29)
  23 #define SDP_VF_R_OUT_CTL_ROR_D        (1ull << 28)
  24 #define SDP_VF_R_OUT_CTL_ES_P         (1ull << 26)
  25 #define SDP_VF_R_OUT_CTL_NSR_P        (1ull << 25)
  26 #define SDP_VF_R_OUT_CTL_ROR_P        (1ull << 24)
  27 #define SDP_VF_R_OUT_CTL_IMODE        (1ull << 23)
  28
  29 /* SDP VF Register definitions */
  30 #define SDP_VF_RING_OFFSET                (0x1ull << 17)
  31
  32 /* SDP VF IQ Registers */
  33 #define SDP_VF_R_IN_CONTROL_START         (0x10000)
  34 #define SDP_VF_R_IN_ENABLE_START          (0x10010)
  35 #define SDP_VF_R_IN_INSTR_BADDR_START     (0x10020)
  36 #define SDP_VF_R_IN_INSTR_RSIZE_START     (0x10030)
  37 #define SDP_VF_R_IN_INSTR_DBELL_START     (0x10040)
  38 #define SDP_VF_R_IN_CNTS_START            (0x10050)
  39 #define SDP_VF_R_IN_INT_LEVELS_START      (0x10060)
  40 #define SDP_VF_R_IN_PKT_CNT_START         (0x10080)
  41 #define SDP_VF_R_IN_BYTE_CNT_START        (0x10090)
  42
  43 #define SDP_VF_R_IN_CONTROL(ring)  \
  44         (SDP_VF_R_IN_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))
  45
  46 #define SDP_VF_R_IN_ENABLE(ring)   \
  47         (SDP_VF_R_IN_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET))
  48
  49 #define SDP_VF_R_IN_INSTR_BADDR(ring)   \
  50         (SDP_VF_R_IN_INSTR_BADDR_START + ((ring) * SDP_VF_RING_OFFSET))
  51
  52 #define SDP_VF_R_IN_INSTR_RSIZE(ring)   \
  53         (SDP_VF_R_IN_INSTR_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET))
  54
  55 #define SDP_VF_R_IN_INSTR_DBELL(ring)   \
  56         (SDP_VF_R_IN_INSTR_DBELL_START + ((ring) * SDP_VF_RING_OFFSET))
  57
  58 #define SDP_VF_R_IN_CNTS(ring)          \
  59         (SDP_VF_R_IN_CNTS_START + ((ring) * SDP_VF_RING_OFFSET))
  60
  61 #define SDP_VF_R_IN_INT_LEVELS(ring)    \
  62         (SDP_VF_R_IN_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET))
  63
  64 #define SDP_VF_R_IN_PKT_CNT(ring)       \
  65         (SDP_VF_R_IN_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
  66
  67 #define SDP_VF_R_IN_BYTE_CNT(ring)          \
  68         (SDP_VF_R_IN_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
  69
  70 /* SDP VF OQ Registers */
  71 #define SDP_VF_R_OUT_CNTS_START              (0x10100)
  72 #define SDP_VF_R_OUT_INT_LEVELS_START        (0x10110)
  73 #define SDP_VF_R_OUT_SLIST_BADDR_START       (0x10120)
  74 #define SDP_VF_R_OUT_SLIST_RSIZE_START       (0x10130)
  75 #define SDP_VF_R_OUT_SLIST_DBELL_START       (0x10140)
  76 #define SDP_VF_R_OUT_CONTROL_START           (0x10150)
  77 #define SDP_VF_R_OUT_ENABLE_START            (0x10160)
  78 #define SDP_VF_R_OUT_PKT_CNT_START           (0x10180)
  79 #define SDP_VF_R_OUT_BYTE_CNT_START          (0x10190)
  80
  81 #define SDP_VF_R_OUT_CONTROL(ring)    \
  82         (SDP_VF_R_OUT_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))
  83
  84 #define SDP_VF_R_OUT_ENABLE(ring)     \
  85         (SDP_VF_R_OUT_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET))
  86
  87 #define SDP_VF_R_OUT_SLIST_BADDR(ring)  \
  88         (SDP_VF_R_OUT_SLIST_BADDR_START + ((ring) * SDP_VF_RING_OFFSET))
  89
  90 #define SDP_VF_R_OUT_SLIST_RSIZE(ring)  \
  91         (SDP_VF_R_OUT_SLIST_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET))
  92
  93 #define SDP_VF_R_OUT_SLIST_DBELL(ring)  \
  94         (SDP_VF_R_OUT_SLIST_DBELL_START + ((ring) * SDP_VF_RING_OFFSET))
  95
  96 #define SDP_VF_R_OUT_CNTS(ring)   \
  97         (SDP_VF_R_OUT_CNTS_START + ((ring) * SDP_VF_RING_OFFSET))
  98
  99 #define SDP_VF_R_OUT_INT_LEVELS(ring)   \
 100         (SDP_VF_R_OUT_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET))
 101
 102 #define SDP_VF_R_OUT_PKT_CNT(ring)   \
 103         (SDP_VF_R_OUT_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
 104
 105 #define SDP_VF_R_OUT_BYTE_CNT(ring)   \
 106         (SDP_VF_R_OUT_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))
 107
 108 /* SDP VF IQ Masks */
 109 #define SDP_VF_R_IN_CTL_RPVF_MASK       (0xF)
 110 #define SDP_VF_R_IN_CTL_RPVF_POS        (48)
 111
 112 /* IO Access */
 113 #define otx2_read64(addr) rte_read64_relaxed((void *)(addr))
 114 #define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))
 115
 116 #define PCI_DEVID_CN9K_EP_NET_VF                0xB203 /* OCTEON 9 EP mode */
 117 #define PCI_DEVID_CN98XX_EP_NET_VF              0xB103
 118
 119 int
 120 otx2_ep_vf_setup_device(struct otx_ep_device *sdpvf);
 121
 122 struct otx2_ep_instr_64B {
 123         /* Pointer where the input data is available. */
 124         uint64_t dptr;
 125
 126         /* OTX_EP Instruction Header. */
 127         union otx_ep_instr_ih ih;
 128
 129         /** Pointer where the response for a RAW mode packet
 130          * will be written by OCTEON TX.
 131          */
 132         uint64_t rptr;
 133
 134         /* Input Request Header. */
 135         union otx_ep_instr_irh irh;
 136
 137         /* Additional headers available in a 64-byte instruction. */
 138         uint64_t exhdr[4];
 139 };
 140
 141 #endif /*_OTX2_EP_VF_H_ */