1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #ifndef _OTX_EP_COMMON_H_
5 #define _OTX_EP_COMMON_H_
7 #define OTX_EP_MAX_RINGS_PER_VF (8)
8 #define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF
9 #define OTX_EP_64BYTE_INSTR (64)
10 #define OTX_EP_MIN_IQ_DESCRIPTORS (128)
11 #define OTX_EP_MIN_OQ_DESCRIPTORS (128)
12 #define OTX_EP_MAX_IQ_DESCRIPTORS (8192)
13 #define OTX_EP_MAX_OQ_DESCRIPTORS (8192)
14 #define OTX_EP_OQ_BUF_SIZE (2048)
15 #define OTX_EP_MIN_RX_BUF_SIZE (64)
17 #define OTX_EP_OQ_INFOPTR_MODE (0)
18 #define OTX_EP_OQ_REFIL_THRESHOLD (16)
20 #define otx_ep_info(fmt, args...) \
21 rte_log(RTE_LOG_INFO, otx_net_ep_logtype, \
22 "%s():%u " fmt "\n", \
23 __func__, __LINE__, ##args)
25 #define otx_ep_err(fmt, args...) \
26 rte_log(RTE_LOG_ERR, otx_net_ep_logtype, \
27 "%s():%u " fmt "\n", \
28 __func__, __LINE__, ##args)
30 #define otx_ep_dbg(fmt, args...) \
31 rte_log(RTE_LOG_DEBUG, otx_net_ep_logtype, \
32 "%s():%u " fmt "\n", \
33 __func__, __LINE__, ##args)
35 #define otx_ep_write64(value, base_addr, reg_off) \
37 typeof(value) val = (value); \
38 typeof(reg_off) off = (reg_off); \
39 otx_ep_dbg("octeon_write_csr64: reg: 0x%08lx val: 0x%016llx\n", \
40 (unsigned long)off, (unsigned long long)val); \
41 rte_write64(val, ((base_addr) + off)); \
46 /* Structure to define the configuration attributes for each Input queue. */
47 struct otx_ep_iq_config {
48 /* Max number of IQs available */
51 /* Command size - 32 or 64 bytes */
54 /* Pending list size, usually set to the sum of the size of all IQs */
55 uint32_t pending_list_size;
58 /* Structure to define the configuration attributes for each Output queue. */
59 struct otx_ep_oq_config {
60 /* Max number of OQs available */
63 /* If set, the Output queue uses info-pointer mode. (Default: 1 ) */
66 /** The number of buffers that were consumed during packet processing by
67 * the driver on this Output queue before the driver attempts to
68 * replenish the descriptor ring with new buffers.
70 uint32_t refill_threshold;
73 /* Structure to define the configuration. */
74 struct otx_ep_config {
75 /* Input Queue attributes. */
76 struct otx_ep_iq_config iq;
78 /* Output Queue attributes. */
79 struct otx_ep_oq_config oq;
81 /* Num of desc for IQ rings */
82 uint32_t num_iqdef_descs;
84 /* Num of desc for OQ rings */
85 uint32_t num_oqdef_descs;
88 uint32_t oqdef_buf_size;
91 /* SRIOV information */
92 struct otx_ep_sriov_info {
93 /* Number of rings assigned to VF */
94 uint32_t rings_per_vf;
96 /* Number of VF devices enabled */
100 /* Required functions for each VF device */
101 struct otx_ep_fn_list {
102 void (*setup_device_regs)(struct otx_ep_device *otx_ep);
105 /* OTX_EP EP VF device data structure */
106 struct otx_ep_device {
107 /* PCI device pointer */
108 struct rte_pci_device *pdev;
112 struct rte_eth_dev *eth_dev;
116 /* Memory mapped h/w address */
119 struct otx_ep_fn_list fn_list;
121 uint32_t max_tx_queues;
123 uint32_t max_rx_queues;
126 struct otx_ep_sriov_info sriov_info;
128 /* Device configuration */
129 const struct otx_ep_config *conf;
131 uint64_t rx_offloads;
133 uint64_t tx_offloads;
136 #define OTX_EP_MAX_PKT_SZ 64000U
137 #define OTX_EP_MAX_MAC_ADDRS 1
139 extern int otx_net_ep_logtype;
140 #endif /* _OTX_EP_COMMON_H_ */