1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #ifndef _OTX_EP_COMMON_H_
5 #define _OTX_EP_COMMON_H_
7 #define OTX_EP_MAX_RINGS_PER_VF (8)
8 #define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF
9 #define OTX_EP_64BYTE_INSTR (64)
10 #define OTX_EP_MIN_IQ_DESCRIPTORS (128)
11 #define OTX_EP_MIN_OQ_DESCRIPTORS (128)
12 #define OTX_EP_MAX_IQ_DESCRIPTORS (8192)
13 #define OTX_EP_MAX_OQ_DESCRIPTORS (8192)
14 #define OTX_EP_OQ_BUF_SIZE (2048)
15 #define OTX_EP_MIN_RX_BUF_SIZE (64)
17 #define OTX_EP_OQ_INFOPTR_MODE (0)
18 #define OTX_EP_OQ_REFIL_THRESHOLD (16)
19 #define OTX_EP_PCI_RING_ALIGN 65536
21 #define SDP_OTX2_PKIND 57
22 #define OTX_EP_MAX_IOQS_PER_VF 8
24 #define otx_ep_info(fmt, args...) \
25 rte_log(RTE_LOG_INFO, otx_net_ep_logtype, \
26 "%s():%u " fmt "\n", \
27 __func__, __LINE__, ##args)
29 #define otx_ep_err(fmt, args...) \
30 rte_log(RTE_LOG_ERR, otx_net_ep_logtype, \
31 "%s():%u " fmt "\n", \
32 __func__, __LINE__, ##args)
34 #define otx_ep_dbg(fmt, args...) \
35 rte_log(RTE_LOG_DEBUG, otx_net_ep_logtype, \
36 "%s():%u " fmt "\n", \
37 __func__, __LINE__, ##args)
39 #define otx_ep_write64(value, base_addr, reg_off) \
41 typeof(value) val = (value); \
42 typeof(reg_off) off = (reg_off); \
43 otx_ep_dbg("octeon_write_csr64: reg: 0x%08lx val: 0x%016llx\n", \
44 (unsigned long)off, (unsigned long long)val); \
45 rte_write64(val, ((base_addr) + off)); \
48 /* OTX_EP IQ request list */
49 struct otx_ep_instr_list {
53 #define OTX_EP_IQREQ_LIST_SIZE (sizeof(struct otx_ep_instr_list))
55 /* Input Queue statistics. Each input queue has four stats fields. */
56 struct otx_ep_iq_stats {
57 uint64_t instr_posted; /* Instructions posted to this queue. */
58 uint64_t instr_processed; /* Instructions processed in this queue. */
59 uint64_t instr_dropped; /* Instructions that could not be processed */
64 /* Structure to define the configuration attributes for each Input queue. */
65 struct otx_ep_iq_config {
66 /* Max number of IQs available */
69 /* Command size - 32 or 64 bytes */
72 /* Pending list size, usually set to the sum of the size of all IQs */
73 uint32_t pending_list_size;
76 /** The instruction (input) queue.
77 * The input queue is used to post raw (instruction) mode data or packet data
78 * to OCTEON TX2 device from the host. Each IQ of a OTX_EP EP VF device has one
79 * such structure to represent it.
81 struct otx_ep_instr_queue {
82 struct otx_ep_device *otx_ep_dev;
87 /* Flag for 64 byte commands. */
92 /* Number of descriptors in this ring. */
95 /* Input ring index, where the driver should write the next packet */
96 uint32_t host_write_index;
98 /* Input ring index, where the OCTEON TX2 should read the next packet */
99 uint32_t otx_read_index;
101 uint32_t reset_instr_cnt;
103 /** This index aids in finding the window in the queue where OCTEON TX2
104 * has read the commands.
106 uint32_t flush_index;
108 /* This keeps track of the instructions pending in this queue. */
109 uint64_t instr_pending;
111 /* Pointer to the Virtual Base addr of the input ring. */
114 /* This IQ request list */
115 struct otx_ep_instr_list *req_list;
117 /* OTX_EP doorbell register for the ring. */
120 /* OTX_EP instruction count register for this ring. */
123 /* Number of instructions pending to be posted to OCTEON TX2. */
126 /* Statistics for this input queue. */
127 struct otx_ep_iq_stats stats;
129 /* DMA mapped base address of the input descriptor ring. */
130 uint64_t base_addr_dma;
133 const struct rte_memzone *iq_mz;
136 /** Descriptor format.
137 * The descriptor ring is made of descriptors which have 2 64-bit values:
138 * -# Physical (bus) address of the data buffer.
139 * -# Physical (bus) address of a otx_ep_droq_info structure.
140 * The device DMA's incoming packets and its information at the address
141 * given by these descriptor fields.
143 struct otx_ep_droq_desc {
144 /* The buffer pointer */
147 /* The Info pointer */
150 #define OTX_EP_DROQ_DESC_SIZE (sizeof(struct otx_ep_droq_desc))
156 #define OTX_EP_RH_SIZE (sizeof(union otx_ep_rh))
158 /** Information about packet DMA'ed by OCTEON TX2.
159 * The format of the information available at Info Pointer after OCTEON TX2
160 * has posted a packet. Not all descriptors have valid information. Only
161 * the Info field of the first descriptor for a packet has information
164 struct otx_ep_droq_info {
165 /* The Length of the packet. */
168 /* The Output Receive Header. */
171 #define OTX_EP_DROQ_INFO_SIZE (sizeof(struct otx_ep_droq_info))
173 /* DROQ statistics. Each output queue has four stats fields. */
174 struct otx_ep_droq_stats {
175 /* Number of packets received in this queue. */
176 uint64_t pkts_received;
178 /* Bytes received by this queue. */
179 uint64_t bytes_received;
181 /* Num of failures of rte_pktmbuf_alloc() */
182 uint64_t rx_alloc_failure;
187 /* packets with data got ready after interrupt arrived */
188 uint64_t pkts_delayed_data;
190 /* packets dropped due to zero length */
191 uint64_t dropped_zlp;
194 /* Structure to define the configuration attributes for each Output queue. */
195 struct otx_ep_oq_config {
196 /* Max number of OQs available */
199 /* If set, the Output queue uses info-pointer mode. (Default: 1 ) */
202 /** The number of buffers that were consumed during packet processing by
203 * the driver on this Output queue before the driver attempts to
204 * replenish the descriptor ring with new buffers.
206 uint32_t refill_threshold;
209 /* The Descriptor Ring Output Queue(DROQ) structure. */
211 struct otx_ep_device *otx_ep_dev;
212 /* The 8B aligned descriptor ring starts at this address. */
213 struct otx_ep_droq_desc *desc_ring;
216 uint64_t last_pkt_count;
218 struct rte_mempool *mpool;
220 /* Driver should read the next packet at this index */
223 /* OCTEON TX2 will write the next packet at this index */
226 /* At this index, the driver will refill the descriptor's buffer */
229 /* Packets pending to be processed */
230 uint64_t pkts_pending;
232 /* Number of descriptors in this ring. */
235 /* The number of descriptors pending to refill. */
236 uint32_t refill_count;
238 uint32_t refill_threshold;
240 /* The 8B aligned info ptrs begin from this address. */
241 struct otx_ep_droq_info *info_list;
243 /* receive buffer list contains mbuf ptr list */
244 struct rte_mbuf **recv_buf_list;
246 /* The size of each buffer pointed by the buffer pointer. */
247 uint32_t buffer_size;
249 /* Statistics for this DROQ. */
250 struct otx_ep_droq_stats stats;
252 /* DMA mapped address of the DROQ descriptor ring. */
253 size_t desc_ring_dma;
255 /* Info_ptr list is allocated at this virtual address. */
256 size_t info_base_addr;
258 /* DMA mapped address of the info list */
259 size_t info_list_dma;
261 /* Allocated size of info list. */
262 uint32_t info_alloc_size;
265 const struct rte_memzone *desc_ring_mz;
266 const struct rte_memzone *info_mz;
268 #define OTX_EP_DROQ_SIZE (sizeof(struct otx_ep_droq))
271 struct otx_ep_io_enable {
277 /* Structure to define the configuration. */
278 struct otx_ep_config {
279 /* Input Queue attributes. */
280 struct otx_ep_iq_config iq;
282 /* Output Queue attributes. */
283 struct otx_ep_oq_config oq;
285 /* Num of desc for IQ rings */
286 uint32_t num_iqdef_descs;
288 /* Num of desc for OQ rings */
289 uint32_t num_oqdef_descs;
292 uint32_t oqdef_buf_size;
295 /* SRIOV information */
296 struct otx_ep_sriov_info {
297 /* Number of rings assigned to VF */
298 uint32_t rings_per_vf;
300 /* Number of VF devices enabled */
304 /* Required functions for each VF device */
305 struct otx_ep_fn_list {
306 void (*setup_iq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);
308 void (*setup_oq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);
310 void (*setup_device_regs)(struct otx_ep_device *otx_ep);
312 void (*disable_io_queues)(struct otx_ep_device *otx_ep);
315 /* OTX_EP EP VF device data structure */
316 struct otx_ep_device {
317 /* PCI device pointer */
318 struct rte_pci_device *pdev;
324 struct rte_eth_dev *eth_dev;
328 /* Memory mapped h/w address */
331 struct otx_ep_fn_list fn_list;
333 uint32_t max_tx_queues;
335 uint32_t max_rx_queues;
338 uint32_t nb_tx_queues;
340 /* The input instruction queues */
341 struct otx_ep_instr_queue *instr_queue[OTX_EP_MAX_IOQS_PER_VF];
344 uint32_t nb_rx_queues;
346 /* The DROQ output queues */
347 struct otx_ep_droq *droq[OTX_EP_MAX_IOQS_PER_VF];
350 struct otx_ep_io_enable io_qmask;
353 struct otx_ep_sriov_info sriov_info;
355 /* Device configuration */
356 const struct otx_ep_config *conf;
358 uint64_t rx_offloads;
360 uint64_t tx_offloads;
363 int otx_ep_setup_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no,
364 int num_descs, unsigned int socket_id);
365 int otx_ep_delete_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no);
367 int otx_ep_setup_oqs(struct otx_ep_device *otx_ep, int oq_no, int num_descs,
368 int desc_size, struct rte_mempool *mpool,
369 unsigned int socket_id);
370 int otx_ep_delete_oqs(struct otx_ep_device *otx_ep, uint32_t oq_no);
372 #define OTX_EP_MAX_PKT_SZ 64000U
373 #define OTX_EP_MAX_MAC_ADDRS 1
375 extern int otx_net_ep_logtype;
376 #endif /* _OTX_EP_COMMON_H_ */