1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #ifndef _OTX_EP_COMMON_H_
5 #define _OTX_EP_COMMON_H_
8 #define OTX_EP_NW_PKT_OP 0x1220
9 #define OTX_EP_NW_CMD_OP 0x1221
11 #define OTX_EP_MAX_RINGS_PER_VF (8)
12 #define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF
13 #define OTX_EP_64BYTE_INSTR (64)
14 #define OTX_EP_MIN_IQ_DESCRIPTORS (128)
15 #define OTX_EP_MIN_OQ_DESCRIPTORS (128)
16 #define OTX_EP_MAX_IQ_DESCRIPTORS (8192)
17 #define OTX_EP_MAX_OQ_DESCRIPTORS (8192)
18 #define OTX_EP_OQ_BUF_SIZE (2048)
19 #define OTX_EP_MIN_RX_BUF_SIZE (64)
21 #define OTX_EP_OQ_INFOPTR_MODE (0)
22 #define OTX_EP_OQ_REFIL_THRESHOLD (16)
24 /* IQ instruction req types */
25 #define OTX_EP_REQTYPE_NONE (0)
26 #define OTX_EP_REQTYPE_NORESP_INSTR (1)
27 #define OTX_EP_REQTYPE_NORESP_NET_DIRECT (2)
28 #define OTX_EP_REQTYPE_NORESP_NET OTX_EP_REQTYPE_NORESP_NET_DIRECT
29 #define OTX_EP_REQTYPE_NORESP_GATHER (3)
30 #define OTX_EP_NORESP_OHSM_SEND (4)
31 #define OTX_EP_NORESP_LAST (4)
32 #define OTX_EP_PCI_RING_ALIGN 65536
34 #define SDP_OTX2_PKIND 57
39 #define NULL_NULL_TAG 3
41 #define OTX_EP_BUSY_LOOP_COUNT (10000)
42 #define OTX_EP_MAX_IOQS_PER_VF 8
43 #define OTX_CUST_DATA_LEN 0
45 #define otx_ep_info(fmt, args...) \
46 rte_log(RTE_LOG_INFO, otx_net_ep_logtype, \
47 "%s():%u " fmt "\n", \
48 __func__, __LINE__, ##args)
50 #define otx_ep_err(fmt, args...) \
51 rte_log(RTE_LOG_ERR, otx_net_ep_logtype, \
52 "%s():%u " fmt "\n", \
53 __func__, __LINE__, ##args)
55 #define otx_ep_dbg(fmt, args...) \
56 rte_log(RTE_LOG_DEBUG, otx_net_ep_logtype, \
57 "%s():%u " fmt "\n", \
58 __func__, __LINE__, ##args)
60 /* Input Request Header format */
61 union otx_ep_instr_irh {
67 /* PCIe port to use for response */
70 /* Scatter indicator 1=scatter */
73 /* Size of Expected result OR no. of entries in scatter list */
76 /* Desired destination port for result */
79 /* Opcode Specific parameters */
82 /* Opcode for the return packet */
87 #define otx_ep_write64(value, base_addr, reg_off) \
89 typeof(value) val = (value); \
90 typeof(reg_off) off = (reg_off); \
91 otx_ep_dbg("octeon_write_csr64: reg: 0x%08lx val: 0x%016llx\n", \
92 (unsigned long)off, (unsigned long long)val); \
93 rte_write64(val, ((base_addr) + off)); \
96 /* Instruction Header - for OCTEON-TX models */
97 typedef union otx_ep_instr_ih {
106 /** PKIND for OTX_EP */
109 /** Front Data size */
112 /** No. of entries in gather list */
115 /** Gather indicator 1=gather*/
119 uint64_t reserved3:1;
123 /* OTX_EP IQ request list */
124 struct otx_ep_instr_list {
128 #define OTX_EP_IQREQ_LIST_SIZE (sizeof(struct otx_ep_instr_list))
130 /* Input Queue statistics. Each input queue has four stats fields. */
131 struct otx_ep_iq_stats {
132 uint64_t instr_posted; /* Instructions posted to this queue. */
133 uint64_t instr_processed; /* Instructions processed in this queue. */
134 uint64_t instr_dropped; /* Instructions that could not be processed */
139 /* Structure to define the configuration attributes for each Input queue. */
140 struct otx_ep_iq_config {
141 /* Max number of IQs available */
144 /* Command size - 32 or 64 bytes */
147 /* Pending list size, usually set to the sum of the size of all IQs */
148 uint32_t pending_list_size;
151 /** The instruction (input) queue.
152 * The input queue is used to post raw (instruction) mode data or packet data
153 * to OCTEON TX2 device from the host. Each IQ of a OTX_EP EP VF device has one
154 * such structure to represent it.
156 struct otx_ep_instr_queue {
157 struct otx_ep_device *otx_ep_dev;
160 uint32_t pkt_in_done;
162 /* Flag for 64 byte commands. */
163 uint32_t iqcmd_64B:1;
167 /* Number of descriptors in this ring. */
170 /* Input ring index, where the driver should write the next packet */
171 uint32_t host_write_index;
173 /* Input ring index, where the OCTEON TX2 should read the next packet */
174 uint32_t otx_read_index;
176 uint32_t reset_instr_cnt;
178 /** This index aids in finding the window in the queue where OCTEON TX2
179 * has read the commands.
181 uint32_t flush_index;
183 /* This keeps track of the instructions pending in this queue. */
184 uint64_t instr_pending;
186 /* Pointer to the Virtual Base addr of the input ring. */
189 /* This IQ request list */
190 struct otx_ep_instr_list *req_list;
192 /* OTX_EP doorbell register for the ring. */
195 /* OTX_EP instruction count register for this ring. */
198 /* Number of instructions pending to be posted to OCTEON TX2. */
201 /* Statistics for this input queue. */
202 struct otx_ep_iq_stats stats;
204 /* DMA mapped base address of the input descriptor ring. */
205 uint64_t base_addr_dma;
208 const struct rte_memzone *iq_mz;
211 /** Descriptor format.
212 * The descriptor ring is made of descriptors which have 2 64-bit values:
213 * -# Physical (bus) address of the data buffer.
214 * -# Physical (bus) address of a otx_ep_droq_info structure.
215 * The device DMA's incoming packets and its information at the address
216 * given by these descriptor fields.
218 struct otx_ep_droq_desc {
219 /* The buffer pointer */
222 /* The Info pointer */
225 #define OTX_EP_DROQ_DESC_SIZE (sizeof(struct otx_ep_droq_desc))
231 #define OTX_EP_RH_SIZE (sizeof(union otx_ep_rh))
233 /** Information about packet DMA'ed by OCTEON TX2.
234 * The format of the information available at Info Pointer after OCTEON TX2
235 * has posted a packet. Not all descriptors have valid information. Only
236 * the Info field of the first descriptor for a packet has information
239 struct otx_ep_droq_info {
240 /* The Length of the packet. */
243 /* The Output Receive Header. */
246 #define OTX_EP_DROQ_INFO_SIZE (sizeof(struct otx_ep_droq_info))
248 /* DROQ statistics. Each output queue has four stats fields. */
249 struct otx_ep_droq_stats {
250 /* Number of packets received in this queue. */
251 uint64_t pkts_received;
253 /* Bytes received by this queue. */
254 uint64_t bytes_received;
256 /* Num of failures of rte_pktmbuf_alloc() */
257 uint64_t rx_alloc_failure;
262 /* packets with data got ready after interrupt arrived */
263 uint64_t pkts_delayed_data;
265 /* packets dropped due to zero length */
266 uint64_t dropped_zlp;
269 /* Structure to define the configuration attributes for each Output queue. */
270 struct otx_ep_oq_config {
271 /* Max number of OQs available */
274 /* If set, the Output queue uses info-pointer mode. (Default: 1 ) */
277 /** The number of buffers that were consumed during packet processing by
278 * the driver on this Output queue before the driver attempts to
279 * replenish the descriptor ring with new buffers.
281 uint32_t refill_threshold;
284 /* The Descriptor Ring Output Queue(DROQ) structure. */
286 struct otx_ep_device *otx_ep_dev;
287 /* The 8B aligned descriptor ring starts at this address. */
288 struct otx_ep_droq_desc *desc_ring;
291 uint64_t last_pkt_count;
293 struct rte_mempool *mpool;
295 /* Driver should read the next packet at this index */
298 /* OCTEON TX2 will write the next packet at this index */
301 /* At this index, the driver will refill the descriptor's buffer */
304 /* Packets pending to be processed */
305 uint64_t pkts_pending;
307 /* Number of descriptors in this ring. */
310 /* The number of descriptors pending to refill. */
311 uint32_t refill_count;
313 uint32_t refill_threshold;
315 /* The 8B aligned info ptrs begin from this address. */
316 struct otx_ep_droq_info *info_list;
318 /* receive buffer list contains mbuf ptr list */
319 struct rte_mbuf **recv_buf_list;
321 /* The size of each buffer pointed by the buffer pointer. */
322 uint32_t buffer_size;
324 /** Pointer to the mapped packet credit register.
325 * Host writes number of info/buffer ptrs available to this register
327 void *pkts_credit_reg;
329 /** Pointer to the mapped packet sent register. OCTEON TX2 writes the
330 * number of packets DMA'ed to host memory in this register.
334 /* Statistics for this DROQ. */
335 struct otx_ep_droq_stats stats;
337 /* DMA mapped address of the DROQ descriptor ring. */
338 size_t desc_ring_dma;
340 /* Info_ptr list is allocated at this virtual address. */
341 size_t info_base_addr;
343 /* DMA mapped address of the info list */
344 size_t info_list_dma;
346 /* Allocated size of info list. */
347 uint32_t info_alloc_size;
350 const struct rte_memzone *desc_ring_mz;
352 const struct rte_memzone *info_mz;
354 #define OTX_EP_DROQ_SIZE (sizeof(struct otx_ep_droq))
357 struct otx_ep_io_enable {
363 /* Structure to define the configuration. */
364 struct otx_ep_config {
365 /* Input Queue attributes. */
366 struct otx_ep_iq_config iq;
368 /* Output Queue attributes. */
369 struct otx_ep_oq_config oq;
371 /* Num of desc for IQ rings */
372 uint32_t num_iqdef_descs;
374 /* Num of desc for OQ rings */
375 uint32_t num_oqdef_descs;
378 uint32_t oqdef_buf_size;
381 /* SRIOV information */
382 struct otx_ep_sriov_info {
383 /* Number of rings assigned to VF */
384 uint32_t rings_per_vf;
386 /* Number of VF devices enabled */
390 /* Required functions for each VF device */
391 struct otx_ep_fn_list {
392 void (*setup_iq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);
394 void (*setup_oq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);
396 void (*setup_device_regs)(struct otx_ep_device *otx_ep);
398 int (*enable_io_queues)(struct otx_ep_device *otx_ep);
399 void (*disable_io_queues)(struct otx_ep_device *otx_ep);
401 int (*enable_iq)(struct otx_ep_device *otx_ep, uint32_t q_no);
402 void (*disable_iq)(struct otx_ep_device *otx_ep, uint32_t q_no);
404 int (*enable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no);
405 void (*disable_oq)(struct otx_ep_device *otx_ep, uint32_t q_no);
408 /* OTX_EP EP VF device data structure */
409 struct otx_ep_device {
410 /* PCI device pointer */
411 struct rte_pci_device *pdev;
417 struct rte_eth_dev *eth_dev;
421 /* Memory mapped h/w address */
424 struct otx_ep_fn_list fn_list;
426 uint32_t max_tx_queues;
428 uint32_t max_rx_queues;
431 uint32_t nb_tx_queues;
433 /* The input instruction queues */
434 struct otx_ep_instr_queue *instr_queue[OTX_EP_MAX_IOQS_PER_VF];
437 uint32_t nb_rx_queues;
439 /* The DROQ output queues */
440 struct otx_ep_droq *droq[OTX_EP_MAX_IOQS_PER_VF];
443 struct otx_ep_io_enable io_qmask;
446 struct otx_ep_sriov_info sriov_info;
448 /* Device configuration */
449 const struct otx_ep_config *conf;
451 uint64_t rx_offloads;
453 uint64_t tx_offloads;
456 int otx_ep_setup_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no,
457 int num_descs, unsigned int socket_id);
458 int otx_ep_delete_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no);
460 int otx_ep_setup_oqs(struct otx_ep_device *otx_ep, int oq_no, int num_descs,
461 int desc_size, struct rte_mempool *mpool,
462 unsigned int socket_id);
463 int otx_ep_delete_oqs(struct otx_ep_device *otx_ep, uint32_t oq_no);
465 struct otx_ep_sg_entry {
466 /** The first 64 bit gives the size of data in each dptr. */
472 /** The 4 dptr pointers for this entry. */
476 #define OTX_EP_SG_ENTRY_SIZE (sizeof(struct otx_ep_sg_entry))
478 /** Structure of a node in list of gather components maintained by
479 * driver for each network device.
481 struct otx_ep_gather {
482 /** number of gather entries. */
485 /** Gather component that can accommodate max sized fragment list
486 * received from the IP layer.
488 struct otx_ep_sg_entry *sg;
491 struct otx_ep_buf_free_info {
492 struct rte_mbuf *mbuf;
493 struct otx_ep_gather g;
496 #define OTX_EP_MAX_PKT_SZ 64000U
497 #define OTX_EP_MAX_MAC_ADDRS 1
498 #define OTX_EP_SG_ALIGN 8
499 #define OTX_EP_CLEAR_ISIZE_BSIZE 0x7FFFFFULL
500 #define OTX_EP_CLEAR_OUT_INT_LVLS 0x3FFFFFFFFFFFFFULL
501 #define OTX_EP_CLEAR_IN_INT_LVLS 0xFFFFFFFF
502 #define OTX_EP_CLEAR_SDP_IN_INT_LVLS 0x3FFFFFFFFFFFFFUL
503 #define OTX_EP_DROQ_BUFSZ_MASK 0xFFFF
504 #define OTX_EP_CLEAR_SLIST_DBELL 0xFFFFFFFF
505 #define OTX_EP_CLEAR_SDP_OUT_PKT_CNT 0xFFFFFFFFF
507 extern int otx_net_ep_logtype;
508 #endif /* _OTX_EP_COMMON_H_ */