1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #ifndef _OTX_EP_COMMON_H_
5 #define _OTX_EP_COMMON_H_
7 #define OTX_EP_MAX_RINGS_PER_VF (8)
8 #define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF
9 #define OTX_EP_64BYTE_INSTR (64)
10 #define OTX_EP_MAX_IQ_DESCRIPTORS (8192)
11 #define OTX_EP_MAX_OQ_DESCRIPTORS (8192)
12 #define OTX_EP_OQ_BUF_SIZE (2048)
14 #define OTX_EP_OQ_INFOPTR_MODE (0)
15 #define OTX_EP_OQ_REFIL_THRESHOLD (16)
17 #define otx_ep_info(fmt, args...) \
18 rte_log(RTE_LOG_INFO, otx_net_ep_logtype, \
19 "%s():%u " fmt "\n", \
20 __func__, __LINE__, ##args)
22 #define otx_ep_err(fmt, args...) \
23 rte_log(RTE_LOG_ERR, otx_net_ep_logtype, \
24 "%s():%u " fmt "\n", \
25 __func__, __LINE__, ##args)
27 #define otx_ep_dbg(fmt, args...) \
28 rte_log(RTE_LOG_DEBUG, otx_net_ep_logtype, \
29 "%s():%u " fmt "\n", \
30 __func__, __LINE__, ##args)
32 #define otx_ep_write64(value, base_addr, reg_off) \
34 typeof(value) val = (value); \
35 typeof(reg_off) off = (reg_off); \
36 otx_ep_dbg("octeon_write_csr64: reg: 0x%08lx val: 0x%016llx\n", \
37 (unsigned long)off, (unsigned long long)val); \
38 rte_write64(val, ((base_addr) + off)); \
43 /* Structure to define the configuration attributes for each Input queue. */
44 struct otx_ep_iq_config {
45 /* Max number of IQs available */
48 /* Command size - 32 or 64 bytes */
51 /* Pending list size, usually set to the sum of the size of all IQs */
52 uint32_t pending_list_size;
55 /* Structure to define the configuration attributes for each Output queue. */
56 struct otx_ep_oq_config {
57 /* Max number of OQs available */
60 /* If set, the Output queue uses info-pointer mode. (Default: 1 ) */
63 /** The number of buffers that were consumed during packet processing by
64 * the driver on this Output queue before the driver attempts to
65 * replenish the descriptor ring with new buffers.
67 uint32_t refill_threshold;
70 /* Structure to define the configuration. */
71 struct otx_ep_config {
72 /* Input Queue attributes. */
73 struct otx_ep_iq_config iq;
75 /* Output Queue attributes. */
76 struct otx_ep_oq_config oq;
78 /* Num of desc for IQ rings */
79 uint32_t num_iqdef_descs;
81 /* Num of desc for OQ rings */
82 uint32_t num_oqdef_descs;
85 uint32_t oqdef_buf_size;
88 /* SRIOV information */
89 struct otx_ep_sriov_info {
90 /* Number of rings assigned to VF */
91 uint32_t rings_per_vf;
93 /* Number of VF devices enabled */
97 /* Required functions for each VF device */
98 struct otx_ep_fn_list {
99 void (*setup_device_regs)(struct otx_ep_device *otx_ep);
102 /* OTX_EP EP VF device data structure */
103 struct otx_ep_device {
104 /* PCI device pointer */
105 struct rte_pci_device *pdev;
109 struct rte_eth_dev *eth_dev;
113 /* Memory mapped h/w address */
116 struct otx_ep_fn_list fn_list;
119 struct otx_ep_sriov_info sriov_info;
121 /* Device configuration */
122 const struct otx_ep_config *conf;
125 extern int otx_net_ep_logtype;
126 #endif /* _OTX_EP_COMMON_H_ */