1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include <ethdev_pci.h>
7 #include "otx2_common.h"
8 #include "otx_ep_common.h"
10 #include "otx2_ep_vf.h"
11 #include "otx_ep_rxtx.h"
13 #define OTX_EP_DEV(_eth_dev) \
14 ((struct otx_ep_device *)(_eth_dev)->data->dev_private)
16 static const struct rte_eth_desc_lim otx_ep_rx_desc_lim = {
17 .nb_max = OTX_EP_MAX_OQ_DESCRIPTORS,
18 .nb_min = OTX_EP_MIN_OQ_DESCRIPTORS,
19 .nb_align = OTX_EP_RXD_ALIGN,
22 static const struct rte_eth_desc_lim otx_ep_tx_desc_lim = {
23 .nb_max = OTX_EP_MAX_IQ_DESCRIPTORS,
24 .nb_min = OTX_EP_MIN_IQ_DESCRIPTORS,
25 .nb_align = OTX_EP_TXD_ALIGN,
29 otx_ep_dev_info_get(struct rte_eth_dev *eth_dev,
30 struct rte_eth_dev_info *devinfo)
32 struct otx_ep_device *otx_epvf;
34 otx_epvf = OTX_EP_DEV(eth_dev);
36 devinfo->speed_capa = RTE_ETH_LINK_SPEED_10G;
37 devinfo->max_rx_queues = otx_epvf->max_rx_queues;
38 devinfo->max_tx_queues = otx_epvf->max_tx_queues;
40 devinfo->min_rx_bufsize = OTX_EP_MIN_RX_BUF_SIZE;
41 devinfo->max_rx_pktlen = OTX_EP_MAX_PKT_SZ;
42 devinfo->rx_offload_capa = RTE_ETH_RX_OFFLOAD_SCATTER;
43 devinfo->tx_offload_capa = RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
45 devinfo->max_mac_addrs = OTX_EP_MAX_MAC_ADDRS;
47 devinfo->rx_desc_lim = otx_ep_rx_desc_lim;
48 devinfo->tx_desc_lim = otx_ep_tx_desc_lim;
54 otx_ep_dev_start(struct rte_eth_dev *eth_dev)
56 struct otx_ep_device *otx_epvf;
60 otx_epvf = (struct otx_ep_device *)OTX_EP_DEV(eth_dev);
61 /* Enable IQ/OQ for this device */
62 ret = otx_epvf->fn_list.enable_io_queues(otx_epvf);
64 otx_ep_err("IOQ enable failed\n");
68 for (q = 0; q < otx_epvf->nb_rx_queues; q++) {
69 rte_write32(otx_epvf->droq[q]->nb_desc,
70 otx_epvf->droq[q]->pkts_credit_reg);
73 otx_ep_info("OQ[%d] dbells [%d]\n", q,
74 rte_read32(otx_epvf->droq[q]->pkts_credit_reg));
77 otx_ep_info("dev started\n");
82 /* Stop device and disable input/output functions */
84 otx_ep_dev_stop(struct rte_eth_dev *eth_dev)
86 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
88 otx_epvf->fn_list.disable_io_queues(otx_epvf);
94 otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)
96 struct rte_pci_device *pdev = otx_epvf->pdev;
97 uint32_t dev_id = pdev->id.device_id;
101 case PCI_DEVID_OCTEONTX_EP_VF:
102 otx_epvf->chip_id = dev_id;
103 ret = otx_ep_vf_setup_device(otx_epvf);
104 otx_epvf->fn_list.disable_io_queues(otx_epvf);
106 case PCI_DEVID_OCTEONTX2_EP_NET_VF:
107 case PCI_DEVID_CN98XX_EP_NET_VF:
108 otx_epvf->chip_id = dev_id;
109 ret = otx2_ep_vf_setup_device(otx_epvf);
110 otx_epvf->fn_list.disable_io_queues(otx_epvf);
113 otx_ep_err("Unsupported device\n");
118 otx_ep_info("OTX_EP dev_id[%d]\n", dev_id);
123 /* OTX_EP VF device initialization */
125 otx_epdev_init(struct otx_ep_device *otx_epvf)
127 uint32_t ethdev_queues;
130 ret = otx_ep_chip_specific_setup(otx_epvf);
132 otx_ep_err("Chip specific setup failed\n");
136 otx_epvf->fn_list.setup_device_regs(otx_epvf);
138 otx_epvf->eth_dev->rx_pkt_burst = &otx_ep_recv_pkts;
139 if (otx_epvf->chip_id == PCI_DEVID_OCTEONTX_EP_VF)
140 otx_epvf->eth_dev->tx_pkt_burst = &otx_ep_xmit_pkts;
141 else if (otx_epvf->chip_id == PCI_DEVID_OCTEONTX2_EP_NET_VF ||
142 otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF)
143 otx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;
144 ethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);
145 otx_epvf->max_rx_queues = ethdev_queues;
146 otx_epvf->max_tx_queues = ethdev_queues;
148 otx_ep_info("OTX_EP Device is Ready\n");
155 otx_ep_dev_configure(struct rte_eth_dev *eth_dev)
157 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
158 struct rte_eth_dev_data *data = eth_dev->data;
159 struct rte_eth_rxmode *rxmode;
160 struct rte_eth_txmode *txmode;
161 struct rte_eth_conf *conf;
163 conf = &data->dev_conf;
164 rxmode = &conf->rxmode;
165 txmode = &conf->txmode;
166 if (eth_dev->data->nb_rx_queues > otx_epvf->max_rx_queues ||
167 eth_dev->data->nb_tx_queues > otx_epvf->max_tx_queues) {
168 otx_ep_err("invalid num queues\n");
171 otx_ep_info("OTX_EP Device is configured with num_txq %d num_rxq %d\n",
172 eth_dev->data->nb_rx_queues, eth_dev->data->nb_tx_queues);
174 otx_epvf->rx_offloads = rxmode->offloads;
175 otx_epvf->tx_offloads = txmode->offloads;
181 * Setup our receive queue/ringbuffer. This is the
182 * queue the Octeon uses to send us packets and
183 * responses. We are given a memory pool for our
184 * packet buffers that are used to populate the receive
188 * Pointer to the structure rte_eth_dev
191 * @param num_rx_descs
192 * Number of entries in the queue
194 * Where to allocate memory
196 * Pointer to the struction rte_eth_rxconf
198 * Pointer to the packet pool
201 * - On success, return 0
202 * - On failure, return -1
205 otx_ep_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t q_no,
206 uint16_t num_rx_descs, unsigned int socket_id,
207 const struct rte_eth_rxconf *rx_conf __rte_unused,
208 struct rte_mempool *mp)
210 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
211 struct rte_pktmbuf_pool_private *mbp_priv;
214 if (q_no >= otx_epvf->max_rx_queues) {
215 otx_ep_err("Invalid rx queue number %u\n", q_no);
219 if (num_rx_descs & (num_rx_descs - 1)) {
220 otx_ep_err("Invalid rx desc number should be pow 2 %u\n",
224 if (num_rx_descs < (SDP_GBL_WMARK * 8)) {
225 otx_ep_err("Invalid rx desc number should at least be greater than 8xwmark %u\n",
230 otx_ep_dbg("setting up rx queue %u\n", q_no);
232 mbp_priv = rte_mempool_get_priv(mp);
233 buf_size = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
235 if (otx_ep_setup_oqs(otx_epvf, q_no, num_rx_descs, buf_size, mp,
237 otx_ep_err("droq allocation failed\n");
241 eth_dev->data->rx_queues[q_no] = otx_epvf->droq[q_no];
247 * Release the receive queue/ringbuffer. Called by
251 * Pointer to Ethernet device structure.
253 * Receive queue index.
259 otx_ep_rx_queue_release(struct rte_eth_dev *dev, uint16_t q_no)
261 struct otx_ep_droq *rq = dev->data->rx_queues[q_no];
262 struct otx_ep_device *otx_epvf = rq->otx_ep_dev;
265 if (otx_ep_delete_oqs(otx_epvf, q_id))
266 otx_ep_err("Failed to delete OQ:%d\n", q_id);
270 * Allocate and initialize SW ring. Initialize associated HW registers.
273 * Pointer to structure rte_eth_dev
278 * @param num_tx_descs
279 * Number of ringbuffer descriptors
282 * NUMA socket id, used for memory allocations
285 * Pointer to the structure rte_eth_txconf
288 * - On success, return 0
289 * - On failure, return -errno value
292 otx_ep_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t q_no,
293 uint16_t num_tx_descs, unsigned int socket_id,
294 const struct rte_eth_txconf *tx_conf __rte_unused)
296 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
299 if (q_no >= otx_epvf->max_tx_queues) {
300 otx_ep_err("Invalid tx queue number %u\n", q_no);
303 if (num_tx_descs & (num_tx_descs - 1)) {
304 otx_ep_err("Invalid tx desc number should be pow 2 %u\n",
309 retval = otx_ep_setup_iqs(otx_epvf, q_no, num_tx_descs, socket_id);
312 otx_ep_err("IQ(TxQ) creation failed.\n");
316 eth_dev->data->tx_queues[q_no] = otx_epvf->instr_queue[q_no];
317 otx_ep_dbg("tx queue[%d] setup\n", q_no);
322 * Release the transmit queue/ringbuffer. Called by
326 * Pointer to Ethernet device structure.
328 * Transmit queue index.
334 otx_ep_tx_queue_release(struct rte_eth_dev *dev, uint16_t q_no)
336 struct otx_ep_instr_queue *tq = dev->data->tx_queues[q_no];
338 otx_ep_delete_iqs(tq->otx_ep_dev, tq->q_no);
341 /* Define our ethernet definitions */
342 static const struct eth_dev_ops otx_ep_eth_dev_ops = {
343 .dev_configure = otx_ep_dev_configure,
344 .dev_start = otx_ep_dev_start,
345 .dev_stop = otx_ep_dev_stop,
346 .rx_queue_setup = otx_ep_rx_queue_setup,
347 .rx_queue_release = otx_ep_rx_queue_release,
348 .tx_queue_setup = otx_ep_tx_queue_setup,
349 .tx_queue_release = otx_ep_tx_queue_release,
350 .dev_infos_get = otx_ep_dev_info_get,
354 otx_epdev_exit(struct rte_eth_dev *eth_dev)
356 struct otx_ep_device *otx_epvf;
357 uint32_t num_queues, q;
359 otx_ep_info("%s:\n", __func__);
361 otx_epvf = OTX_EP_DEV(eth_dev);
363 otx_epvf->fn_list.disable_io_queues(otx_epvf);
365 num_queues = otx_epvf->nb_rx_queues;
366 for (q = 0; q < num_queues; q++) {
367 if (otx_ep_delete_oqs(otx_epvf, q)) {
368 otx_ep_err("Failed to delete OQ:%d\n", q);
372 otx_ep_info("Num OQs:%d freed\n", otx_epvf->nb_rx_queues);
374 num_queues = otx_epvf->nb_tx_queues;
375 for (q = 0; q < num_queues; q++) {
376 if (otx_ep_delete_iqs(otx_epvf, q)) {
377 otx_ep_err("Failed to delete IQ:%d\n", q);
381 otx_ep_dbg("Num IQs:%d freed\n", otx_epvf->nb_tx_queues);
387 otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev)
389 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
391 otx_epdev_exit(eth_dev);
393 eth_dev->dev_ops = NULL;
394 eth_dev->rx_pkt_burst = NULL;
395 eth_dev->tx_pkt_burst = NULL;
401 otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)
403 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
404 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
405 struct rte_ether_addr vf_mac_addr;
407 /* Single process support */
408 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
411 otx_epvf->eth_dev = eth_dev;
412 otx_epvf->port_id = eth_dev->data->port_id;
413 eth_dev->dev_ops = &otx_ep_eth_dev_ops;
414 eth_dev->data->mac_addrs = rte_zmalloc("otx_ep", RTE_ETHER_ADDR_LEN, 0);
415 if (eth_dev->data->mac_addrs == NULL) {
416 otx_ep_err("MAC addresses memory allocation failed\n");
417 eth_dev->dev_ops = NULL;
420 rte_eth_random_addr(vf_mac_addr.addr_bytes);
421 rte_ether_addr_copy(&vf_mac_addr, eth_dev->data->mac_addrs);
422 otx_epvf->hw_addr = pdev->mem_resource[0].addr;
423 otx_epvf->pdev = pdev;
425 otx_epdev_init(otx_epvf);
426 if (pdev->id.device_id == PCI_DEVID_OCTEONTX2_EP_NET_VF)
427 otx_epvf->pkind = SDP_OTX2_PKIND;
429 otx_epvf->pkind = SDP_PKIND;
430 otx_ep_info("using pkind %d\n", otx_epvf->pkind);
436 otx_ep_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
437 struct rte_pci_device *pci_dev)
439 return rte_eth_dev_pci_generic_probe(pci_dev,
440 sizeof(struct otx_ep_device),
441 otx_ep_eth_dev_init);
445 otx_ep_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
447 return rte_eth_dev_pci_generic_remove(pci_dev,
448 otx_ep_eth_dev_uninit);
451 /* Set of PCI devices this driver supports */
452 static const struct rte_pci_id pci_id_otx_ep_map[] = {
453 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX_EP_VF) },
454 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_EP_NET_VF) },
455 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN98XX_EP_NET_VF) },
456 { .vendor_id = 0, /* sentinel */ }
459 static struct rte_pci_driver rte_otx_ep_pmd = {
460 .id_table = pci_id_otx_ep_map,
461 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
462 .probe = otx_ep_eth_dev_pci_probe,
463 .remove = otx_ep_eth_dev_pci_remove,
466 RTE_PMD_REGISTER_PCI(net_otx_ep, rte_otx_ep_pmd);
467 RTE_PMD_REGISTER_PCI_TABLE(net_otx_ep, pci_id_otx_ep_map);
468 RTE_PMD_REGISTER_KMOD_DEP(net_otx_ep, "* igb_uio | vfio-pci");
469 RTE_LOG_REGISTER_DEFAULT(otx_net_ep_logtype, NOTICE);