1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include <ethdev_pci.h>
7 #include "otx2_common.h"
8 #include "otx_ep_common.h"
10 #include "otx2_ep_vf.h"
12 #define OTX_EP_DEV(_eth_dev) ((_eth_dev)->data->dev_private)
14 otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)
16 struct rte_pci_device *pdev = otx_epvf->pdev;
17 uint32_t dev_id = pdev->id.device_id;
21 case PCI_DEVID_OCTEONTX_EP_VF:
22 otx_epvf->chip_id = dev_id;
23 ret = otx_ep_vf_setup_device(otx_epvf);
25 case PCI_DEVID_OCTEONTX2_EP_NET_VF:
26 case PCI_DEVID_CN98XX_EP_NET_VF:
27 otx_epvf->chip_id = dev_id;
28 ret = otx2_ep_vf_setup_device(otx_epvf);
31 otx_ep_err("Unsupported device\n");
36 otx_ep_info("OTX_EP dev_id[%d]\n", dev_id);
41 /* OTX_EP VF device initialization */
43 otx_epdev_init(struct otx_ep_device *otx_epvf)
47 ret = otx_ep_chip_specific_setup(otx_epvf);
49 otx_ep_err("Chip specific setup failed\n");
53 otx_epvf->fn_list.setup_device_regs(otx_epvf);
55 otx_ep_info("OTX_EP Device is Ready\n");
62 otx_ep_eth_dev_uninit(__rte_unused struct rte_eth_dev *eth_dev)
68 otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)
70 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
71 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
72 struct rte_ether_addr vf_mac_addr;
74 /* Single process support */
75 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
78 otx_epvf->eth_dev = eth_dev;
79 otx_epvf->port_id = eth_dev->data->port_id;
80 eth_dev->data->mac_addrs = rte_zmalloc("otx_ep", RTE_ETHER_ADDR_LEN, 0);
81 if (eth_dev->data->mac_addrs == NULL) {
82 otx_ep_err("MAC addresses memory allocation failed\n");
85 rte_eth_random_addr(vf_mac_addr.addr_bytes);
86 rte_ether_addr_copy(&vf_mac_addr, eth_dev->data->mac_addrs);
87 otx_epvf->hw_addr = pdev->mem_resource[0].addr;
88 otx_epvf->pdev = pdev;
90 otx_epdev_init(otx_epvf);
96 otx_ep_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
97 struct rte_pci_device *pci_dev)
99 return rte_eth_dev_pci_generic_probe(pci_dev,
100 sizeof(struct otx_ep_device),
101 otx_ep_eth_dev_init);
105 otx_ep_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
107 return rte_eth_dev_pci_generic_remove(pci_dev,
108 otx_ep_eth_dev_uninit);
111 /* Set of PCI devices this driver supports */
112 static const struct rte_pci_id pci_id_otx_ep_map[] = {
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX_EP_VF) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_EP_NET_VF) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN98XX_EP_NET_VF) },
116 { .vendor_id = 0, /* sentinel */ }
119 static struct rte_pci_driver rte_otx_ep_pmd = {
120 .id_table = pci_id_otx_ep_map,
121 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
122 .probe = otx_ep_eth_dev_pci_probe,
123 .remove = otx_ep_eth_dev_pci_remove,
126 RTE_PMD_REGISTER_PCI(net_otx_ep, rte_otx_ep_pmd);
127 RTE_PMD_REGISTER_PCI_TABLE(net_otx_ep, pci_id_otx_ep_map);
128 RTE_PMD_REGISTER_KMOD_DEP(net_otx_ep, "* igb_uio | vfio-pci");
129 RTE_LOG_REGISTER(otx_net_ep_logtype, pmd.net.octeontx_ep, NOTICE);