1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include <ethdev_pci.h>
7 #include "otx_ep_common.h"
9 #include "otx2_ep_vf.h"
10 #include "otx_ep_rxtx.h"
12 #define OTX_EP_DEV(_eth_dev) \
13 ((struct otx_ep_device *)(_eth_dev)->data->dev_private)
15 static const struct rte_eth_desc_lim otx_ep_rx_desc_lim = {
16 .nb_max = OTX_EP_MAX_OQ_DESCRIPTORS,
17 .nb_min = OTX_EP_MIN_OQ_DESCRIPTORS,
18 .nb_align = OTX_EP_RXD_ALIGN,
21 static const struct rte_eth_desc_lim otx_ep_tx_desc_lim = {
22 .nb_max = OTX_EP_MAX_IQ_DESCRIPTORS,
23 .nb_min = OTX_EP_MIN_IQ_DESCRIPTORS,
24 .nb_align = OTX_EP_TXD_ALIGN,
28 otx_ep_dev_info_get(struct rte_eth_dev *eth_dev,
29 struct rte_eth_dev_info *devinfo)
31 struct otx_ep_device *otx_epvf;
33 otx_epvf = OTX_EP_DEV(eth_dev);
35 devinfo->speed_capa = RTE_ETH_LINK_SPEED_10G;
36 devinfo->max_rx_queues = otx_epvf->max_rx_queues;
37 devinfo->max_tx_queues = otx_epvf->max_tx_queues;
39 devinfo->min_rx_bufsize = OTX_EP_MIN_RX_BUF_SIZE;
40 devinfo->max_rx_pktlen = OTX_EP_MAX_PKT_SZ;
41 devinfo->rx_offload_capa = RTE_ETH_RX_OFFLOAD_SCATTER;
42 devinfo->tx_offload_capa = RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
44 devinfo->max_mac_addrs = OTX_EP_MAX_MAC_ADDRS;
46 devinfo->rx_desc_lim = otx_ep_rx_desc_lim;
47 devinfo->tx_desc_lim = otx_ep_tx_desc_lim;
53 otx_ep_dev_start(struct rte_eth_dev *eth_dev)
55 struct otx_ep_device *otx_epvf;
59 otx_epvf = (struct otx_ep_device *)OTX_EP_DEV(eth_dev);
60 /* Enable IQ/OQ for this device */
61 ret = otx_epvf->fn_list.enable_io_queues(otx_epvf);
63 otx_ep_err("IOQ enable failed\n");
67 for (q = 0; q < otx_epvf->nb_rx_queues; q++) {
68 rte_write32(otx_epvf->droq[q]->nb_desc,
69 otx_epvf->droq[q]->pkts_credit_reg);
72 otx_ep_info("OQ[%d] dbells [%d]\n", q,
73 rte_read32(otx_epvf->droq[q]->pkts_credit_reg));
76 otx_ep_info("dev started\n");
81 /* Stop device and disable input/output functions */
83 otx_ep_dev_stop(struct rte_eth_dev *eth_dev)
85 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
87 otx_epvf->fn_list.disable_io_queues(otx_epvf);
93 otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)
95 struct rte_pci_device *pdev = otx_epvf->pdev;
96 uint32_t dev_id = pdev->id.device_id;
100 case PCI_DEVID_OCTEONTX_EP_VF:
101 otx_epvf->chip_id = dev_id;
102 ret = otx_ep_vf_setup_device(otx_epvf);
103 otx_epvf->fn_list.disable_io_queues(otx_epvf);
105 case PCI_DEVID_CN9K_EP_NET_VF:
106 case PCI_DEVID_CN98XX_EP_NET_VF:
107 otx_epvf->chip_id = dev_id;
108 ret = otx2_ep_vf_setup_device(otx_epvf);
109 otx_epvf->fn_list.disable_io_queues(otx_epvf);
112 otx_ep_err("Unsupported device\n");
117 otx_ep_info("OTX_EP dev_id[%d]\n", dev_id);
122 /* OTX_EP VF device initialization */
124 otx_epdev_init(struct otx_ep_device *otx_epvf)
126 uint32_t ethdev_queues;
129 ret = otx_ep_chip_specific_setup(otx_epvf);
131 otx_ep_err("Chip specific setup failed\n");
135 otx_epvf->fn_list.setup_device_regs(otx_epvf);
137 otx_epvf->eth_dev->rx_pkt_burst = &otx_ep_recv_pkts;
138 if (otx_epvf->chip_id == PCI_DEVID_OCTEONTX_EP_VF)
139 otx_epvf->eth_dev->tx_pkt_burst = &otx_ep_xmit_pkts;
140 else if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF ||
141 otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF)
142 otx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;
143 ethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);
144 otx_epvf->max_rx_queues = ethdev_queues;
145 otx_epvf->max_tx_queues = ethdev_queues;
147 otx_ep_info("OTX_EP Device is Ready\n");
154 otx_ep_dev_configure(struct rte_eth_dev *eth_dev)
156 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
157 struct rte_eth_dev_data *data = eth_dev->data;
158 struct rte_eth_rxmode *rxmode;
159 struct rte_eth_txmode *txmode;
160 struct rte_eth_conf *conf;
162 conf = &data->dev_conf;
163 rxmode = &conf->rxmode;
164 txmode = &conf->txmode;
165 if (eth_dev->data->nb_rx_queues > otx_epvf->max_rx_queues ||
166 eth_dev->data->nb_tx_queues > otx_epvf->max_tx_queues) {
167 otx_ep_err("invalid num queues\n");
170 otx_ep_info("OTX_EP Device is configured with num_txq %d num_rxq %d\n",
171 eth_dev->data->nb_rx_queues, eth_dev->data->nb_tx_queues);
173 otx_epvf->rx_offloads = rxmode->offloads;
174 otx_epvf->tx_offloads = txmode->offloads;
180 * Setup our receive queue/ringbuffer. This is the
181 * queue the Octeon uses to send us packets and
182 * responses. We are given a memory pool for our
183 * packet buffers that are used to populate the receive
187 * Pointer to the structure rte_eth_dev
190 * @param num_rx_descs
191 * Number of entries in the queue
193 * Where to allocate memory
195 * Pointer to the struction rte_eth_rxconf
197 * Pointer to the packet pool
200 * - On success, return 0
201 * - On failure, return -1
204 otx_ep_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t q_no,
205 uint16_t num_rx_descs, unsigned int socket_id,
206 const struct rte_eth_rxconf *rx_conf __rte_unused,
207 struct rte_mempool *mp)
209 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
210 struct rte_pktmbuf_pool_private *mbp_priv;
213 if (q_no >= otx_epvf->max_rx_queues) {
214 otx_ep_err("Invalid rx queue number %u\n", q_no);
218 if (num_rx_descs & (num_rx_descs - 1)) {
219 otx_ep_err("Invalid rx desc number should be pow 2 %u\n",
223 if (num_rx_descs < (SDP_GBL_WMARK * 8)) {
224 otx_ep_err("Invalid rx desc number should at least be greater than 8xwmark %u\n",
229 otx_ep_dbg("setting up rx queue %u\n", q_no);
231 mbp_priv = rte_mempool_get_priv(mp);
232 buf_size = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
234 if (otx_ep_setup_oqs(otx_epvf, q_no, num_rx_descs, buf_size, mp,
236 otx_ep_err("droq allocation failed\n");
240 eth_dev->data->rx_queues[q_no] = otx_epvf->droq[q_no];
246 * Release the receive queue/ringbuffer. Called by
250 * Pointer to Ethernet device structure.
252 * Receive queue index.
258 otx_ep_rx_queue_release(struct rte_eth_dev *dev, uint16_t q_no)
260 struct otx_ep_droq *rq = dev->data->rx_queues[q_no];
261 struct otx_ep_device *otx_epvf = rq->otx_ep_dev;
264 if (otx_ep_delete_oqs(otx_epvf, q_id))
265 otx_ep_err("Failed to delete OQ:%d\n", q_id);
269 * Allocate and initialize SW ring. Initialize associated HW registers.
272 * Pointer to structure rte_eth_dev
277 * @param num_tx_descs
278 * Number of ringbuffer descriptors
281 * NUMA socket id, used for memory allocations
284 * Pointer to the structure rte_eth_txconf
287 * - On success, return 0
288 * - On failure, return -errno value
291 otx_ep_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t q_no,
292 uint16_t num_tx_descs, unsigned int socket_id,
293 const struct rte_eth_txconf *tx_conf __rte_unused)
295 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
298 if (q_no >= otx_epvf->max_tx_queues) {
299 otx_ep_err("Invalid tx queue number %u\n", q_no);
302 if (num_tx_descs & (num_tx_descs - 1)) {
303 otx_ep_err("Invalid tx desc number should be pow 2 %u\n",
308 retval = otx_ep_setup_iqs(otx_epvf, q_no, num_tx_descs, socket_id);
311 otx_ep_err("IQ(TxQ) creation failed.\n");
315 eth_dev->data->tx_queues[q_no] = otx_epvf->instr_queue[q_no];
316 otx_ep_dbg("tx queue[%d] setup\n", q_no);
321 * Release the transmit queue/ringbuffer. Called by
325 * Pointer to Ethernet device structure.
327 * Transmit queue index.
333 otx_ep_tx_queue_release(struct rte_eth_dev *dev, uint16_t q_no)
335 struct otx_ep_instr_queue *tq = dev->data->tx_queues[q_no];
337 otx_ep_delete_iqs(tq->otx_ep_dev, tq->q_no);
340 /* Define our ethernet definitions */
341 static const struct eth_dev_ops otx_ep_eth_dev_ops = {
342 .dev_configure = otx_ep_dev_configure,
343 .dev_start = otx_ep_dev_start,
344 .dev_stop = otx_ep_dev_stop,
345 .rx_queue_setup = otx_ep_rx_queue_setup,
346 .rx_queue_release = otx_ep_rx_queue_release,
347 .tx_queue_setup = otx_ep_tx_queue_setup,
348 .tx_queue_release = otx_ep_tx_queue_release,
349 .dev_infos_get = otx_ep_dev_info_get,
353 otx_epdev_exit(struct rte_eth_dev *eth_dev)
355 struct otx_ep_device *otx_epvf;
356 uint32_t num_queues, q;
358 otx_ep_info("%s:\n", __func__);
360 otx_epvf = OTX_EP_DEV(eth_dev);
362 otx_epvf->fn_list.disable_io_queues(otx_epvf);
364 num_queues = otx_epvf->nb_rx_queues;
365 for (q = 0; q < num_queues; q++) {
366 if (otx_ep_delete_oqs(otx_epvf, q)) {
367 otx_ep_err("Failed to delete OQ:%d\n", q);
371 otx_ep_info("Num OQs:%d freed\n", otx_epvf->nb_rx_queues);
373 num_queues = otx_epvf->nb_tx_queues;
374 for (q = 0; q < num_queues; q++) {
375 if (otx_ep_delete_iqs(otx_epvf, q)) {
376 otx_ep_err("Failed to delete IQ:%d\n", q);
380 otx_ep_dbg("Num IQs:%d freed\n", otx_epvf->nb_tx_queues);
386 otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev)
388 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
390 otx_epdev_exit(eth_dev);
392 eth_dev->dev_ops = NULL;
393 eth_dev->rx_pkt_burst = NULL;
394 eth_dev->tx_pkt_burst = NULL;
400 otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)
402 struct rte_pci_device *pdev = RTE_ETH_DEV_TO_PCI(eth_dev);
403 struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
404 struct rte_ether_addr vf_mac_addr;
406 /* Single process support */
407 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
410 otx_epvf->eth_dev = eth_dev;
411 otx_epvf->port_id = eth_dev->data->port_id;
412 eth_dev->dev_ops = &otx_ep_eth_dev_ops;
413 eth_dev->data->mac_addrs = rte_zmalloc("otx_ep", RTE_ETHER_ADDR_LEN, 0);
414 if (eth_dev->data->mac_addrs == NULL) {
415 otx_ep_err("MAC addresses memory allocation failed\n");
416 eth_dev->dev_ops = NULL;
419 rte_eth_random_addr(vf_mac_addr.addr_bytes);
420 rte_ether_addr_copy(&vf_mac_addr, eth_dev->data->mac_addrs);
421 otx_epvf->hw_addr = pdev->mem_resource[0].addr;
422 otx_epvf->pdev = pdev;
424 otx_epdev_init(otx_epvf);
425 if (pdev->id.device_id == PCI_DEVID_CN9K_EP_NET_VF)
426 otx_epvf->pkind = SDP_OTX2_PKIND;
428 otx_epvf->pkind = SDP_PKIND;
429 otx_ep_info("using pkind %d\n", otx_epvf->pkind);
435 otx_ep_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
436 struct rte_pci_device *pci_dev)
438 return rte_eth_dev_pci_generic_probe(pci_dev,
439 sizeof(struct otx_ep_device),
440 otx_ep_eth_dev_init);
444 otx_ep_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
446 return rte_eth_dev_pci_generic_remove(pci_dev,
447 otx_ep_eth_dev_uninit);
450 /* Set of PCI devices this driver supports */
451 static const struct rte_pci_id pci_id_otx_ep_map[] = {
452 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX_EP_VF) },
453 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN9K_EP_NET_VF) },
454 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN98XX_EP_NET_VF) },
455 { .vendor_id = 0, /* sentinel */ }
458 static struct rte_pci_driver rte_otx_ep_pmd = {
459 .id_table = pci_id_otx_ep_map,
460 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
461 .probe = otx_ep_eth_dev_pci_probe,
462 .remove = otx_ep_eth_dev_pci_remove,
465 RTE_PMD_REGISTER_PCI(net_otx_ep, rte_otx_ep_pmd);
466 RTE_PMD_REGISTER_PCI_TABLE(net_otx_ep, pci_id_otx_ep_map);
467 RTE_PMD_REGISTER_KMOD_DEP(net_otx_ep, "* igb_uio | vfio-pci");
468 RTE_LOG_REGISTER_DEFAULT(otx_net_ep_logtype, NOTICE);