1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
7 #define OTX_EP_RING_OFFSET (0x1ull << 17)
9 /* OTX_EP VF IQ Registers */
10 #define OTX_EP_R_IN_CONTROL_START (0x10000)
11 #define OTX_EP_R_IN_INSTR_BADDR_START (0x10020)
12 #define OTX_EP_R_IN_INSTR_RSIZE_START (0x10030)
13 #define OTX_EP_R_IN_INSTR_DBELL_START (0x10040)
14 #define OTX_EP_R_IN_CNTS_START (0x10050)
15 #define OTX_EP_R_IN_INT_LEVELS_START (0x10060)
17 #define OTX_EP_R_IN_CONTROL(ring) \
18 (OTX_EP_R_IN_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET))
20 #define OTX_EP_R_IN_INSTR_BADDR(ring) \
21 (OTX_EP_R_IN_INSTR_BADDR_START + ((ring) * OTX_EP_RING_OFFSET))
23 #define OTX_EP_R_IN_INSTR_RSIZE(ring) \
24 (OTX_EP_R_IN_INSTR_RSIZE_START + ((ring) * OTX_EP_RING_OFFSET))
26 #define OTX_EP_R_IN_INSTR_DBELL(ring) \
27 (OTX_EP_R_IN_INSTR_DBELL_START + ((ring) * OTX_EP_RING_OFFSET))
29 #define OTX_EP_R_IN_CNTS(ring) \
30 (OTX_EP_R_IN_CNTS_START + ((ring) * OTX_EP_RING_OFFSET))
32 #define OTX_EP_R_IN_INT_LEVELS(ring) \
33 (OTX_EP_R_IN_INT_LEVELS_START + ((ring) * OTX_EP_RING_OFFSET))
35 /* OTX_EP VF IQ Masks */
36 #define OTX_EP_R_IN_CTL_RPVF_MASK (0xF)
37 #define OTX_EP_R_IN_CTL_RPVF_POS (48)
39 #define OTX_EP_R_IN_CTL_IDLE (0x1ull << 28)
40 #define OTX_EP_R_IN_CTL_RDSIZE (0x3ull << 25) /* Setting to max(4) */
41 #define OTX_EP_R_IN_CTL_IS_64B (0x1ull << 24)
42 #define OTX_EP_R_IN_CTL_ESR (0x1ull << 1)
43 /* OTX_EP VF OQ Registers */
44 #define OTX_EP_R_OUT_CNTS_START (0x10100)
45 #define OTX_EP_R_OUT_INT_LEVELS_START (0x10110)
46 #define OTX_EP_R_OUT_SLIST_BADDR_START (0x10120)
47 #define OTX_EP_R_OUT_SLIST_RSIZE_START (0x10130)
48 #define OTX_EP_R_OUT_SLIST_DBELL_START (0x10140)
49 #define OTX_EP_R_OUT_CONTROL_START (0x10150)
50 #define OTX_EP_R_OUT_ENABLE_START (0x10160)
52 #define OTX_EP_R_OUT_CONTROL(ring) \
53 (OTX_EP_R_OUT_CONTROL_START + ((ring) * OTX_EP_RING_OFFSET))
55 #define OTX_EP_R_OUT_ENABLE(ring) \
56 (OTX_EP_R_OUT_ENABLE_START + ((ring) * OTX_EP_RING_OFFSET))
58 #define OTX_EP_R_OUT_SLIST_BADDR(ring) \
59 (OTX_EP_R_OUT_SLIST_BADDR_START + ((ring) * OTX_EP_RING_OFFSET))
61 #define OTX_EP_R_OUT_SLIST_RSIZE(ring) \
62 (OTX_EP_R_OUT_SLIST_RSIZE_START + ((ring) * OTX_EP_RING_OFFSET))
64 #define OTX_EP_R_OUT_SLIST_DBELL(ring) \
65 (OTX_EP_R_OUT_SLIST_DBELL_START + ((ring) * OTX_EP_RING_OFFSET))
67 #define OTX_EP_R_OUT_CNTS(ring) \
68 (OTX_EP_R_OUT_CNTS_START + ((ring) * OTX_EP_RING_OFFSET))
70 #define OTX_EP_R_OUT_INT_LEVELS(ring) \
71 (OTX_EP_R_OUT_INT_LEVELS_START + ((ring) * OTX_EP_RING_OFFSET))
73 /* OTX_EP VF OQ Masks */
75 #define OTX_EP_R_OUT_CTL_IDLE (1ull << 36)
76 #define OTX_EP_R_OUT_CTL_ES_I (1ull << 34)
77 #define OTX_EP_R_OUT_CTL_NSR_I (1ull << 33)
78 #define OTX_EP_R_OUT_CTL_ROR_I (1ull << 32)
79 #define OTX_EP_R_OUT_CTL_ES_D (1ull << 30)
80 #define OTX_EP_R_OUT_CTL_NSR_D (1ull << 29)
81 #define OTX_EP_R_OUT_CTL_ROR_D (1ull << 28)
82 #define OTX_EP_R_OUT_CTL_ES_P (1ull << 26)
83 #define OTX_EP_R_OUT_CTL_NSR_P (1ull << 25)
84 #define OTX_EP_R_OUT_CTL_ROR_P (1ull << 24)
85 #define OTX_EP_R_OUT_CTL_IMODE (1ull << 23)
87 #define PCI_DEVID_OCTEONTX_EP_VF 0xa303
89 /* this is a static value set by SLI PF driver in octeon
90 * No handshake is available
91 * Change this if changing the value in SLI PF driver
93 #define SDP_GBL_WMARK 0x100
96 otx_ep_vf_setup_device(struct otx_ep_device *otx_ep);
97 #endif /*_OTX_EP_VF_H_ */