1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018-2019 NXP
8 /* This file is for Ethernet MAC registers and offsets
11 #include <linux/ethtool.h>
13 #define EMAC_IEVENT_REG 0x004
14 #define EMAC_IMASK_REG 0x008
15 #define EMAC_R_DES_ACTIVE_REG 0x010
16 #define EMAC_X_DES_ACTIVE_REG 0x014
17 #define EMAC_ECNTRL_REG 0x024
18 #define EMAC_MII_DATA_REG 0x040
19 #define EMAC_MII_CTRL_REG 0x044
20 #define EMAC_MIB_CTRL_STS_REG 0x064
21 #define EMAC_RCNTRL_REG 0x084
22 #define EMAC_TCNTRL_REG 0x0C4
23 #define EMAC_PHY_ADDR_LOW 0x0E4
24 #define EMAC_PHY_ADDR_HIGH 0x0E8
25 #define EMAC_GAUR 0x120
26 #define EMAC_GALR 0x124
27 #define EMAC_TFWR_STR_FWD 0x144
28 #define EMAC_RX_SECTION_FULL 0x190
29 #define EMAC_RX_SECTION_EMPTY 0x194
30 #define EMAC_TX_SECTION_EMPTY 0x1A0
31 #define EMAC_TRUNC_FL 0x1B0
33 #define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */
34 #define RMON_T_PACKETS 0x204 /* RMON TX packet count */
35 #define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */
36 #define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */
37 #define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */
38 #define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */
39 #define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
40 #define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */
41 #define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
42 #define RMON_T_COL 0x224 /* RMON TX collision count */
43 #define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */
44 #define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */
45 #define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */
46 #define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */
47 #define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */
48 #define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */
49 #define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */
50 #define RMON_T_OCTETS 0x244 /* RMON TX octets */
51 #define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */
52 #define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */
53 #define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */
54 #define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */
55 #define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */
56 #define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */
57 #define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */
58 #define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */
59 #define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */
60 #define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */
61 #define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */
62 #define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */
63 #define RMON_R_PACKETS 0x284 /* RMON RX packet count */
64 #define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */
65 #define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */
66 #define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */
67 #define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */
68 #define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
69 #define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */
70 #define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
71 #define RMON_R_RESVD_O 0x2a4 /* Reserved */
72 #define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */
73 #define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */
74 #define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */
75 #define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */
76 #define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */
77 #define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */
78 #define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */
79 #define RMON_R_OCTETS 0x2c4 /* RMON RX octets */
80 #define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */
81 #define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */
82 #define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */
83 #define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */
84 #define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */
85 #define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */
86 #define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */
88 #define EMAC_SMAC_0_0 0x500 /*Supplemental MAC Address 0 (RW).*/
89 #define EMAC_SMAC_0_1 0x504 /*Supplemental MAC Address 0 (RW).*/
91 /* GEMAC definitions and settings */
96 /* GEMAC Bit definitions */
97 #define EMAC_IEVENT_HBERR 0x80000000
98 #define EMAC_IEVENT_BABR 0x40000000
99 #define EMAC_IEVENT_BABT 0x20000000
100 #define EMAC_IEVENT_GRA 0x10000000
101 #define EMAC_IEVENT_TXF 0x08000000
102 #define EMAC_IEVENT_TXB 0x04000000
103 #define EMAC_IEVENT_RXF 0x02000000
104 #define EMAC_IEVENT_RXB 0x01000000
105 #define EMAC_IEVENT_MII 0x00800000
106 #define EMAC_IEVENT_EBERR 0x00400000
107 #define EMAC_IEVENT_LC 0x00200000
108 #define EMAC_IEVENT_RL 0x00100000
109 #define EMAC_IEVENT_UN 0x00080000
111 #define EMAC_IMASK_HBERR 0x80000000
112 #define EMAC_IMASK_BABR 0x40000000
113 #define EMAC_IMASKT_BABT 0x20000000
114 #define EMAC_IMASK_GRA 0x10000000
115 #define EMAC_IMASKT_TXF 0x08000000
116 #define EMAC_IMASK_TXB 0x04000000
117 #define EMAC_IMASKT_RXF 0x02000000
118 #define EMAC_IMASK_RXB 0x01000000
119 #define EMAC_IMASK_MII 0x00800000
120 #define EMAC_IMASK_EBERR 0x00400000
121 #define EMAC_IMASK_LC 0x00200000
122 #define EMAC_IMASKT_RL 0x00100000
123 #define EMAC_IMASK_UN 0x00080000
125 #define EMAC_RCNTRL_MAX_FL_SHIFT 16
126 #define EMAC_RCNTRL_LOOP 0x00000001
127 #define EMAC_RCNTRL_DRT 0x00000002
128 #define EMAC_RCNTRL_MII_MODE 0x00000004
129 #define EMAC_RCNTRL_PROM 0x00000008
130 #define EMAC_RCNTRL_BC_REJ 0x00000010
131 #define EMAC_RCNTRL_FCE 0x00000020
132 #define EMAC_RCNTRL_RGMII 0x00000040
133 #define EMAC_RCNTRL_SGMII 0x00000080
134 #define EMAC_RCNTRL_RMII 0x00000100
135 #define EMAC_RCNTRL_RMII_10T 0x00000200
136 #define EMAC_RCNTRL_CRC_FWD 0x00004000
138 #define EMAC_TCNTRL_GTS 0x00000001
139 #define EMAC_TCNTRL_HBC 0x00000002
140 #define EMAC_TCNTRL_FDEN 0x00000004
141 #define EMAC_TCNTRL_TFC_PAUSE 0x00000008
142 #define EMAC_TCNTRL_RFC_PAUSE 0x00000010
144 #define EMAC_ECNTRL_RESET 0x00000001 /* reset the EMAC */
145 #define EMAC_ECNTRL_ETHER_EN 0x00000002 /* enable the EMAC */
146 #define EMAC_ECNTRL_MAGIC_ENA 0x00000004
147 #define EMAC_ECNTRL_SLEEP 0x00000008
148 #define EMAC_ECNTRL_SPEED 0x00000020
149 #define EMAC_ECNTRL_DBSWAP 0x00000100
151 #define EMAC_X_WMRK_STRFWD 0x00000100
153 #define EMAC_X_DES_ACTIVE_TDAR 0x01000000
154 #define EMAC_R_DES_ACTIVE_RDAR 0x01000000
156 #define EMAC_RX_SECTION_EMPTY_V 0x00010006
158 * The possible operating speeds of the MAC, currently supporting 10, 100 and
161 enum mac_speed {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS};
163 /* MII-related definitios */
164 #define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
165 #define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
166 #define EMAC_MII_DATA_OP_CL45_RD 0x30000000 /* Perform a read operation */
167 #define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
168 #define EMAC_MII_DATA_OP_CL45_WR 0x10000000 /* Perform a write operation */
169 #define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
170 #define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
171 #define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */
172 #define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
174 #define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
175 #define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */
176 #define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
177 #define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */
179 #define EMAC_MII_DATA_RA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \
180 EMAC_MII_DATA_RA_SHIFT)
181 #define EMAC_MII_DATA_PA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \
182 EMAC_MII_DATA_PA_SHIFT)
183 #define EMAC_MII_DATA(v) ((v) & 0xffff)
185 #define EMAC_MII_SPEED_SHIFT 1
186 #define EMAC_HOLDTIME_SHIFT 8
187 #define EMAC_HOLDTIME_MASK 0x7
188 #define EMAC_HOLDTIME(v) (((v) & EMAC_HOLDTIME_MASK) << \
192 * The Address organisation for the MAC device. All addresses are split into
193 * two 32-bit register fields. The first one (bottom) is the lower 32-bits of
194 * the address and the other field are the high order bits - this may be 16-bits
195 * in the case of MAC addresses, or 32-bits for the hash address.
196 * In terms of memory storage, the first item (bottom) is assumed to be at a
197 * lower address location than 'top'. i.e. top should be at address location of
198 * 'bottom' + 4 bytes.
200 struct pfe_mac_addr {
201 u32 bottom; /* Lower 32-bits of address. */
202 u32 top; /* Upper 32-bits of address. */
206 * The following is the organisation of the address filters section of the MAC
207 * registers. The Cadence MAC contains four possible specific address match
208 * addresses, if an incoming frame corresponds to any one of these four
209 * addresses then the frame will be copied to memory.
210 * It is not necessary for all four of the address match registers to be
211 * programmed, this is application dependent.
214 struct pfe_mac_addr one; /* Specific address register 1. */
215 struct pfe_mac_addr two; /* Specific address register 2. */
216 struct pfe_mac_addr three; /* Specific address register 3. */
217 struct pfe_mac_addr four; /* Specific address register 4. */
227 #define EMAC_HASH_REG_BITS 64
229 #define EMAC_SPEC_ADDR_MAX 4
231 #endif /* _EMAC_H_ */